← Back to: Supervisors & Reset
Why RF/Clock Rails Need Dedicated Supervisors
Target Scenario
REFCLK → PLL/VCO → LO / clock-tree. Highly sensitive to UV, OV, and slow drift.
Value Proposition
Phase-noise-friendly thresholds + clean reset outperform “just tighten ripple specs”.
Key Semantics
PG = “currently good”; FAULT = “was bad”. Keep them separate.
Design Rules
- UV:
V_UV ≥ V_hold + ΔV_margin(T)(covers temp drift, tolerance, wiring drops). - OV:
V_OV ≤ V_absmax − ΔV_headroom(avoid gate-oxide stress on VCO). - Single-threshold cases: prefer UV + hysteresis; if drift is significant, use Windowed.
Validation
Inject slow dips (10–200 ms), fast sags (hundreds µs), bounce (1–10 ms). Observe lock status and sidebands.
Records
Log unlock count, max unlock duration, and PG recovery latency.
Risks & Mitigations
- Tolerance too loose → use Windowed + independent hysteresis.
- Sampling/filtering injects noise → shorten RESET routing, fix pull-up domain and value.
Deliverable · Requirement Card
Fields: V_lock, V_hold, temperature range, ΔV_margin, Windowed(Y/N), counters(K-of-M).
Threshold Strategy for Phase-Noise-Sensitive Rails
Why Windowed & Hysteresis
Suppress long-term drift and avoid threshold chatter; keep PLL in the hold-in region.
Error Stack
Detector tolerance ±x% + divider error + temp coefficient ±ppm/°C + wiring drop.
Validation Target
False-trip rate < 1e−6 / hour over −40~+85 °C with 10^5 cycles.
Formulas & Coefficients
V_UV = V_hold + k1·σ_T + k2·ΔV_drop
V_OV = V_nom + k3·Ripple_pk + k4·σ_T
Default k1..k4 = 2~3 (≈99% coverage); refine with manufacturing data. Hysteresis: Hyst ≥ max(ΔV_noise_band, 1.5×ADC_LSB_equiv).
Risks & Mitigations
- Divider too large → migrate pull-up to a quieter domain and re-evaluate injection.
- Window overlapping PLL hold-in → align with device team’s hold-in/lock-in data.
Deliverables
Threshold budget table: V_nom, V_hold, σ_T, ΔV_drop, Ripple_pk, k1..k4, Hyst, tolerance %.
Reset Pulse Shaping & Debounce for PLL/VCO Domains
Keep reset edges clean (no slow tails), size a one-shot wide enough to guarantee re-lock, and reject micro-glitches without adding jitter-sensitive RC delays.
One-Shot Sizing
t_RST = max(t_lock_min + 20%, 1 ms). Margin covers cold start and low-temp oscillator slow rise.
Glitch Filter
Use digital K-of-M or <1 ms windows; avoid long RC which softens edges.
Output Type
Mixed-voltage boards → OD (open-drain) pulled up to the target domain. Single domain → PP (push-pull) is acceptable.
Design Rules
- Recommend
K/M = 2/3or3/5; voting window100–500 µs. - OD pull-up to the reset target domain; choose
R_pull-upsot_rise ≤ 100 µswith minimal injection. - Record both
t_riseandt_fallagainst JESD/internal limits.
Validation & Manufacturing
- At −40 °C, measure re-lock time distribution; use P95/P99 to set margins.
- Exercise sparse spikes vs. clustered spikes inside the voting window.
Risks & Mitigations
- PP across domains → back-power risk → switch to OD + correct pull-up domain.
- RC debounce → slow edges → replace with digital K-of-M or a hardware debouncer.
Deliverables
Reset timing table (t_lock_min, t_RST, t_rise, t_fall), K-of-M config (K, M, window), pull-up domain & resistor list.
Sequencing with Clock Tree (REFCLK → PLL → RF LO)
Enforce a one-way order—source → lock → derived—by aggregating PG (AND semantics) and fanning out reset. Prefer controlled degradation (hold REFCLK) over hard cut-off on power-fail.
PG Aggregation & Truth
Use AND: PG_REFCLK ∧ PG_PLL ⇒ RST_LO_release. Keep PG=present good and FAULT=past bad on separate lines.
Reset Tree & Fanout
Upstream PG gates downstream reset-enable. Add micro-stagger +0.2–0.5 ms per branch to avoid bursts.
Degraded Mode
On power-fail, hold REFCLK and limit derived outputs. Tag events for later diagnostics.
Validation Scenarios
- A: REFCLK instability only
- B: PLL dip only
- C: LO load step
Checks
No false relock resets; consistent PG→reset fanout delays across branches.
Risks & Mitigations
- Race conditions → add minimum-hold and verify with a dependency graph.
- Fanout storm → stagger release or tiered gating.
Deliverables
Sequencing dependency diagram (swimlanes) and a PG/Reset truth table (copyable).
Noise-Safe Integration Patterns
Place the supervisor with respect to PLL/VCO to keep phase-noise and jitter intact: pull up into the reset target domain, keep short return paths, and treat long traces with small series damping and via fences.
Pull-Up Domain
Reset output uses OD; pull up to the target domain to avoid cross-domain back-power. Prefer OD over level shifters for 1.8 V↔3.3 V crossings.
Return Path & Loop
Keep Reset and its return on the same layer with a short loop, hugging the reference ground; avoid crossing sensitive loops.
Long Trace Treatment
For long runs, add 22–100 Ω series damping close to source or mid-point and build a GND via comb near corners/changes of direction.
Design Rules
- Pull-up sizing: balance
t_rise ≤ 100 µs(clean edges) vs minimal injection; start with 10–47 kΩ and tune with measured line capacitance. - Level map: if 1.8 V/3.3 V cross, use OD + pull-up to target domain; avoid dedicated level translators unless mandatory.
Validation & Manufacturing
- Reset-tip injection: add small pulses near the reset pin; target phase-noise delta < 0.2 dB (app-specific).
- EMI scan: 150 kHz–30 MHz, compare with/without supervisor enabled.
Risks & Mitigations
- Slow reset edges → lower R or pull up to a higher rail (then re-check injection).
- Ground return cuts through sensitive loops → move layers / add via-fence for shorter return.
Deliverables
Level-Domain map, pull-up value & placement, series resistor spec and locations.
Tele-PG/FAULT Semantics & Logging Hooks
Make diagnosis easy without disturbing clock quality: keep PG (present good) and FAULT (past bad) semantics strict, provide minimal counters/timestamps, and throttle any telemetry that could touch the reference domain.
Semantics
PG = present good (instantaneous). FAULT = past bad (latched/counted). Keep polarity/hold strategies documented and consistent.
GPIO-Only
PG pulled up to the target domain. FAULT uses latch with manual/command clear. Wire separately to avoid coupling loops.
I²C/PMBus
Read back counters, thresholds, last state. Prefer interrupt-driven reports or throttled polling to avoid reference-domain stress.
Design Rules
- Events: power-loss count, max outage duration, last timestamp (no RTC → “relative ticks + boot index”).
- Safety island: one-way sideband only; avoid feedback loops between PG and FAULT paths.
Validation & Mfg Checks
- Inject N dips/slow drifts; verify counter and timestamp integrity/readability.
- After remote FW update, re-validate semantic invariants (polarity, fields, clear path).
Risks & Mitigations
- PG meaning drift (“past good” vs “present good”) → fix wording on the BOM note and design doc.
- Over-polling → throttle or switch to interrupt-based reporting.
Deliverables
PG/FAULT semantics table; optional register map and recommended report cadence.
Layout & Validation for Low-Jitter Outcomes
Freeze a repeatable checklist and validation script so that board changes do not degrade PLL/VCO phase noise and jitter. Keep Reset short, near the reference ground, avoid VCO loops, pair vias across layers, and verify with AB spectra.
Layout Checklist (extract)
- Reset trace hugs REF-GND; shortest loop, same-layer return.
- Pull-up near target, OD to target domain, no level shifter unless mandatory.
- Paired vias for layer transitions; no GND splits between source and target.
- Long runs: 22–100 Ω series damping + GND via-fence at corners.
- Avoid routing across VCO/loop filter keep-out region.
Validation Playbook
- Phase-noise offsets: 10 Hz–1 MHz; AB with supervisor enable/disable.
- Power scripts: normal, brown-out, slow-ramp, rebound; log PG→Reset fan-out skew.
- Minimum reproducible corner: single-rail injection, known line C/R, fixed temp points.
- Worst boundary: extreme temp, longest line, max ripple, highest coupling.
Acceptance Gates
- Δ phase-noise (enable vs disable) ≤ 0.2 dB.
- Reset fan-out end-to-end jitter ≤ 0.1 ms (project-tuned).
- Automate: golden scripts run on every layout ECO.
BOM & Procurement Notes
| Field | Required | Notes / Example |
|---|---|---|
| V_rail | Yes | e.g., 1.8 V RF/PLL |
| n_rails | Yes | Number of supervised rails |
| Threshold tolerance (±%) | Yes | Match V_hold / V_lock budget |
| Latch / One-shot | Yes | Reset pulse strategy |
| Output type (OD/PP) | Yes | OD preferred for mixed domains |
| AEC-Q100 (Y/N) | Yes | Automotive grade if required |
| Package height (mm) | Yes | Clearance vs shield/cans |
| Second-source (Y/N) | Yes | If Y, provide pin/semantics map |
| I²C/PMBus (Y/N) | Optional | Telemetry/config channels |
| PG/FAULT semantics | Optional | PG=present-good; FAULT=past-bad |
| Tamper/Zeroize hooks | Optional | If security interlocks exist |
| dV/dt requirements | Optional | Ramp limits for safe lock |
Risks & Mitigations
- Pin/semantics mismatch → publish fixed PG/FAULT table with polarity/hold.
- EOL/PCN → shortlist alternate families across brands in advance.
- Sample lead-time / MOQ → pre-agree phased lots or package alternatives.
CTA
Send your rail details and constraints for a 48-hour cross-brand recommendation.
Submit your BOM (48h)Cross-Brand Shortlist (Family-Level; RF/Clock Rails)
Families below are well-suited to REFCLK/PLL/VCO rails where tight UV/OV thresholds, clean RESET edges, and PG/FAULT semantics matter. Example part numbers (PNs) are placeholders for evaluation; confirm AEC-Q100 status, package height, and supply before purchase.
Texas Instruments
- TPS3702-Q1 (windowed; OD/PP). Why: independent UV/OV with hysteresis maps neatly to PLL hold-in/lock-in zones; quiet edges for low-jitter domains.
- TPS3890-Q1 (single-threshold; delay options). Why: high accuracy UV with configurable one-shot width suits “UV+Hyst first” policies.
- TPS3703-Q1 (windowed). Why: clean PG vs RESET separation simplifies “PG=present-good / FAULT=past-bad”.
- Example PNs: TPS3702AQDSFRQ1, TPS3890AQDBVRQ1, TPS3703AQDDFRQ1.
STMicroelectronics
- STM706/STM708 (single-th; manual reset pin; OD/PP). Why: classic low-noise reset; pair with digital K-of-M for glitch rejection.
- STM6719 (windowed; watchdog combo). Why: window + hysteresis covers slow drift and rebound events.
- STM1001/STM1005 (ultra-low Iq). Why: lean UV guardrail when budget is tight.
- Example PNs: STM706RP, STM708RP, STM6719S, STM1001R.
NXP
- FS26xx (SBC; multi-rail monitors; AEC-Q100). Why: PG aggregation and sequencing for multi-PLL trees.
- FS84/FS85 (multi-rail). Why: supervised power with degraded-mode policies for complex RF clocking.
- Example PNs: FS26B0, FS8500, FS8400 (family placeholders; pick rail set per SKU).
Renesas
- ISL88014/015/016 (accurate reset; OD/PP). Why: fine threshold bins + delay options align with
t_RST = t_lock_min×1.2. - ISL88002/003 (micro-power detector). Why: minimal Iq for sensitive RF rails.
- Example PNs: ISL88014IH31Z-T, ISL88016IH31Z-T, ISL88002IH31Z-T.
onsemi
- NCV301/302 (accurate single-th; AEC-Q100). Why: stable RESET edges; wide threshold catalog.
- NCV303/304 (with delay/variants). Why: fixed one-shot for deterministic re-lock.
- NCV809/810 (ultra-low Iq). Why: quiet baseline UV guard.
- Example PNs: NCV301LSN30T1G, NCV302LSN29T1G, NCV303LSN30T1G, NCV809SN20T1G.
Microchip
- MCP1316/MCP1317 (delay + polarity options). Why: flexible one-shot matching PLL cold-start statistics.
- MCP809/MCP810 (low Iq; AEC-Q100 options). Why: simple UV with tight tolerance for clock rails.
- Example PNs: MCP1316T-29LE/CHY, MCP1317T-29LE/CHY, MCP809T-315I/TT, MCP810T-315I/TT.
Melexis
- MLX81116/81115 (LIN node controllers w/ supply monitor). Why: local domain monitoring where RF/clock lives inside a LIN slave; not for primary PLL rail.
- MLX81112/81113 similar note—use only for subordinate domains; document semantics.
- Example PNs: MLX81116KAE, MLX81115KAE (scope-qualified).
Migration Tips
- Single-threshold + hysteresis: TI TPS3890-Q1 ⇄ onsemi NCV301/302 ⇄ Microchip MCP809/810 ⇄ Renesas ISL88014. Verify polarity, OD/PP, and delay bin.
- Windowed UV/OV: TI TPS3702-Q1 ⇄ ST STM6719 ⇄ Renesas multi-bin variants. Align windows to hold-in and lock-in regions.
- Multi-rail sequencing: NXP FS26/FS84/85 for PG aggregation; document “PG=present-good / FAULT=past-bad”.
Frequently Asked Questions
What UV/OV margins are safe for PLL/VCO rails without triggering false unlocks?
Start from measured V_hold and V_lock. Set UV ≥ V_hold + σ(T,line) and OV ≤ V_absmax − headroom. Add hysteresis ≥ max(noise band, 1.5× ADC-LSB-equiv). For typical 1.8-V rails this yields 3–6% UV margin and 5–8% OV headroom, tuned by temperature and ripple statistics.
How wide should the reset one-shot be to guarantee re-lock across cold starts?
Use t_RST = max(t_lock_min × 1.2, 1 ms), then verify at −40 °C with cold oscillator statistics. Maintain fast edges (avoid large RC tails) and prefer open-drain pulled to the target domain. Document t_RST@temp distribution and re-lock success rate over 1e3 cycles.
When is a windowed supervisor better than a single-threshold detector for drift?
Choose windowed UV/OV when the PLL’s hold-in and lock-in regions are distinct or when slow thermal drift and rebound spikes both matter. Independent hysteresis lets you widen the OV band to protect gate oxide while keeping UV tight to avoid false unlocks on marginal rails.
Open-drain or push-pull RESET on mixed-voltage clock boards?
Prefer open-drain with a pull-up to the target domain to avoid back-powering and level-mismatch currents. Use push-pull only inside a single voltage island with guaranteed compatibility and short routes. Size the pull-up so rise time ≤ 100 µs while keeping injection low.
How to filter micro-glitches without adding jitter-sensitive RC tails?
Use digital K-of-M voting (e.g., 2/3 in 100–500 µs windows) or the supervisor’s internal debounce rather than large RC constants. Keep edges sharp; add a small series resistor (22–100 Ω) for long runs and maintain a solid return path close to reference ground.
How to aggregate PG for multi-PLL trees and avoid sequencing races?
Build an AND-style aggregator where upstream PG releases downstream resets. Add minimum-hold timers to mask brief wobble after enable. Fan-out resets through matched delays to keep skew tight, and document a dependency graph so ECOs can be checked by scripts automatically.
Can I time-stamp power-fail events without a secure RTC?
Yes. Store relative ticks + boot index (e.g., uptime counter and monotonic event ID). Capture “last outage length” and occurrence count, and throttle reporting via interrupt or sparse polling. If authenticity matters, sign batches later using a host secure element.
What debounce/majority-vote schemes reduce spurious trips on RF rails?
Use majority voting like 2/3 or 3/5 with sub-millisecond windows tuned to the rail’s noise spectrum. Combine with windowed thresholds and independent hysteresis. Avoid RC tails; keep RESET edges crisp and place pull-ups near the target domain input.
How to validate that supervision didn’t worsen phase noise/jitter?
Run A/B spectra (supervisor enabled vs bypassed) across 10 Hz–1 MHz offsets. Acceptance: ΔPN ≤ 0.2 dB and reset fan-out jitter ≤ 0.1 ms. Repeat at temperature corners and worst-case ripple. Lock results in a “golden script” for post-layout regression.
Where to place pull-ups so RESET edges stay clean yet quiet?
Place the pull-up in the target voltage island, physically close to the receiving pin. Size R to meet rise-time targets without injecting excess current; route alongside a solid return and avoid crossing VCO/loop-filter regions. Add 22–100 Ω series damping on long traces.
How tight must threshold tolerance be vs PLL hold-in region over temp?
Budget the stack: detector accuracy, divider error, temp drift, and line drop. Keep the UV setpoint inside hold-in with ≥ 3σ margin over temperature. If tolerance pressure is high, move to a windowed supervisor so UV remains tight while OV protects oxide against spikes.
What’s the safest degraded-mode if REFCLK is good but VCO rail dips?
Prefer a controlled degrade: keep REFCLK alive, hold downstream clocks in reset, and log a FAULT with duration. Release only after rail recovery and re-lock confirmation. Avoid hard cut-off unless oxide/EM concerns demand it; communicate status via PG aggregation.
