← Back to: Supervisors & Reset
What It Solves
Map hard-to-see yet fatal imaging artifacts to controllable power-supervision strategies and measurable acceptance: UV/OV windows, programmable delay/debounce, soft clamp / controlled discharge, multi-rail PG aggregation, and safe OD/PP semantics.
Cold/Resume Black-Level Jump
VREF/VCM stabilize first + tPG_filter ≥ 0.5–1 ms + keep-bias soft clamp.
Row Banding / FPN on Power-Up
AVDD controlled ramp; DVDD after analog; avoid half-powered sampling.
Thermal Black-Level Drift
Narrow VREF/VCM windows + ppm/°C margin; validate across −40~+85 °C.
False PG / Back-Power
OD outputs, proper pull-up rail, fanout buffering; PG aggregation with first-fault tagging.
Acceptance (examples):
- ΔBlack-Level@resume ≤ 2 LSB (25 °C); ≤ 4 LSB at 85 °C
- FPN RMS ≤ baseline + 10%
- Sleep→Stable resume time ≤ 5 ms (with VREF/VCM kept)
- Re-reset events ≤ 10 ppm (ramp + brownout scripts)
Rails & Bias Map for Imager/AFE
Recommended order: VREF/VCM first → AVDD next → DVDD last. Set narrow windows for references, controlled discharge for analog, and allow faster discharge for digital with proper debounce.
| Rail | Window % | Thermal Margin | tPG / Debounce | Discharge Policy | Output (OD/PP) | Pull-up Rail | Notes |
|---|---|---|---|---|---|---|---|
| VREF | ±1.5–2% | ≥ 30–50 ppm/°C | tPG ≥ 2 ms | keep (no fast) | OD | always-on ref | Bias conservation across sleep |
| VCM | ±2% | ≥ 50 ppm/°C | tPG ≥ 1.5 ms | keep (no fast) | OD | reference domain | Common-mode for sensor black level |
| AVDD | ±5% | ≥ 100 ppm/°C | tPG ≥ 1 ms | slow-discharge | OD/PP (same domain) | analog rail | Control dV/dt to avoid sampling artifacts |
| DVDD | ±8–10% | ≥ 150 ppm/°C | tPG ≥ 0.5–1 ms | fast-allowed | OD (mixed domains) | digital or IO rail | Debounce stronger to mask bus chatter |
| VANA* | ±3–4% | ≥ 80 ppm/°C | tPG ≥ 1–1.5 ms | slow-discharge | OD/PP per domain | analog/ISP domain | Project-specific analog sensitive rail |
Soft Clamp & Controlled Discharge
Use keep-bias + slow discharge to avoid black-level re-calibration; allow faster discharge on digital rails when paired with stronger debounce. Default policy: VREF/VCM = keep, AVDD = slow, DVDD = fast-allowed.
Strategy Matrix
{VREF, VCM, AVDD, DVDD} × {keep / slow / fast / cut}. Default highlights emphasize bias conservation.
Discharge Path
External FET with controlled Rds(on) and time window; avoid rapid collapse of references.
Sleep/Resume
Keeping VREF/VCM reduces resume calibration from ms to µs; capture Δblacklevel_resume as KPI.
Engineering: t_discharge, Rds(on), E_hold, I_leak_total, Δblacklevel_resume; abnormal power-loss → “limit current + keep bias” hook.
Power-Up Order & PG/RESET Semantics
Turn the slogan “reference → analog → digital” into a repeatable recipe: OD-first across mixed domains, PP only within same-level fanout; aggregate PG with first-fault/last-good tagging; apply debounce to tolerate slow ramps.
Recipe: tPG(VREF)=2 ms → tEN(AVDD)=+1 ms → tEN(DVDD)=+2 ms; tPG_filter ≥ 0.5–1 ms; tPW_reset_min per MCU (50–200 µs typical).
Parameters: tPW_reset_min, tPG_valid_min, I_fanout, R_pull, C_filter, dV/dt. Unify active-low/high via small adapter board if mixed; ensure pull-up rail is always present to avoid false PG.
Back-Power & Level Domains
Identify back-power paths created by long harness/FPC and shared pull-ups, then design fan-out buffering and level compatibility to eliminate false stability and half-powered states.
Back-Power Paths
Pull-ups tied to always-on rails, input clamp diodes/ESD arrays, oversized series resistors causing slow charge “fake-PG”.
Fanout & Level
Budget PG fanout current; OD across mixed domains; buffer or translate levels; pick a pull-up rail that is always present.
Test Hooks
Pluggable/shortable pull-ups; I–V back-power sweeps to locate knee points; DVDD-off with VREF/VCM-kept A/B.
| Parameter | Guideline | Notes |
|---|---|---|
| I_backpower_max | ≤ 10% standby budget | Measure with DVDD off, references kept |
| R_series (IO/PG) | 100–470 Ω (typ.) | Coordinate with pull-up and ESD model |
| OD pull-up rail | Always-on, level-compatible | Avoid DVDD-only in sleep paths |
| PG fanout budget | I_fanout ≤ Σ I_sink_node (≥30% margin) | Buffer if wiring is long or multi-drop |
Validation & Tuning
Turn “feels stable” into a data-closed loop: ramp spectra, temperature cycling, sleep-resume A/B, and EMI/glitch immunity, with reproducible KPIs for acceptance.
Ramp Spectrum
0.1/0.5/1/2/5 V/ms; log false-PG, re-reset, start-up jitter.
Temperature Cycling
−40/−10/25/60/85 °C; track black-level curve, FPN RMS, t_resume_s2s.
Sleep A/B
Keep VREF/VCM vs full-off; compare re-calibration cost and noise floor.
EMI/Glitches
Reuse ramp/instant-brownout scripts; validate tPG_filter adequacy.
| Metric | Target (example) | Notes |
|---|---|---|
| Δblacklevel_85C (LSB) | ≤ X | Curve vs temperature |
| FPN_RMS (LSB) | ≤ Y | Row/column fixed pattern |
| t_resume_s2s (ms) | ≤ Z | Sleep→stable black level |
| Re-reset / False-PG (ppm) | ≤ 10 / ≤ 5 | Ramp + transient scripts |
Tuning: If false-PG is high → increase tPG_filter, move OD pull-up, add buffer/RC. If ΔBL/FPN exceed targets → tighten VREF/VCM windows, delay DVDD enable, limit dV/dt(AVDD). If resume time is long → keep references or adjust post-reset wait. If back-power is noticeable → raise R_series, add one-way elements/isolation, choose an always-on pull-up rail.
Cross-Brand Shortlist (Procurement-Oriented)
Directional candidates for Imager/AFE rails (VREF/VCM/AVDD/DVDD). Final PNs must match your inventory/BOM to avoid guesswork. Focus on window/threshold accuracy, delay/debounce, OD/PP output strategy, and cooperation with controlled discharge.
| Brand | Part / Family | Rails (n) | Window / Delay / Debounce | Output (OD/PP) | Discharge Control | Why It Fits Imager/AFE | Docs |
|---|---|---|---|---|---|---|---|
| TI |
TPS3851-Q1 (high-accuracy + watchdog) TPS386596 (quad-rail supervisor) |
1 / 4 | Tight UV thresholds, selectable reset/WDT delays; quad version supports fixed or divider-set windows | OD preferred across mixed domains; PP available in family | Use external FET + timing for controlled discharge/soft clamp | Narrow windows for VREF/VCM, watchdog-friendly RESET tree, and multi-rail aggregation to gate AVDD/DVDD cleanly. | TPS3851-Q1 · TPS386596 |
| ST |
STM6717/18/19/20 (multi-rail + manual reset) STWD100 (stand-alone watchdog) |
2–3 / — | Fixed thresholds, robust reset timing; WDT timeouts selectable | OD or PP by variant | Pair with external FET for slow/fast discharge policies | Practical for splitting VREF/AVDD monitoring and keeping a human-reset path; WDT decouples from PG aggregation to avoid false stability. | STM6717 · STWD100 |
| NXP |
PF5020 (multi-rail PMIC, integrated PGOOD/RESET) VR5510 (automotive multi-output PMIC) |
≥5 (PMIC) | Built-in power-up sequence, OV/UV monitors, synchronized PGOOD/RESET masking | PGOOD/RESET pins; translate to OD/PP if needed | Coordinate with external soft-clamp/discharge switch | If rails are PMIC-sourced, reuse its native supervisors to reduce discretes and lock a consistent RESET release point for black-level stability. | PF series · VR5510 DS |
| Renesas |
ISL88022 (configurable 3-rail) ISL88013 (dual: one fixed + one adjustable) |
3 / 2 | Adjustable thresholds, selectable reset delays; valid at low V | PP/OD by option (see DS) | External discharge path | Bind VREF/AVDD/DVDD with different window widths and release delays in one device; reduce re-calibration across temperature. | ISL88022 · ISL88013 |
| onsemi |
NCV809 (ultra-low IQ single-rail) NCV303 (OD, programmable delay) |
1 / 1 | Fixed thresholds; NCV303 adds delay to reject slow-slope glitches | OD (preferred across domains); PP on some variants | External controlled discharge | Cost-effective guards for DVDD/IO with long harness/FPC; easy to aggregate into a unified RESET tree. | NCV809 · NCV303 |
| Microchip |
MCP1316 (single-rail, wide temp) MIC2775 (single-rail, dual PP outputs, MR pin) |
1 / 1 | Fixed thresholds; typical 280 ms reset (device-dependent); manual reset support | PP; OD available in family options | External soft-discharge with FET | Good for narrow-window, long-debounce guarding near VREF or AVDD with minimal disturbance; MIC2775’s dual PP eases RESET fan-out. | MCP1316 · MIC2775 |
| Melexis | — (no dedicated supervisor family) | — | — | — | — | In imaging programs typically paired with the supervisor/PMIC options above; keep system-level compatibility only. | — |
- Automotive: prefer -Q1 / AEC-Q100 variants where available; keep same package/codes for drop-in alternates.
- Outputs: OD across mixed/long domains; PP allowed only within same-level short fan-out.
- Discharge: most supervisors lack integrated controlled discharge—pair with eFuse/load switch or external FET for soft-clamp policies.
BOM & Procurement Notes
Required Fields
V_rail (VREF/VCM/AVDD/DVDD…), n_rails, threshold tolerance/window, t_delay/debounce, discharge policy (off/slow/fast), output (OD/PP), AEC-Q100, package height, second-source (Y/N).
Optional Fields
I²C/PMBus, PG/FAULT semantics, back-power notes, dV/dt requirements, temperature coefficients, production test hooks (ramp/thermal/sleep A/B).
Risks & Mitigations
- Pin/semantics mismatch → adapter board (OD↔PP or polarity), RESET-tree decoding.
- EOL/NRND → dual-source plan and transition BOM; keep package/thresholds aligned.
- Sample lead time / MOQ → lock samples early (same lot if possible) and keep drop-in alternates.
FAQs
Why is black level highly sensitive to power-up order?
Should VREF/VCM be retained in standby or powered down?
Soft clamp vs fast discharge FET—how do I choose?
On mixed-voltage boards, is OD or PP safer for PG?
How much temperature margin do window thresholds need?
How do I prove slow ramps don’t false-trigger?
How do I tag first-fault/last-good in multi-rail PG without chatter?
How do I quantify black-level step after standby and set a pass line?
How do I locate and isolate back-power from long cables or FPC?
How do I migrate from single-rail to multi-rail windowing without a respin?
When is I²C programmability mandatory instead of fixed hooks?
What AEC-Q100 and PPAP pitfalls affect supervisors in automotive projects?
Need help mapping rails, policies, and parts for your camera board? Submit your BOM (48h).
