Threshold & Tolerance in Supervisors: Accuracy & Drift

Q: How do IC accuracy, divider tolerance and temp drift combine into a single threshold budget?

Treat contributors as independent and combine statistically: σ_total ≈ √(σ_ic² + σ_divider² + σ_temp² + σ_leak²). Convert to a spec using Tol_total(%) ≈ (3·σ_total / V_TH)×100%. For windowed parts, compute upper and lower budgets separately. Align assumptions with your divider TCR, ΔT and leakage model so procurement and validation share the same baseline.

Q: What hysteresis is “just enough” for slow ramps and 20–50 mV ripple?

Start with ΔV_HYS ≥ max(1.5×V_pp, S·t_blank). With 20–50 mV of ripple, practical hysteresis is often 30–80 mV depending on slew and delay. Verify by ripple injection at 50–200 kHz near V_TH and confirm no chatter. Avoid excessive hysteresis that masks real faults or compresses a window supervisor’s usable range.

Q: When should I pick ±1% vs ±1.5% accuracy in automotive rails?

Choose ±1% when the system budget is ≤±2% or when windows are tight and recovery behavior is critical. If noise, temperature spread or divider drift dominate and hysteresis can be larger, ±1.5% is often sufficient. Consider availability and second source. Document the budget so the alternative device can meet the same combined tolerance target.

Q: How do I size the divider to limit leakage error on a 1 MΩ-class input?

High impedance amplifies leakage and measurement loading. Use R_total in the 200–500 kΩ range for automotive supervisors, with same-series thin‑film resistors and TCR ≤100 ppm/°C. Estimate offset as ΔV ≈ I_leak × R_eq at the sense node. Validate by A/B measurement with the ADC or ESD network connected and disconnected.

Q: Does OTP-fixed threshold beat I²C-programmable for stability and spread?

OTP-fused thresholds provide excellent lot‑to‑lot consistency and no boot‑time dependency. I²C programmability adds flexibility for late tuning but needs safe defaults, CRC and configuration timing controls. For volume builds or second source, OTP often simplifies spread control. Whatever you choose, re‑verify trip and return after programming or fuse options.

Q: How do I verify window supervisor limits across −40~+125 °C?

Use chamber points at −40, 25, 85 and 125 °C with ≥10 minutes soak per point. Record trip and return distributions for each window, over at least ten cycles per unit. Accept when μ_gap − 3·σ_gap ≥ ΔV_HYS + margin or Cpk ≥ 1.33. Confirm no overlap or dead zone exists across the full temperature range.

Q: What blanking/delay avoids chatter on pre-biased rails?

Set hysteresis first, then choose t_blank so S·t_blank ≤ ΔV_HYS/2 for the worst‑case slew. As a starting point, 50–200 μs covers many MCU and PMIC rails. Validate by injecting power‑on spikes and pre‑bias conditions. Ensure the delay does not mask genuine brown‑out events or violate your reset tree dependencies.

Q: How do I translate spec ppm/°C into mV shift on a 5 V rail?

Use ΔV(mV) = V × (ppm/1e6) × ΔT(°C) × 1000. Example: 5 V with 100 ppm/°C over 100 °C yields 50 mV expected drift. Apply this to both the IC reference and divider TCR. Sum statistically when sources are independent and check that the total remains inside your threshold budget.

Q: Can I reuse the same divider for ADC sense and supervisor without skew?

Yes, but include ADC input leakage, sampling kickback and any ESD or protection branch currents. Either buffer the ADC, lower R_total or split the node with defined resistors. Quantify the added error as ΔV ≈ I_leak × R_eq and verify by A/B measurements. Keep the measurement bandwidth from disturbing the supervisor comparator.

Q: What’s a safe acceptance criterion for small-batch validation (n=10~30)?

Use P(out‑of‑spec) < 0.13% (approximately 3σ) or Cpk ≥ 1.33 as your pass line. Report n, mean and standard deviation with confidence bands. Cycle each unit at least ten times per condition. Maintain identical metrology across ramp, ripple and temperature tests so your statistics remain comparable.

Pain Points & Objectives

Typical Symptoms

Chatter on slow ramps or fine ripple; false trips at upper/lower windows; cross-season threshold drift. Measured trip points off datasheet spec; long-term drift from divider leakage/TCR.

Root-Cause Frame

IC accuracy (@25 °C vs full-temp) + divider tolerance/TCR + leakage loading + temp drift + insufficient hysteresis.

You Will Achieve

Build a total threshold budget; size ΔV_HYS and t_blank from ripple V_pp and slew S; follow a validation recipe; fill BOM required fields.

Target tolerance: Tol_total ≤ ±2%   ·   Minimum hysteresis: ΔV_HYS ≥ max(1.5×V_pp, S·t_blank)
Acceptance: P(out-of-spec) < 0.13% (≈3σ) or Cpk ≥ 1.33
BOM (preview): V_rail / n_rails / threshold tolerance (%) / hysteresis strategy / AEC-Q100 / Second-source (Y/N)

Key Terms & Measurements

Thresholds

V_TH: trip threshold (specify up/down if distinct). ΔV_HYS: return-to-trip gap to prevent chatter.

Accuracy & Drift

Tol@25 °C vs Tol@−40~125 °C; T_C in ppm/°C for IC ref/comparator and divider resistors.

Dynamic Conditions

S = dV/dt (slew near threshold), V_pp (local ripple), t_blank (blanking/delay).

ppm → mV:  ΔV (mV) = V × (ppm/1e6) × ΔT(°C) × 1000
Example: 100 ppm/°C, ΔT = 100 °C, V = 5 V → ΔV ≈ 50 mV

Hysteresis margin:  M = ΔV_HYS / V_pp
Rule of thumb:  M ≥ 1.5; add S·t_blank for slow ramps.

Error Stack-Up Model

Combine independent contributors in variance to form a single threshold budget: σ_total ≈ sqrt(σ_ic² + σ_divider² + σ_temp² + σ_leak²), then map to design tolerance: Tol_total(%) ≈ ±3·σ_total / V_TH × 100% (3σ example). Aim for Tol_total ≤ your design ceiling (e.g., ±2% or ±3%).

Accuracy Class	ΔT (°C)	σ_ic	σ_temp	σ_divider	σ_leak	Tol_total (%)	Result
±0.9% (@25 °C / full-temp)	65	…	…	…	…	…	✓ / ×
±1.5% (@25 °C / full-temp)	85	…	…	…	…	…	✓ / ×
±2.5% (@25 °C / full-temp)	125	…	…	…	…	…	✓ / ×

Divider Design & Leakage Impact

Sense ratio: V_SENSE = V_IN · R2/(R1+R2). Linearized propagation: ΔV/V ≈ sqrt(ΔR1² + ΔR2²)/(R1+R2). Include TCR via an equivalent α_eqR term. Choose R_total in the 100 k–1 MΩ span (automotive often 200–500 kΩ) to balance power, noise pickup, and leakage sensitivity. Model ADC/ESD/protection as parallel leakage branches and evaluate bias on V_TH.

R_total (kΩ)	TCR (ppm/°C)	I_leak (nA)	ΔV/V (%) @25 °C	ΔV/V (%) @Full-Temp	Rating
150	25	0	…	…	Recommended
300	50	50	…	…	Caution
600	100	200	…	…	Avoid

Layout tips: place R1/R2 adjacent with same series & TCR, short return path, guard the sense node, avoid switch-node coupling.
A/B test: measure V_TH with leakage branches connected vs. isolated; repeat across −40/25/85/125 °C.

Hysteresis Sizing & Anti-Chatter

Size hysteresis from local ripple and slew near threshold: ΔV_HYS ≥ max(1.5×V_pp, S·t_blank). For automotive rails, a 1–3% · V_nom range is common. Pair with delay/blanking to suppress pre-bias and power-on spikes. If larger ΔV_HYS is required, consider programmable-hysteresis supervisors or an external positive-feedback network.

Basic rule:  ΔV_HYS ≥ max(1.5 × V_pp, S × t_blank)
Automotive guide:  ΔV_HYS ≈ 1–3% · V_nom
Window check:  V_upper − V_lower ≥ ΔV_HYS + margin
Trade-offs:  Excessive ΔV_HYS → slow return; too much t_blank → delayed fault reporting

V_pp (mV)	S = dV/dt (V/s)	ΔV_HYS (mV / %·V_nom)	t_blank (μs / ms)	Use Case	Notes
10	0.1	≥15 mV (~0.3% @5V)	≥100 μs	Clean rails	Small ΔV_HYS OK; verify return time
30	0.3	≥45 mV (~0.9% @5V)	≥200 μs	Typical automotive	Good compromise; start here
100	1.0	≥150 mV (≥3% @5V)	≥0.5–1 ms	Noisy & slow ramps	Prefer programmable ΔV_HYS + explicit blanking

Caution: Oversized ΔV_HYS compresses window range and can delay recovery; check V_upper − V_lower margin and reset-tree dependencies.

Temperature Drift & Aging

Budget temperature effects from IC reference/comparator and divider TCR using: ΔV_temp ≈ V_TH · (α_ic + α_eqR) · ΔT (ppm→ratio). Validate at extreme corners (−40/125 °C) that the threshold band does not cross UVLO/POR functional limits. For aging/humidity, reserve extra ±x% or shift part of the budget to tighter divider/TCR or slightly higher ΔV_HYS.

Temp drift:  ΔV_temp ≈ V_TH · (α_ic + α_eqR) · ΔT
ppm → ratio:  α = (ppm_per_degC / 1e6) × ΔT
Example: 100 ppm/°C · 100 °C · 5 V → ΔV ≈ 50 mV
Corner check:  {−40, 25, 85, 125} °C → measure trip/return; keep minimum margin to UVLO/POR ≥ target
Aging allowance:  add ±x% budget or tighten TCR and R_total, then re-verify ΔV/V and ΔV_HYS

Validation plan (n=10–30):  measure trip/return at −40/25/85/125 °C → derive σ vs T; 
compare threshold band to UVLO/POR limits; apply aging allowance ±x% and re-verify.

Window Supervisor: Upper/Lower Threshold Balancing

Balance the window so that combined tolerances and hysteresis don’t create overlaps or dead zones: WCS (worst case) requires V_upper,min − V_lower,max ≥ ΔV_HYS + margin. In statistical terms, verify μ_gap − k·σ_gap ≥ ΔV_HYS + margin (typically k=3). Prefer devices whose upper/lower thresholds share the same reference for drift synchronization; otherwise bias the system so the upper window is more conservative and the lower window more tolerant.

WCS check:  V_upper,min − V_lower,max ≥ ΔV_HYS + margin
Stat check:  μ_gap − k·σ_gap ≥ ΔV_HYS + margin   (k ≈ 3)
Sync drift:  Prefer shared reference; else set Upper more conservative / Lower more tolerant
Coupling:    If ΔV_HYS increases → widen (V_upper − V_lower) accordingly

V_upper_nom	V_lower_nom	ΔV_HYS	Tol_upper (%)	Tol_lower (%)	α_ic / α_eqR	μ_gap	σ_gap	k	μ_gap − k·σ_gap	Result
…	…	…	…	…	… / …	…	…	3	…	✓ / ×

Validation Recipe & Acceptance Criteria

Execute four tracks—Slow Ramp, Ripple Injection, Temperature Sweep, and Blanking/Delay. For each, capture trip/return distributions across samples (n=10–30). Accept when P(out-of-spec) < 0.13% (~3σ) or Cpk ≥ 1.33. Record mean/σ and sample size explicitly.

Ramp:   0.1 / 0.3 / 1 V/s → μ_trip, σ_trip; μ_ret, σ_ret (≥10 cycles per unit)
Ripple: 50–200 kHz, 10–100 mVpp near V_TH → chatter/misfire, minimum ΔV_HYS & t_blank
Temp:   −40 / 25 / 85 / 125 °C; ≥10 min soak; plot μ/σ vs temperature; edges to UVLO/POR
Blank:  Inject pre-bias/power-on spikes; verify no false trigger; measure minimum t_blank
Accept: P<0.13% (~3σ) or Cpk≥1.33; report n and confidence bands

Test	Setting	Samples (n)	μ_trip	σ_trip	μ_ret	σ_ret	Pass line	Result	Notes
Ramp	0.1 / 0.3 / 1 V/s	…	…	…	…	…	3σ / Cpk≥1.33	✓ / ×	…
Ripple	50–200 kHz, 10–100 mVpp	…	…	…	…	…	3σ / Cpk≥1.33	✓ / ×	…
Temperature	−40 / 25 / 85 / 125 °C	…	…	…	…	…	3σ / Cpk≥1.33	✓ / ×	…
Blanking/Delay	Pre-bias / Power-on spikes	…	…	…	…	…	3σ / Cpk≥1.33	✓ / ×	…

Report metrology: instrument models, probe types/bandwidth, injection source details, chamber soak times, fixture schematic.
Ensure repeatability: per-unit cycling (≥10), reset-tree dependencies logged, and environmental conditions recorded.

BOM & Procurement Notes (Small-Batch Ready)

Required: V_rail | n_rails | Threshold tolerance (%) | Latch/One-shot | Output (OD/PP) | AEC-Q100 (Y/N, Grade) | Package height (mm) | Second-source (Y/N)
Optional: I²C/PMBus | PG/FAULT semantics | Tamper/Zeroize hook | dV/dt requirement (S·t_blank with ΔV_HYS)
Risks: TCR mismatch → temp boundary crossing | MOQ/samples lead time | EOL | Window semantics mismatch | Ignored leakage paths

Submit your BOM (48h)

Cross-Brand Shortlist (Real PNs · Reasons)

Only publish verified, real PNs and datasheets. Columns below are placeholders for live specs: Tol@25°C / Tol@FullTemp / ΔV_HYS typ / ref. drift note / pkg height / AEC-Q100. Use the “Notes” column for pin/behavior compatibility and migration caveats.

Brand	Family / PN	Type	Tol@25°C	Tol@FullTemp	ΔV_HYS typ	Output	AEC-Q100	Pkg height (mm)	Notes (Pin/Behavior)	Datasheet
TI	TPS38-Q1	Dual-rail OV/UV supervisor	—	—	—	OD/PP options	Yes (family)	—	High VIN tolerance; dual windows; good for battery-side rails	Datasheet (PDF)
TI	TPS3890-Q1	Precise single-rail reset (delayable)	—	—	—	OD	Yes	—	High-accuracy threshold + programmable delay, great for logic core rails	Product page (DS inside)
ST	STM706	Supervisor + WDT + PFAIL options	—	—	—	OD/PP variants	Industrial/Automotive variants	—	All-in-one reset + WDT for MCU boards; legacy pinouts widely available	Product page (DS inside)
ST	STM1815	Simple reset detector (variants)	—	—	—	OD/PP variants	Check variant	—	Low-cost reset; easy drop-in for many boards	Product page (DS inside)
NXP	FS5600	Multi-rail monitor + window WDT (PMIC/SBC)	—	—	—	Integrated	ASIL-ready family (check grade)	—	Domain/gateway supply root monitor; FCCU/ERRMON hooks	Product page (DS inside)
NXP	FS6502 / FS6500	SBC with supervisor + watchdog	—	—	—	Integrated	G1 option	—	Good for high-integration ECUs; windowed WDT	Datasheet (PDF)
Renesas	ISL88011/012/013/014/015	Single/dual supervisor (delayable POR)	—	—	—	OD/PP variants	Industrial/Auto options	~SOT-23 class	Tight reset with MR/WDT options; easy drop-in	Family page (find DS)
onsemi	NCV301	Voltage detector / reset	—	—	—	OD	Yes (variants)	—	Simple brown-out reset; broad pin-compatibility families	Datasheet (PDF)
onsemi	NCP303 / NCV303	Precision reset detector family	—	—	—	OD/PP variants	Auto variants avail.	—	Cross-backup vs TI TPS38x/TPS384x families	Product page (DS inside)
Microchip	MCP1316/18/19, MCP1320/21/22	Automotive supervisors (delays/MR)	—	—	—	OD/PP variants	Yes (series)	~SOT-23 class	Robust supply + broad sourcing; second-source friendly	Family page (find DS)
Microchip	MIC2779 / MIC2790	Dual/multi-rail supervisors	—	—	—	OD / PP	Low / Medium	—	Dual/multi-rail sync supervision for SoC + I/O split domains.	Product page (DS inside)
Melexis	MLX81114	LIN node w/ supply monitor (module)	—	—	—	Integrated reset/WDT	ASIL-A capable (check)	—	Great for lamp modules; acts as local supervisor	LIN/SBC list (find MLX81114)
Melexis	MLX81116	High-speed LED driver w/ reset/WDT	—	—	—	Integrated WDT	Module-class	—	LED submodule supervisor role; check behavior semantics	Product page (DS inside)

Compatibility legend for “Notes”: Pin (pin-compatible) | Behav. (reset polarity/hold/PG semantics) | Func. (functional equivalence).
Publish only verified datasheet values; when uncertain, leave cell blank and add a TODO.

FAQs (Threshold & Tolerance)

How do IC accuracy, divider tolerance and temp drift combine into a single threshold budget?

Treat contributors as independent and combine statistically: σ_total ≈ √(σ_ic² + σ_divider² + σ_temp² + σ_leak²). Convert to a spec using Tol_total(%) ≈ (3·σ_total / V_TH)×100%. For windowed parts, compute upper and lower budgets separately. Align assumptions with your divider TCR, ΔT and leakage model so procurement and validation share the same baseline.

What hysteresis is “just enough” for slow ramps and 20–50 mV ripple?

Start with ΔV_HYS ≥ max(1.5×V_pp, S·t_blank). With 20–50 mV of ripple, practical hysteresis is often 30–80 mV depending on slew and delay. Verify by ripple injection at 50–200 kHz near V_TH and confirm no chatter. Avoid excessive hysteresis that masks real faults or compresses a window supervisor’s usable range.

When should I pick ±1% vs ±1.5% accuracy in automotive rails?

Choose ±1% when the system budget is ≤±2% or when windows are tight and recovery behavior is critical. If noise, temperature spread or divider drift dominate and hysteresis can be larger, ±1.5% is often sufficient. Consider availability and second source. Document the budget so the alternative device can meet the same combined tolerance target.

How do I size the divider to limit leakage error on a 1 MΩ-class input?

High impedance amplifies leakage and measurement loading. Use R_total in the 200–500 kΩ range for automotive supervisors, with same-series thin-film resistors and TCR ≤100 ppm/°C. Estimate offset as ΔV ≈ I_leak × R_eq at the sense node. Validate by A/B measurement with the ADC or ESD network connected and disconnected.

Does OTP-fixed threshold beat I²C-programmable for stability and spread?

OTP-fused thresholds provide excellent lot-to-lot consistency and no boot-time dependency. I²C programmability adds flexibility for late tuning but needs safe defaults, CRC and configuration timing controls. For volume builds or second source, OTP often simplifies spread control. Whatever you choose, re-verify trip and return after programming or fuse options.

How do I verify window supervisor limits across −40~+125 °C?

Use chamber points at −40, 25, 85 and 125 °C with ≥10 minutes soak per point. Record trip and return distributions for each window, over at least ten cycles per unit. Accept when μ_gap − 3·σ_gap ≥ ΔV_HYS + margin or Cpk ≥ 1.33. Confirm no overlap or dead zone exists across the full temperature range.

What blanking/delay avoids chatter on pre-biased rails?

Set hysteresis first, then choose t_blank so S·t_blank ≤ ΔV_HYS/2 for the worst-case slew. As a starting point, 50–200 μs covers many MCU and PMIC rails. Validate by injecting power-on spikes and pre-bias conditions. Ensure the delay does not mask genuine brown-out events or violate your reset tree dependencies.

How do I translate spec ppm/°C into mV shift on a 5 V rail?

Use ΔV(mV) = V × (ppm/1e6) × ΔT(°C) × 1000. Example: 5 V with 100 ppm/°C over 100 °C yields 50 mV expected drift. Apply this to both the IC reference and divider TCR. Sum statistically when sources are independent and check that the total remains inside your threshold budget.

Can I reuse the same divider for ADC sense and supervisor without skew?

Yes, but include ADC input leakage, sampling kickback and any ESD or protection branch currents. Either buffer the ADC, lower R_total or split the node with defined resistors. Quantify the added error as ΔV ≈ I_leak × R_eq and verify by A/B measurements. Keep the measurement bandwidth from disturbing the supervisor comparator.

What’s a safe acceptance criterion for small-batch validation (n=10~30)?

Use P(out-of-spec) < 0.13% (approximately 3σ) or Cpk ≥ 1.33 as your pass line. Report n, mean and standard deviation with confidence bands. Cycle each unit at least ten times per condition. Maintain identical metrology across ramp, ripple and temperature tests so your statistics remain comparable.

How much hysteresis is too much—what are the downsides?

Excessive hysteresis can compress a window supervisor’s effective range, prolong recovery after faults and hide marginal brown-outs. It may also delay legitimate resets during slow ramps. Prefer the smallest hysteresis that meets ripple and slew requirements, and consider temperature-aware or programmable options when boundaries shift across environments or loads.

How do I document tolerance stacks for procurement and second-source?

Attach a one-page tolerance stack showing IC accuracy, divider TCR, ΔT, leakage, ΔV_HYS and t_blank, with the statistical combination and limit lines. Include pin, behavior and functional compatibility notes. Use the same template in the BOM and validation report so suppliers and alternatives can match the exact system-level budget.

Threshold & Tolerance: Accuracy Class, Drift, and Hysteresis