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Why Layout & Grounding Matter for Thresholds/Reset
The stability of thresholds, hysteresis, and reset pulse width is the product of device specs and PCB implementation: ripple couples into the divider; switching loop flux couples into SENSE; ground bounce shifts the reset reference; long routes add parasitic C/L that create spikes. This section isolates root causes from controllable layout variables.
Noise Paths
- Supply ripple → divider node
- Switch loop flux → couples into SENSE
- Ground bounce → shifts reset reference
- Long routes → parasitic C/L spikes
Threshold Budget (5 factors)
IC accuracy (±%) + divider tolerance (±%) + temperature drift (ppm/°C → mV) + leakage bias (nA × Req) + front-end RC phase error.
Reset Stability (4 levers)
- Pulse ≥ datasheet min × 1.2
- Pull-up near the source
- 33–100 Ω series damping
- Correct level domains & semantics
| Symptom | Likely Root Cause | First Layout Fix |
|---|---|---|
| PG chatter at ramp | Ripple on divider; SENSE under split-plane gap | Add front-end RC; ensure continuous ground under SENSE |
| False reset near switching node | Crosstalk & ground bounce | Re-route away from SW; stitch-via fence; series 33–100 Ω |
| Threshold drift vs temperature | Divider mismatch & leakage | Thermally co-locate R’s; increase I_divider; clean surface |
Acceptance: Threshold drift ≤ 0.5× hysteresis; 0 false resets over 48 h (program/heat/cold cycles); PG chatter < 1 per 100 power-ups.
Threshold Sense: Dividers, Kelvin, RC & Leakage
Combine divider placement, Kelvin sensing, front-end RC, and a leakage budget to make thresholds reproducible under temperature and electrical noise. Keep routes short, same-layer, over continuous ground, away from SW/CLK nodes.
- Divider layout: close to SENSE, same layer, short & straight; lower resistor returns to the reference ground island at a single point.
- Kelvin return: from a “clean point” on the measured rail; independent trace back to divider top; continuous ground underneath.
- Front-end RC: start with Rser=100–1kΩ, C=1–10 nF → τ=0.5–5 ms. Condition: Rser ≪ (Rdiv∥Rin) to avoid breaking internal hysteresis.
- Leakage budget: Iin(leak) + board surface leakage. Rule of thumb: Idivider ≥ 100× Ileak,total; ΔVleak ≈ Ileak × Req.
- Thermal pairing: divider resistors side-by-side in one thermal zone; avoid cross-zone gradients.
- Shared divider (ADC + supervisor): buffer or small series resistors + single-point summing to limit sampling injection skew.
- Slope scan: 0.1 → 5 V/ms; trigger level drift ≤ ±1.5% (typical).
- Thermal cycle: ΔT ≈ 80 °C; total shift ≤ 50% of hysteresis.
- Ripple injection: 20–50 mV at kHz; post-RC, no chatter; upper/lower thresholds stable.
Divider & Hysteresis Cost Tiers
±1.0% vs ±1.5% threshold accuracy; 0.1%/25 ppm vs 1%/200 ppm divider pairs. Pick per rail criticality and inventory risk.
Cleanliness & Leakage Control
Flux residues and moisture raise Ileak. Specify board cleaning and conformal coating on small-current sensing networks.
Quick rules: place divider at SENSE; Kelvin from load clean point; Rser ≪ (Rdiv∥Rin); Idivider ≥ 100× Ileak; guard ring & continuous ground under trace.
Star/Split Grounds & Return Control
Control the reference ground so thresholds and resets stay stable. Use a Quiet Island for supervisors/RTC/reference, connect to power ground at a single low-impedance star point, and guide return currents with stitching vias. Only split ground when necessary and always bridge across critical gaps to avoid uncertain return paths and ground bounce.
Star Connection & Quiet Island
- Supervisor/RTC/reference on a “Quiet Island”.
- Single-point, short-wide star to power GND.
- High-ripple returns must not cross the island.
Split Strategy & Bridge
- Split only when necessary (“if it can stay solid, keep it solid”).
- Bridge gaps under crossing signals with via fences (2–3 mm pitch).
- No voids or slots under SENSE/RESET routes.
Return Continuity & Guard
- Keep “ground-under-trace” continuity; use full GND planes.
- Stitch vias every 10–15 mm near key routes.
- SENSE keepout 10–15 mil; guard ring to ground as needed.
Acceptance / Validation
- TDR/phase probe: minimal impedance step across the split.
- ESD event: reference ground shift < 50 mV per event near the island.
- Thermal swing: threshold shift ≤ 50% of hysteresis.
Procurement Notes
- Via count/drill size vs prototyping cost.
- Laminate, solder mask, cleaning process adders for reliability.
- Height limits near the star point (assembly risk control).
Reset/PG Lines: Topology & Crosstalk Immunity
Make RESET/PG immune to chatter in complex power trees: select a robust topology, control edges with series damping, keep pull-ups near the source, respect level domains, and place delay/blanking where the true power state is known first.
Topology
- Point-to-point first choice.
- Multiple loads → use a fanout buffer.
- Avoid long “branched daisy-chain”.
Edge & Ringing Control
- Series 33–100 Ω near the source.
- Pull-up placed close to the driver.
- Limit trace length & via count; add small C if needed.
Level Domains & Bias
- Open-drain can cross domains, but each domain owns its pull-up.
- Push-pull requires level matching or isolation.
- Route away from SW/high-speed nets; keep common ground reference.
Pre-bias & Slow Ramp
Place delay/blanking where the system first learns the true power state (e.g., supervisor side). Define PG semantics/polarity before and after aggregation to avoid low-active/high-active confusion.
Acceptance / Validation
- RESET low pulse ≥ 1.2× datasheet minimum.
- 100 power cycles: no chatter or false resets.
- Injected switching noise does not trigger reset.
Procurement Notes
- Fanout buffer family (placeholder; brand-neutral).
- Pull-up & series resistors: E24 common packs.
- Mixed-voltage boards: level shifters/isolators options (placeholder).
EMC Entry Points & Fixes
Around supervisors and reset lines, adopt a “conduct energy first, then clamp voltage” micro-structure. Place low-cap TVS near the I/O, add a series R (10–100 Ω) plus tens-of-pF C RC-snub before the IC, and keep ground-under-trace continuity. For EFT/Surge, keep chassis paths short/straight/wide and avoid common-impedance coupling across partitions.
ESD (IEC 61000-4-2)
- Reserve low-cap TVS pads right at the connector (≤1 via).
- Before IC: Rseries 10–100 Ω + C 10–100 pF → RC-snub.
- Trace over solid ground; prioritize orthogonal crossing near HS nets.
EFT / Surge (-4-4 / -4-5)
- Chassis return short · straight · wide (>2 mm with multi-vias).
- PG/Reset across partitions: stitch to local ground at both ends.
- Use ground guards + via fences (2–3 mm pitch) to limit field spread.
RF/Clock Proximity
- ≥10 mm from XO/RF front-end; orthogonal over parallel.
- Optional 22–33 Ω series + local ground guard.
- Shield cans: multi-point to chassis to dump ground bounce.
Copy-Ready Rules
- TVS: Cdiff ≤ 0.5–1.5 pF (HS), low Rdyn, VWM ≥ rail max.
- RC-snub start: R=33 Ω, C=33 pF → tune toward ζ≈0.7.
- RESET/PG: length <100 mm, vias ≤ 2–3, local ground at each partition.
Acceptance (Bench Screening)
- ESD ±8/±15 kV (contact/air): no reset, PG steady.
- EFT 1 kV: no false toggle on PG/Reset.
- Surge combo: PG semantics preserved; no VIH false-high / VIL false-low crossings.
Procurement Hooks
- Low-cap TVS arrays (cap/height/price tiers).
- RC-snub packs: 22/33/47/68/100 Ω & 10/22/33/47/68/100 pF.
- Shield/chassis hardware BOM share for small-batch.
Bring-Up & Validation Checklist
Turn “looks stable” into evidence-backed stability with a repeatable bench flow. Measure static points, sweep dynamics, characterize reset behavior, run EMC smoke tests, and archive artifacts against acceptance criteria.
Static Measurements
- Divider ratio, SENSE node voltage, input leakage.
- Multi-temp points: −40/25/85/125 °C (threshold logs).
Dynamic Scans
- Ramp 0.1→5 V/ms; inject 20–50 mV ripple (kHz).
- Pre-bias / power-drop-and-reapply; log V/T windows.
Reset Characteristics
- RESET low width ≥ 1.2× datasheet minimum.
- Pull-up domain, fanout skew, ringing/overshoot vs load/length.
EMC Smoke Tests
- ESD/EFT/Surge quick screening; localize issue; re-verify.
- Document peak values, RC/TVS positions, return lengths.
Acceptance Criteria (Example)
- Threshold drift ≤ 50% of hysteresis.
- RESET low ≥ 1.2× minimum spec.
- 100 hot/cold cycles: no chatter/false resets.
- EMC pre-check pass; PG semantics consistent.
Procurement Hooks
- Environmental chamber, programmable PSU, ripple injector.
- Probe/fixture kit: ×10 passive, differential, wide-band current.
- Sample packs: divider tolerance/ppm bins, TVS Cdiff variants.
BOM & Procurement Notes
For small-batch builds, provide the mandatory fields below to get a first-pass shortlist and a cross-brand “two choices” proposal. Keep layouts aligned with the earlier grounding/reset rules to avoid late changes during validation or EMC screening.
Mandatory Fields
- V_rail (e.g., 3.3/5/12 V), n_rails
- Threshold / hysteresis targets
- delay/blanking needed at source or aggregate
- Output type: OD / PP
- AEC-Q100 grade / temp class
- Package height limit
- Second-source (Y/N)
Optional Fields
- I²C/PMBus address range
- PG/FAULT semantic alignment (polarity, wired-OR)
- dV/dt constraints (ramp domains)
- Divider ppm/°C target (e.g., 25–100 ppm/°C)
- RC-snub initial values (e.g., 33 Ω + 33 pF)
Risks & Mitigations
- Pin/semantic mismatch → fanout buffer / level shifting
- EOL/lead time → dual-brand “primary+backup” mapping
- MOQ → prefer E24/E96 passives & swappable packages
- Contamination/moisture → cleaning + conformal coat; re-budget leakage
| Item | Spec / Value | % of Budget | Note |
|---|---|---|---|
| IC accuracy | ±1.0% (target) | 40% | Use precision series when hysteresis is small |
| Divider tolerance | 0.1% / 25 ppm/°C | 20% | Pair resistors thermally |
| Temp drift | ΔV = Vrail×ppm×ΔT/106 | 20% | Use 80 °C span estimate |
| Leakage equivalent | ΔV = Ileak×Req | 15% | Compare “pre/post clean” |
| RC phase error | τ = Rser×C vs ramp slope | 5% | Don’t eat hysteresis margin |
Reset Damping Cheatsheet
- Trace ≤ 50 mm: pull-up 10–47 kΩ; Rseries 33–47 Ω
- 50–100 mm or multi-fanout: pull-up 4.7–10 kΩ; Rseries 47–100 Ω; vias ≤ 3
- Optional de-ring: C = 10–22 pF at receiver
Supervisors / Window Detectors
- TI: TPS3702-Q1, TPS3890-Q1 — precise UV/OV, automotive families
- onsemi: NCV809x, NCV308 — wide availability, Q-grade options
- Renesas: ISL88014/016 — stable drift, clear timing options
- Microchip: MIC803/809, MCP1316/1318 — many polarities/delays
- ST: STM706/708 families — compact reset monitors
- NXP: Use SBC platform monitor, or add window (TI/onsemi) externally
- Melexis: Pair external window (TI/onsemi) with MLX domain devices
Reset Fanout / Level Domains
- TI: SN74LVC1G17/2G17 (Schmitt buffer); TXS010x (level)
- onsemi: NCV7SZ14 (Schmitt-inv, Q-grade), NC7SZ17 (buffer)
- Renesas: 74LVC1T45 (bi-dir level shifting)
- NXP: PCA9517A (I²C buffer), NVT2001 (level translator)
- ST: 74LVC family; ST2378E where protection is needed
- Microchip: MCP14xx drivers/buffers (per polarity)
- Melexis: mix-and-match with external window supervisors
Low-Cap TVS Arrays & Passives
- TI: TDP0x series (HS lines)
- onsemi: ESD9x/ESD7x, NUP2105L (diff-pair)
- NXP: PRTR5V0U2F, PESD5V families
- ST: ESDALC/USBLC (low capacitance)
- Resistors: 0.1%/25 ppm (strict) or 0.5–1%/50–100 ppm (cost)
- Capacitors: C0G/NP0 for pF–nF; X7R for nF–µF; start 33 Ω + 33 pF
Frequently Asked Questions
How do I route Kelvin sense to stop threshold drift on a noisy 5 V rail?
Take a dedicated trace from the rail’s quiet point back to the divider top, over continuous ground. Keep it away from SW nodes and clocks, cross orthogonally, and add 33–68 Ω + 10–33 pF at SENSE. Pair divider resistors thermally and budget leakage so total shift stays within 50% of hysteresis.
What RC values debounce 20–50 mV ripple without breaking hysteresis?
Start with Rseries=33–68 Ω and C=10–33 pF for a 0.3–2 ms pole, then tune toward ζ≈0.7. Confirm that τ is small relative to the rail’s ramp so it won’t “eat” the internal hysteresis. Validate with injected ripple and verify no chatter across hot/cold corners.
Where should I place the divider relative to the supervisor and the load?
Place the divider close to the supervisor SENSE pin, same layer, short traces, and return the lower leg to the reference-ground island. Kelvin the top node from a clean rail point. Avoid plane voids under SENSE, and separate from switching nets; pair resistors for matched temperature exposure.
When is a ground cut safe and when do I prefer stitching vias instead?
Cut only to contain known high-ripple paths and never under SENSE/RESET. If a signal must cross a slot, bridge it with a via fence (2–3 mm pitch) and keep the return short, straight, and wide. When unsure, keep planes solid and rely on stitching to shrink loop area and impedance steps.
How do I keep RESET lines immune to crosstalk near a switching node?
Route away from SW and clocks, prefer orthogonal crossings, and maintain ground-under-trace continuity. Add 33–100 Ω series at the driver, keep pull-ups near the source, and limit length and vias. For long multi-drops, use a fanout buffer and small de-ring capacitance at receivers if needed.
Should I use open-drain or push-pull resets on mixed-voltage boards?
Open-drain resets cross domains safely when each domain owns its pull-up to the local rail. Push-pull offers tighter edges but demands level matching or isolation. If aggregation is required, buffer fanout per domain and document the polarity and semantics before combining PG or reset signals.
What’s a practical leakage budget for 1 MΩ-class dividers?
Size divider current at 50–200× total expected leakage, including IC input bias, TVS or ESD leakage, and surface conduction after flux. Convert to ΔV = Ileak×Req and keep the sum within ~40% of hysteresis. Verify with pre/post cleaning measurements across temperature.
How do I validate thresholds across −40~+125 °C on the bench?
Log trigger points over −40/25/85/125 °C using controlled ramps and ripple injection. Record up/down thresholds, hysteresis, and any drift against the budget table. Confirm the reset pulse exceeds 1.2× minimum at each corner and that chatter remains zero under pre-bias and power-reapply tests.
What delay/blanking locations avoid chatter on pre-biased rails?
Place delay or blanking where the system first knows true power state—typically at the supervisor output or the earliest PG. Avoid late, aggregated points that see mixed domains. Re-test with slow ramps and injected ripple to ensure the window never straddles hysteresis during bias decay.
Can I share the divider between ADC and supervisor without skew?
Yes, if you isolate the sampling kickback. Add a small series resistor to the ADC input or buffer it; star-join at one node and keep the lower leg on the reference-ground island. Validate by stepping the ADC sampling rate and checking threshold shift stays below half the hysteresis.
How do I place TVS and RC-snubbers without adding false trips?
Put low-cap TVS close to the connector (≤1 via), then an RC-snub just before the IC with C to the reference-ground island. Maintain ground-under-trace continuity and avoid plane voids. Tune R/C so the pole damps spikes but doesn’t delay ramps enough to erode the internal hysteresis.
What acceptance criteria prove “layout-safe” before EMC testing?
Threshold drift ≤ 50% of hysteresis; reset low ≥ 1.2× spec; zero chatter across 100 hot/cold power cycles; injected switching noise does not flip PG. Pre-screen ESD/EFT/Surge with photos and waveforms archived, then lock the BOM and routing for the certification test pass.
