Buried-Zener Voltage Reference
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What Is a Buried-Zener?
Definition & Process
A Buried-Zener reference uses avalanche/zener mixed breakdown inside a buried junction to suppress surface states, moisture coupling, and package-stress effects. The buried structure improves low-frequency noise and temperature stability compared with surface Zeners.
Value for Metrology
- Lower 0.1–10 Hz noise; smoother TC curve.
- Slower long-term drift after stress relaxation.
- Best suited for calibration sources and precision rails.
Positioning (vs Bandgap/XFET)
Bandgap/XFET wins on power/cost and flexible PSRR at low Iq; Buried-Zener wins when the priority is ultra-low noise, tight TC, and long-term stability in metrology-grade designs.
Device Physics & Temperature Behavior
TC Model & Inflection
Use first/second-order TC with an inflection temperature. Drift budget: ΔV = Vref × (TCppm/°C × ΔT)/1e6. Integrate over −40~+85/125 °C for total drift; validate with 3-point or 5-point chamber tests.
Noise & Measurement Window
Combine broadband and 1/f noise. Keep measurement bandwidth consistent (0.1–10 Hz window). A practical upper bound: µVpp ≈ 6.6 × µVrms.
Stress Relaxation & Aging
Expect early drift within the first 100–200 h from package-stress relaxation. Temperature cycling may rebound slightly, then a plateau follows. Pre-aging can shorten the stabilization time at a power/cycle cost.
Methods & Repeatability
- 3-point/5-point TC fit; check residuals and R².
- Low-frequency noise: fixed window, averaging count, bandwidth traceability.
- Lot-to-lot statistics: median and variance, with traceable IDs.
Series vs Shunt & Ovenized Options
Series (Reference Rail)
- Acts as a clean reference rail feeding precision loads.
- PSRR stacking: low-noise LDO + RC prefilter improves immunity.
- Buffer position: BZR → RC → low-noise buffer → star fan-out.
- Loop/transient: phase margin vs Cout ESR/ESL; Kelvin return.
Shunt (Clamp/Threshold)
- Parallel clamp relying on IKA window to hold bias.
- More sensitive to source impedance and self-heating.
- Useful for simple thresholds; metrology prefers series+buffer.
Ovenized / Quasi-Ovenized
- Stabilizes junction near Toven to minimize TC.
- Trade-offs: power, volume, warm-up time (≈10–30 min).
- Thermal loop must be stable; shield from airflow/vibration.
Design Conclusion
Default to Series + Buffer for precision rails. If TC budget still fails and power allows, adopt a small ovenized shell. For automotive, verify vibration/thermal path integrity and maintain PSRR with layout discipline.
Low-Noise Biasing & Filtering
Bias Source
- Low-noise LDO + RC π; avoid knee region bias.
- Metal-film/low-TCR resistors; balance thermal noise vs impedance.
- Start with Ibias ≈ 1.2× datasheet noise-optimal midpoint.
Filtering & Loops
- 0.1–10 Hz window via multi-stage RC; add Sallen–Key if needed.
- Soft-start/pre-charge to limit dV/dt and overshoot.
- Verify AC sweep first, then transient step response.
Buffer & Isolation
- Low-offset/low-1/f op-amp; GBW sized to load bandwidth.
- Kelvin sense to reference node; star ground; return current control.
- Near-load decoupling (1–10 µF + 100 nF).
Starter Defaults
- RC-1: 10–100 Ω + 10–47 µF; RC-2: 100–470 Ω + 1–10 µF.
- Sallen–Key: Fc=1–5 Hz; GBW ≥ 10×Fc.
- Buffer PM ≥ 60°; Cout=1–10 µF, ESR 20–100 mΩ.
Warm-Up, Aging & Long-Term Drift
Warm-Up (ΔV to Thermal Plateau)
- From power-on to thermal steady state; fast first minutes, then slow settle.
- Metrology guidance: 10–30 min typical (package/ovenization dependent).
- Define plateau via |dV/dt| < X µV/min for ≥ Y min.
Aging (Stress Relaxation)
- 100 h: rapid relaxation; potential rebound.
- 500/1000 h: slope slows toward a plateau.
- Optional pre-aging to shorten in-field drift.
Long-Term Drift (ppm/yr)
- Report as ppm/yr or µV/yr with ambient & bandwidth notes.
- Track lot, device ID, timestamp, 0.1–10 Hz or DC, averages.
- Use median + 90th percentile envelope as yearly budget.
Re-Calibration Rules
- Trigger when cumulative drift > 70–80% of budget or environment out of spec.
- Lab: 12-month cycle; ATE: 6–12 months; Automotive node: ~12 months + spot checks.
- Keep signed logs for traceability.
PCB Layout & EMI Immunity
Return Loops & Grounding
- Minimize loop area; separate sensitive reference loop from power loop.
- Star ground and Kelvin sense to the reference node.
- Add guard ring around the reference net tied to clean ground.
Thermal Management
- Avoid direct airflow/heat from power devices toward the reference.
- Account for metal connector heat paths; promote isothermal regions.
- Thermal shielding without destabilizing loops.
EMI/EMC Paths
- Input ripple isolation: low-noise LDO + RC π, shield can single-point ground.
- Keep distance from magnetic components; manage cable common-mode.
- Use ground stitch/slot bridges across domain boundaries.
Thermoelectric EMF
- Hetero-metal junctions (Cu/Sn/Ni/terminals) create µV-level EMF under ΔT.
- Reduce junction count; keep both ends isothermal; log ambient during calibration.
- Set ΔT threshold (≤1–2 °C) for acceptance in scripts.
Metrology-Grade Design Checklist
Convert key metrics into Metric → Method → Pass line items for small-batch validation and mass-production sampling: TC, 0.1–10 Hz noise, aging/long-term drift, PSRR & loop, and traceability.
-
TC (ppm/°C)
3/5-point chamber; fit 1st/2nd order; R²≥0.995; log bandwidth & averaging. -
0.1–10 Hz noise
Integrate LF band; average N runs; 95% CI; record bias & rd. -
Aging / LT drift
Check at 100/500/1000 h; median & P90 envelope; re-cal triggers. -
PSRR & loop
Ripple injection & transient; PM≥60°; ΔVref_max vs ripple. -
Traceability
Brand/PN • Lot • Date code • Work order • signed logs • AQL plan.
7-Brand Shortlist & Mapping (Datasheets nofollow)
All parts verified on official pages. Prioritize Buried-Zener / ovenized; otherwise best low-drift series/shunt options. External links use rel="nofollow".
| Brand | Family / PN | Type | VREF | TC (ppm/°C) | Noise (key spec) | Iq / IKA | AEC-Q100 | Package (H) | Notes | Datasheet |
|---|---|---|---|---|---|---|---|---|---|---|
| Texas Instruments | REF80 (heater-compensated) | Ovenized Buried-Zener | ~7.6 V | Ultra-low (see DS) | Low LF noise (BZR) | — | — | Hermetic | Internal heater; calibration instruments. | TI REF80 DS |
| Texas Instruments | REF102 | Series (Precision) | 10 V | ≤ 2.5 typ grade | Noise-reduction pin | — | — | SOIC-8 | Classic 10 V reference rail for ADC/DAC. | TI REF102 DS |
| STMicroelectronics | LM4040 (fixed) | Shunt (Bandgap) | 2.048–5.000 V options | ≤ 70 max (grade) | LF noise ~10 µVpp (AN) | IKA ≥ 10 µA typ | Varies | SOT23 / SOT323 | Micropower shunt; easy TL43x alt. | ST LM4040 DS |
| NXP (Nexperia) | TL431 family | Shunt (Adjustable) | 2.5 V (settable to 36 V) | — | Dyn. R & LF noise depend on bias | IKA 40 µA–100 mA | Auto variants | SOT23 / TO-92 | Threshold/loops baseline; verify LF noise. | Nexperia TL431 DS |
| Renesas (Intersil) | ISL21090Bxx (e.g., 7.5 V) | Series (Ultra-low-noise) | 1.25 / 2.5 / 5.0 / 7.5 V | ~7 typ (grade) | Sub-µVpp @0.1–10 Hz (1.25 V) | — | — | SOIC-8 | Bipolar-based; metrology-class LF noise. | Renesas ISL21090B DS |
| onsemi | NCP431 / NCP432 | Shunt (Adjustable) | 2.5 V (settable to 36 V) | — | Typical dyn. R 0.22 Ω (DS) | IKA 40 µA–100 mA | Some AEC-Q101 Z-series | SOT23 / SC59 | TL431-class alternative. | onsemi NCP431 DS |
| Microchip | MCP1501 (buffered) | Series (Precision) | 1.024 / 2.048 / 4.096 / 5.000 V | ≤ 50 max (−40~125 °C) | Buffered; 20 mA source/sink | Iq up to 20 mA drive | Auto recs (see DS) | SOIC-8 / SOT23 | Solid low-drift bandgap baseline. | Microchip MCP1501 DS |
| Melexis | Use external metrology VREF (system) | External reference pin | — | — | Device-level drift spec | — | Many AEC-Q100 sensors | — | Select BZR/ovenized series into VREF pin. | Melexis VREF pin AN |
Notes: For ADC/DAC rails, start with Series+Buffer; for ovenized needs, consider TI REF80. TL431-class shunts (Nexperia/onsemi) are practical thresholds/error-amp baselines—verify LF noise under actual bias.
BOM & Procurement Notes
For small-batch builds, lock the minimum info set before ordering: reference target, drift/TC class, noise window, topology, bias, package height, and second-source plan. Separate pilot vs mass sampling strategy and keep lots consistent.
Required fields
- VREF nominal & tolerance
- TC class (ppm/°C, window)
- 0.1–10 Hz noise window
- Type: Series / Shunt / Ovenized
- Iq / IKA
- AEC-Q100 (Y/N/Grade)
- Package height (H)
- Second-source (Y/N)
Optional constraints
- Warm-up timing and soak policy
- Re-calibration interval (months)
- EMI/EMC constraints near VREF node
- Ovenized option and power budget
- Temperature window (e.g., −40~+85 °C)
Risks & countermeasures
- EOL/PCN: verify notices pre-PO; keep package/pin-compatible alternates.
- Counterfeit: use OEM/authorized only; unify lots; incoming TC/noise spot-checks.
- Pin/semantics: buffer polarity, PG/FAULT logic & level; power-up ordering; stability in splits.
- Samples/MOQ: different SLA for pilot vs mass; check lead time & minimums; jig height recal.
Copy this block into your RFQ (adjust values):
vref_nominal=7.000V
vref_tol_ppm=±50ppm
tc_ppm_c=≤5ppm/°C (−40~+85°C)
noise_uvpp_0p1_10hz=≤2.0µVpp
type_ref=series # series|shunt|ovenized
iq_ma=1.8mA
pkg_code=SOIC-8; pkg_height_mm=1.75
aecq100_grade=N/A
second_source=Yes (brand/model to be aligned)
warmup_min=20
recal_interval_month=12
emi_constraints="shield near VREF; star ground; Kelvin sense"
temp_window_c="-40~+85"
FAQs
Answers assume metrology-grade practice: declared bandwidth, averaging N≥10, and warm-up per #drift-aging. Text below exactly matches the JSON-LD block.
How do I size bias current to minimize noise while keeping the reference out of its knee?
Sweep bias from the knee region to the flat region and monitor 0.1–10 Hz noise and dynamic resistance. Choose the lowest current that keeps the device outside the knee across temperature, then add margin for load and buffer input bias. Re-verify after filtering to avoid false minima from bandwidth limits.
What TC spec is “good enough” for a 16-bit ADC at −40 to +85 °C?
Translate TC to full-range shift: ΔV/V ≈ TC·ΔT. For 5 ppm/°C over 125 °C, drift is ~625 ppm. Compare against the ADC’s LSB fraction of full-scale and system recalibration plan. With periodic trim, 3–5 ppm/°C works; without recal, target ≤3 ppm/°C and derate for oven or shielding.
How do I translate ppm/°C into expected mV shift over my operating range?
Use ΔV ≈ VREF · TC · ΔT. Example: 7.000 V, 3 ppm/°C, −40~+85 °C (ΔT=125 °C) gives ≈ 7.000 × 3e−6 × 125 ≈ 2.625 mV. If the device has an inflection point, integrate piecewise around the knee; validate with 3- or 5-point chamber data to refine the estimate.
When should I choose an ovenized Buried-Zener instead of simple temperature compensation?
Pick ovenized when the TC budget is ≤1–2 ppm/°C over wide ambient, warm-up and power are acceptable, and long-term drift drives calibration cost. Temperature compensation helps, but heater-stabilized references deliver flatter TC and reduced stress sensitivity for calibration sources and transfer standards.
How do I filter 1/f noise without creating startup overshoot or ringing?
Prefer passive RC at the reference pin with a well-damped buffer. If using active filters, add soft-start or precharge and check the buffer’s phase margin with worst-case ESR/ESL. Validate cold/hot starts and load attachment transients; keep the corner below the measurement band to avoid shaping artifacts.
What layout tricks cut thermocouple-grade thermal EMF around the reference node?
Use matched metals and symmetric copper to cancel gradients, route Kelvin sense to the load, and keep the reference away from connectors or hot parts. Add a guard ring tied to the quiet ground, minimize loop area, and align airflow so both sense leads see the same temperature profile.
How long should warm-up last before taking metrology-grade measurements?
Log VREF vs time at constant ambient and declare stability when slope falls below your ppm/min threshold. Buried-Zener rails typically need tens of minutes; ovenized parts may stabilize faster once the heater closes the loop. Re-check after load connection and after enclosure lid-on to capture thermal settling.
How do I budget long-term drift and set a realistic re-calibration interval?
Combine vendor ppm/yr guidance with early-life aging data (100/500/1000 h). Set an annual budget and trigger recal when the cumulative trend exceeds 70–80% of that guard band. Keep lots unmixed, record temperature and bandwidth, and use median plus P90 envelopes to avoid chasing outliers.
Can I parallel references for lower noise, and what are the stability hazards?
Paralleling can reduce broadband noise as √N, but mismatch and loop interaction may create current hogging and oscillation. Use small isolation resistors, a single buffer, and verify startup and load steps. Low-frequency noise may not average as ideally; measure the 0.1–10 Hz window to confirm benefit.
What’s the safest way to buffer a Buried-Zener into multiple rails or loads?
Use a low-noise, low-offset buffer with adequate GBW and output drive, then split rails after the buffer with per-branch RC damping. Keep the reference pin quiet with a local RC and star ground. Validate phase margin with worst-case capacitive loading and verify transient recovery on each branch.
How do I evaluate lot-to-lot variation and avoid mixing “noisy” lots in small-batch builds?
Sample each lot for TC and 0.1–10 Hz noise using identical fixtures and bandwidth. Track median and P90 and flag lots whose LF noise exceeds your envelope. Build pilot and mass runs from the same lot where possible, and archive raw logs with lot/date codes for traceability.
What procurement red flags indicate counterfeits or re-marked parts for precision references?
Inconsistent lot/date codes, unusual package height or mold marks, off-spec LF noise, and drift far from datasheet norms are warning signs. Purchase only from OEM or authorized distributors, require certificates, and perform incoming spot checks on TC and 0.1–10 Hz noise before parts enter production.
Resources
Texas Instruments
STMicroelectronics
- LM4040 — Precision shunt reference: Datasheet
NXP (Nexperia)
- TL431 family — Adjustable shunt regulators: Datasheet
Renesas (Intersil)
- ISL21090B — Ultra-low-noise precision reference: Datasheet
onsemi
- NCP431 — Programmable precision reference: Datasheet
Microchip
- MCP1501 — Buffered precision reference: Datasheet
Melexis
- MLX91220 — Reference pin usage (system VREF): Application Note
