V/F vs FOC — how to choose for an ACIM drive

Before the inverter hardware is frozen, the control strategy for the AC induction motor needs to be decided. The choice between a simple scalar V/f scheme and a full field-oriented control (FOC) implementation drives requirements on current sensing, feedback interfaces, MCU or DSC performance and the number of hooks the ACIM inverter must expose.

Scalar V/f control suits applications where torque follows a relatively smooth profile and dynamic performance is modest, such as many industrial fans, pumps, cooling towers and HVAC blowers. FOC becomes attractive when fast torque response, accurate speed regulation, high efficiency and four-quadrant operation are required, or when regulatory and energy-saving targets push the drive beyond basic V/f capabilities.

Typical situations where V/f control is often sufficient:

• Fans and pumps with monotonic flow curves and modest dynamic requirements
• Drives with infrequent starts and stops and gentle acceleration or deceleration ramps
• Applications where low-speed torque, zero-speed holding force and positioning are not critical
• Projects where cost, simplicity and ease of maintenance dominate over maximum efficiency

Typical situations that tend to favour FOC:

• Conveyors, hoists and positioning systems that demand fast torque and speed response
• Low-speed or near-zero-speed operation with significant torque demand
• Drives subject to explicit efficiency or energy KPIs, such as kWh per tonne or SEER targets
• Systems requiring four-quadrant operation or regenerative braking into the DC link or grid
• Applications where acoustic noise, vibration and smooth torque are design constraints

A practical way to translate these ideas into an inverter requirement is to walk through a short checklist. Each question answered with a clear “yes” pushes the design further toward richer feedback and FOC requirements; a sequence of “no” answers usually keeps scalar V/f acceptable.

• Does the application demand high torque at low or near-zero speed for extended periods?
• Is four-quadrant operation or regenerative braking part of the functional specification?
• Are there explicit efficiency or energy-saving KPIs that the drive must help achieve?
• Is tight speed regulation required over a wide mechanical speed range and load variation?
• Must the system remain completely sensorless, or is an encoder or resolver interface acceptable?
• Is acoustic noise or mechanical vibration from torque ripple a critical acceptance criterion?

A V/f-oriented ACIM inverter can often work with a simpler current-sensing scheme, such as a DC-link shunt and limited phase-current feedback. In contrast, an inverter intended to support FOC typically needs multiple phase-current sensing channels, higher bandwidth and linearity in the current measurement chain, and access to encoder or resolver interfaces when closed-loop position or speed feedback is used. Detailed control algorithms and code structure are handled in the FOC controller and motion MCU topics; this section focuses on what the ACIM inverter must expose to those controllers.

Inverter power stage topology for ACIM drives

Once the control strategy is outlined, the inverter topology and device class must match the AC induction motor line voltage, current range and thermal budget. Most industrial ACIM drives use a two-level three-phase bridge built from MOSFETs or IGBTs, with the DC-link capacitor bank providing the energy buffer between the rectifier or PFC front-end and the inverter. At higher voltages and powers, multi-level structures appear, but the fundamental role of the ACIM inverter remains the same.

For low to medium power levels, a conventional two-level bridge is typically sufficient. At 230 Vac line voltages the DC link sits around 325 VDC and 600–650 V MOSFETs or IGBTs are common. At 400–480 Vac the DC link moves toward 560–680 VDC and 1200 V IGBTs dominate. Multi-level topologies such as NPC or T-type are introduced at higher voltages and powers to reduce device voltage stress and dv/dt, but the detailed treatment of those structures belongs in high-voltage drive topics rather than this ACIM inverter overview.

Typical combinations of line voltage, DC link and device class:

Switching frequency is another key dimension. Lower frequencies in the 2–4 kHz range reduce switching losses but may bring audible noise into the mechanical system. Higher frequencies in the 8–12 kHz or even 16 kHz+ range can move dominant ripple components out of the most sensitive acoustic bands at the cost of increased losses and tighter demands on device selection and cooling. Detailed acoustic and vibration mitigation is handled in a dedicated topic; this section simply highlights how the chosen frequency range influences the inverter design envelope.

AC induction motors introduce risk factors that should be reflected in the power-stage design. Single-phasing can lead to excessive current and heating in the remaining phases. High dv/dt at the inverter output stresses winding insulation and long motor cables and may call for dv/dt filtering or output reactors. Harmonic content and high-order components increase iron and copper losses and can drive unexpected temperature rise. The inverter topology and device class should therefore be chosen with these ACIM-specific behaviours in mind.

PFC / rectifier front-end hooks into the inverter

The rectifier or power-factor-correction front-end and the ACIM inverter share a common DC link, but their responsibilities are different. The front-end shapes input current and regulates the DC-link voltage, while the inverter bridges that DC link to the motor phases and reports loading and regenerative conditions. This section focuses on interfaces and coordination, not on PFC control algorithms.

In smaller drives a simple diode bridge feeding the DC-link capacitor bank is often used. This arrangement keeps cost low but leaves AC-side harmonic content and power factor largely determined by the rectifier waveform. It is most suitable where power levels are modest and grid power-quality requirements are not stringent, and where regenerative operation is limited or handled only by a brake resistor on the DC link.

As power levels and regulatory demands increase, the rectifier is replaced by a single- phase or three-phase PFC stage. The PFC controller sets and maintains the DC-link voltage within a defined window, while the inverter is responsible for motor control and for signalling loading and regenerative conditions. Clear ownership is needed for who sets the DC-link voltage target, who manages precharge and soft-start, and how excess energy is dissipated or returned to the grid.

Key coordination points between PFC / rectifier front-end and inverter:

• DC-link voltage setpoint and window – the PFC controller typically maintains the DC link at a target level with upper and lower tolerance limits, while the inverter monitors for under-voltage and over-voltage conditions that affect motor operation and protection thresholds.
• Precharge and soft-start ownership – either the front-end module handles inrush and precharge autonomously and exposes a “ready” status, or the inverter controls precharge relays and resistors while the PFC waits for a stable DC link before closing its own loop.
• Regenerative energy handling – smaller systems may rely on a brake chopper and resistor to burn excess energy, while larger systems may use a bidirectional PFC stage to return energy to the grid. The inverter must still indicate when DC-link voltage rises due to regeneration.

Signal and I/O hooks commonly shared around the DC link:

• VDC_SENSE – an analog DC-link voltage measurement, usually shared by both PFC and inverter controllers for regulation, derating and protection.
• DC_LINK_OV_FAULT – a fast hardware over-voltage comparator output that can directly trigger drive shutdown or brake chopper activation.
• DC_LINK_UV_WARNING – an under-voltage warning or status used to ramp down torque or prevent aggressive acceleration when the DC link is not fully supported.
• PRECHARGE_ACTIVE / PRECHARGE_DONE – signals that indicate when inrush limiting or precharge is in progress and when the DC link has reached a safe operating level for enabling the inverter.
• PFC_ENABLE / INVERTER_ENABLE – handshake lines that coordinate which block is allowed to operate and under what conditions, so that the DC link is never driven into unsafe states.
• BRAKE_CHOPPER_ENABLE / BRAKE_ACTIVE and optional PFC_REGEN_OK – signals that coordinate how brake choppers and bidirectional PFC stages handle regenerative energy.

DC-link voltage thresholds, precharge timing and regenerative strategies are detailed in the front-end power-supply and brake chopper topics. This section defines the hooks the ACIM inverter should provide so that those power stages can be integrated without redesigning the inverter every time the front end evolves.

PWM generation, dead-time and modulation options

The ACIM inverter bridge relies on a PWM strategy that fits the chosen power devices, switching frequency and acoustic and efficiency targets. Typical carrier frequencies for AC induction motor drives range from a few kilohertz up to the mid-teens, with sinusoidal PWM and space-vector PWM (SVPWM) as the dominant modulation schemes. The choice affects current ripple, audible noise and switching losses, and therefore directly influences the thermal design of the inverter.

Sinusoidal PWM remains widely used in fans, pumps and general-purpose drives where simple implementation and predictable performance are valued. SVPWM takes better advantage of the available DC-link voltage, improving voltage utilization and harmonic performance, which benefits high-performance ACIM applications and FOC-based control. In both cases the inverter hardware expects clean complementary gate-drive signals with properly inserted dead-time to prevent shoot-through.

Dead-time is inserted to ensure that the high-side and low-side devices in each leg are never on simultaneously. Larger dead-times increase safety margin but also introduce more distortion into the output waveform, which degrades low-speed torque accuracy and can increase harmonic losses. Very small dead-times improve linearity but demand careful attention to device turn-off characteristics, gate-drive strength and propagation delays, especially over temperature and device tolerances.

Power-stage requirements on PWM and dead-time:

• Gate-driver propagation delays should be well matched across phases and legs.
• Gate drivers should support a configurable dead-time range suitable for the devices used.
• Turn-off and turn-on sequencing must follow device recommendations to avoid shoot-through.
• Hardware shoot-through protection, desaturation detection or fast over-current shutdown is essential.
• For higher switching frequencies, gate-drive strength and dv/dt control must balance switching loss and EMI.

Controller-side hooks that the inverter expects:

• Timer units that generate complementary PWM outputs with programmable dead-time.
• Synchronised ADC trigger points for current and DC-link voltage sampling relative to the PWM cycle.
• Fault inputs that can force hardware PWM shutdown on over-current, desaturation or over-voltage trips.
• Capture or comparator resources to support calibration of actual propagation delays and dead-time values.

Switching frequency selection trades acoustic behaviour against losses and device stress. Lower frequencies keep switching losses down but push ripple and acoustic content into sensitive bands, while higher frequencies move those artefacts upward at the cost of greater dissipation. The table below summarises typical trade-offs for ACIM applications.

Phase-current sensing strategies for ACIM drives

Phase-current sensing defines how much information the ACIM inverter can provide to the control and protection layers. For AC induction motor drives, three main strategies are used around the inverter bridge: three individual phase shunts, two shunts with current reconstruction and a single shunt in the DC link. Each option trades cost, complexity, sampling-window constraints and suitability for high-performance FOC or simpler V/f schemes.

Three-shunt sensing places a resistor in series with each phase leg, delivering the most complete view of phase currents for field-oriented control and detailed diagnostics. Two- shunt sensing removes one shunt and reconstructs the third current from the other two, reducing cost and analog front-end count while keeping most of the information needed for FOC. Single-shunt sensing measures DC-link current and relies on PWM timing and reconstruction algorithms, which keeps hardware cost low but demands tighter coordination between PWM generation and ADC sampling.

The goal in this section is to position the shunts and define which ADC or ΣΔ channels must be available, not to select specific current-sense amplifiers, isolated modulators or Hall sensors. Those details are handled in the phase and bus current-sensing topic. The emphasis here is on where to measure currents, how many channels are required and how each strategy aligns with FOC or V/f control expectations.

Three-phase shunts for FOC-ready sensing:

• One shunt in series with each inverter leg, typically placed in the low-side return path.
• Provides direct measurement of all three phase currents for vector control and diagnostics.
• Requires multiple ADC or ΣΔ channels and tight synchronisation with PWM sampling windows.
• Delivers the most flexibility for future algorithm updates and advanced condition monitoring.

Two shunts with reconstruction of the third phase:

• Shunts placed in two of the three phases, with the third current reconstructed from Kirchhoff’s law.
• Reduces the number of shunts and analog front-end channels while retaining adequate information for FOC.
• Works well when phase currents remain reasonably balanced and ADC linearity and synchronisation are good.
• Requires protection thresholds and diagnostics to account for reconstruction error under extreme imbalance.

Single-shunt DC-link current sensing:

• A single shunt in the DC-link return measures the inverter input current instead of individual phase currents.
• Minimises hardware cost and current-sense component count, attractive for small ACIM drives.
• Needs carefully planned PWM patterns and ADC trigger timing to reconstruct phase currents during valid windows.
• Well suited to V/f control and protection-oriented sensing and usable for FOC with dedicated reconstruction schemes.

In summary, three-shunt sensing is the natural fit for high-performance FOC and rich diagnostics, two-shunt sensing keeps most of that capability with lower hardware cost, and single-shunt DC-link sensing pushes complexity into timing and reconstruction in exchange for minimal bill-of-materials. Amplifier, ΣΔ modulator and isolation choices attach on top of these layouts and are treated separately in the phase and bus current-sensing topic.

DC-link, bus-voltage and thermal sensing hooks

DC-link voltage and thermal measurements around the ACIM inverter provide the protection and derating information needed for safe operation over the drive lifetime. The DC link acts as an energy buffer between the rectifier or PFC front-end and the inverter bridge, and its voltage and temperature directly influence switching limits, regenerative behaviour and capacitor life. Thermal sensing on the power module and heat-sink allows the control system to manage loss distribution and protect semiconductor junctions.

This section focuses on signal hooks and sensing locations rather than detailed analog front-end design. The intent is to identify where the DC-link voltage should be measured, how over-voltage events are detected quickly and where temperature sensors should be placed on the inverter assembly. The implementation of dividers, buffers, NTC networks and digital temperature sensors is handled in the thermal and current-sensing topics.

DC-link voltage sense into the controller ADC:

• A resistive divider from the DC link feeds a buffered signal into an MCU or DSC ADC channel.
• The divider ratio and buffer range must cover expected DC-link levels for 230, 400 and 480 Vac systems.
• Sufficient resolution is needed to distinguish under-voltage, nominal operation and derating thresholds.
• Bandwidth can be modest, focusing on average DC-link level rather than high-frequency ripple content.

Bus ripple and over-voltage detection through fast comparators:

• A high-speed comparator monitors the divided DC-link voltage and asserts an over-voltage fault when a programmable threshold is exceeded.
• The comparator output typically feeds gate-driver fault inputs or a central protection IC, providing a path for rapid inverter shutdown.
• Additional comparator thresholds can support staged responses such as warning, derating and immediate trip levels.
• Comparator outputs are often latched and reported to the controller so that the drive history records the cause of each shutdown.

Thermal sensing on the power module, heat-sink and DC-link capacitors:

• At least one temperature sensor is placed on or near the power module or heat-sink to estimate junction temperature and enforce thermal derating or shutdown limits.
• A second sensor is typically positioned near the DC-link electrolytic capacitors to track long-term temperature exposure and lifetime stress.
• Additional sensors may monitor ambient cabinet temperature or specific hotspots identified during thermal design and validation.
• Temperature signals feed the controller for fan control, current derating, alarm reporting and long-term predictive maintenance functions.

Together, DC-link voltage sensing, fast over-voltage detection and thermal monitoring provide the hooks needed for robust inverter protection and lifetime management. Detailed amplifier, NTC network and digital temperature-sensor options are developed in the thermal sensing and control topic, using the sensing locations and signal roles defined here as a starting point.

Faults, protection limits and what the inverter must report

Protection in an AC induction motor drive is shared between the inverter hardware, the motion controller and any external safety and braking functions. The inverter power stage is closest to the semiconductors and DC link, so it must detect fast electrical faults, capture key operating limits and present clear fault signals and diagnostic information to the controller and safety monitor. This section defines which fault conditions the inverter must recognise and which signals must be available at its interface.

The emphasis is not on writing a complete protection standard but on making explicit which comparators, sensing hooks and fault outputs the inverter must expose. Higher-level decisions such as restart policies, derating strategies, brake-chopper coordination and safe torque-off behaviour are handled in the protection, safety and braking topics. Here, the inverter is treated as a power module that reports what it sees at the phase legs, DC link and temperature sensors.

Key fault conditions that the inverter module must detect:

• Phase overcurrent and shoot-through – fast detection of leg overcurrent, short-circuit or desaturation, followed by hardware turn-off and a latched fault output.
• DC-link overvoltage and undervoltage – monitoring of DC-link level for excessive voltage due to regeneration or front-end faults and for undervoltage conditions that compromise gate drive or motor torque.
• Overtemperature – sensing of power-module, heat-sink and DC-link capacitor temperatures, with at least one threshold mapped to an overtemperature fault.
• Single-phasing and mains unbalance – where line-side detection is available, indication that one phase is missing or strongly unbalanced and that torque capability and heating have changed.
• Stall or locked-rotor indication – combination of sustained high current and missing speed feedback or near-zero slip to indicate a rotor that is not turning as commanded.

Responsibility split for each fault type:

• The inverter module provides comparators, sensing points, fast shutdown paths and fault output pins or diagnostic status bits for each relevant condition.
• The motion controller or drive MCU interprets fault signals and measurements, applies derating logic, restart policies and alarm reporting.
• Safety monitors and STO functions use the inverter’s fault lines as inputs to higher- integrity safety functions defined in the protection, safety and braking topics.

The table below summarises which conditions the inverter must recognise and which signal or data must leave the module so that system-level protection and safety functions can act on them.

Controller interface — how the MCU/DSC talks to the inverter

The ACIM inverter behaves as a power module that responds to PWM and enable signals, delivers measured currents, voltages and temperatures and reports fault and status conditions. The motion controller or DSC must provide enough PWM channels and control lines to drive the three-phase bridge, enough ADC channels to capture the required sensing information and enough digital inputs to latch and diagnose faults. Optional encoder or speed feedback further widens the interface in high-performance drives.

This section focuses on signal counts and groupings at the inverter boundary rather than on controller selection or FOC library details. The intent is to show how many PWM outputs, analog inputs, fault pins and status lines are typically required when planning the controller interface. Timing, interrupt load and software architecture are addressed in the motion-controller topic.

PWM and enable signals from controller to inverter:

• Three complementary PWM pairs (six outputs) for the three-phase bridge, or at least three single-ended PWM outputs in simpler V/f drives.
• One or more enable or shutdown lines to gate-driver ICs and inverter power stage.
• Optional synchronisation or reference clock output when multiple axes or drives require phase alignment or time stamping.

Sensing inputs into the controller ADC:

• Two or three phase-current channels or a combination of phase and DC-link current channels, depending on the chosen sensing architecture.
• One DC-link voltage measurement channel for regulation, derating and protection.
• Two or more temperature channels for the power module, heat-sink, DC-link capacitors and any identified hotspots or ambient locations.
• Optional additional analog inputs for auxiliary sensors such as line-voltage monitors or cabinet thermal sensors.

Fault and status outputs from inverter to controller:

• Fast hardware fault inputs for overcurrent, desaturation and DC-link overvoltage events that must shut down the inverter immediately.
• Overtemperature and undervoltage status signals, including warning-level outputs where staged derating is required before hard trips.
• Ready and precharge status lines, indicating that DC-link precharge has completed and that the inverter is allowed to accept PWM drive.
• Optional brake-chopper activity or mains-unbalance indicators for integration into system-level diagnostics and safety decisions.

Optional encoder and speed feedback hooks:

• Incremental or absolute encoder interfaces for ACIM drives that use encoder-based FOC, mapped to the dedicated encoder-interface topic.
• Sin-Cos, TTL or digital encoder signals routed to capture/compare units or dedicated encoder interface modules in the controller.
• For sensorless drives, the inverter still needs to expose motor-current and DC-link information with sufficient fidelity to support estimator algorithms.

A typical ACIM FOC drive therefore requires six PWM outputs, five to six ADC channels for currents, DC-link voltage and temperatures, several fast fault inputs and a small set of status and control lines. Encoder interfaces and additional sensing expand this baseline where performance or diagnostics demand it, and the inverter’s I/O definition becomes a key input to controller selection and pin-budget planning.

Design checklist & IC vendor mapping for ACIM V/F–FOC inverter

This closing section turns the ACIM V/F–FOC inverter topic into a practical checklist and a vendor-mapping guide. The checklist groups key decisions on the line and DC link side, the inverter bridge and modulation, sensing and protection hooks and integration with the control MCU or DSC. The vendor mapping then links typical integrated-circuit roles in an AC induction motor drive inverter to major suppliers and their established product families and reference designs, without drilling into specific device numbers.

The intent is to make it easy to verify that all critical decisions around the ACIM inverter and its interfaces have been addressed and that suitable IC families and reference designs are identified for gate drivers, current sensing, DC-link monitoring, thermal sensing and controller platforms. Detailed signal-chain selection for current sensing, thermal interfaces and safety functions is developed in the dedicated sensing and protection topics.

A. ACIM V/F–FOC inverter design checklist

The checklist below groups design decisions into four domains. Each bullet represents a specific point that should be confirmed before an AC induction motor inverter design is considered ready for prototype build or design review.

Line and DC-link side:

• Line voltage, frequency and allowed power-factor and THD limits are clearly defined for the target grid and application.
• The choice between simple diode rectifier and active PFC has been made and reflected in DC-link voltage targets and power-quality expectations.
• DC-link nominal voltage, allowable operating window and ripple envelope are specified and matched to capacitor ratings and precharge strategy.
• Short-term overvoltage scenarios, including regeneration and upstream protection trips, have been considered and tied into brake-chopper or PFC behaviour.
• Line-side protection, fusing and EMC filtering are defined and consistent with the selected rectifier or PFC architecture.

Inverter bridge and modulation:

• Switching device voltage ratings are chosen with suitable margin over the maximum DC-link and line-transient conditions and are checked against device SOA.
• A switching-frequency range has been selected with clear trade-offs between losses, acoustic noise and EMI for the ACIM application.
• The modulation scheme (such as sinusoidal PWM or SVPWM) is defined and compatible with the motion-control firmware and gate-driver timing.
• Dead-time requirements and gate-driver propagation delays are understood and budgeted, balancing shoot-through protection against current waveform distortion.
• ACIM-specific risks such as single-phasing, high dv/dt stress on windings and cables and harmonic losses have been considered in layout and filter decisions.

Sensing and protection hooks:

• The phase-current sensing strategy (three shunts, two shunts with reconstruction or single DC-link shunt) is selected and corresponding ADC or ΣΔ channels are allocated.
• DC-link voltage sensing, including divider, buffering and ADC channel, is designed to cover the full operating window with adequate resolution.
• A fast DC-link overvoltage comparator, and where required undervoltage or brown-out detection, is implemented with clear fault outputs.
• At least one temperature sensor on the power module or heat-sink and one near the DC-link capacitor bank are placed and wired into the monitoring chain.
• Essential fault and status signals (overcurrent, overvoltage, overtemperature, ready, precharge complete, brake-chopper status) are routed from the inverter to the motion controller and safety monitor.
• Required connections into the protection, safety and braking chain, including STO related signals, are identified and reserved.

Integration with the control MCU or DSC:

• The number of PWM channels, including complementary outputs if needed, fits within the controller’s timer resources with margin for future features.
• Available ADC channels and sampling triggers cover phase currents, DC-link voltage and temperature inputs with suitable sampling rates for V/F or FOC control.
• Fast fault inputs and digital pins for OC, OV, OT and other hard protection events are available on suitable interrupt-capable or dedicated fault-input pins.
• Interfaces for STO and higher-integrity safety modules are mapped, including any dual-channel requirements and feedback paths.
• Pins are reserved where possible for future upgrades, such as encoder-based FOC, extra temperature sensors or extended diagnostics.

B. IC vendor mapping for ACIM inverter roles

The table below maps typical AC induction motor inverter IC roles to major semiconductor vendors. It highlights families and reference-design coverage at a functional level rather than listing specific part numbers. Detailed device selection for current sensing, thermal interfaces, protection and control should build on the families indicated here and the dedicated sensing and protection topics.

FAQs — ACIM V/F–FOC inverter

These twelve questions collect the main decisions around AC induction motor V/F–FOC inverters into compact, reusable answers. Each FAQ focuses on practical design choices: when V/F is enough, when FOC and encoders become necessary, how many current and voltage sensors are needed and how DC-link, braking, fault and MCU interfaces should be planned.