Resolver-to-Digital ICs for Motor & Motion Control
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This page organises resolver-to-digital design into a complete signal chain, showing how to plan excitation, AFEs, angle solvers, diagnostics and safety so a motion axis can meet its accuracy and robustness targets. It ends with a sourcing checklist and FAQs that turn these technical trade-offs into concrete questions for vendors and internal design reviews.
What this page solves
This page focuses on resolver-to-digital signal chains for motion and servo drives that run in harsh, noisy and mechanically demanding environments. It is written for motion engineers who need stable position feedback over long cables, across wide temperature ranges and in high vibration conditions.
The content helps compare two main implementation paths: using a dedicated resolver-to-digital IC that integrates excitation, analog front-end and digital angle solver, or using an MCU or DSC to drive the resolver and process the raw sine and cosine signals directly. The emphasis is on what changes in accuracy, latency, diagnostics coverage and design complexity when each approach is used.
Throughout the page, resolver feedback is broken down into the key trade-offs that matter in a real motor or motion-control project: how much angle resolution is needed, how much latency the FOC and motion loops can tolerate, how EMC and cable routing impact signal integrity, and how much diagnostic visibility and safety coverage the system requires. The goal is to turn the resolver feedback chain into a clear decision map instead of a trial-and-error exercise.
- When resolver feedback is a better fit than digital encoders or Hall sensors.
- When to choose a dedicated resolver-to-digital IC versus an MCU-based solution.
- How accuracy, latency, EMC robustness and diagnostics interact in the final design.
Resolver signal chain overview
A resolver-to-digital architecture can be viewed as a series of well-defined building blocks. The signal starts as a controlled sine excitation from the drive electronics, passes through the resolver and long cables, is conditioned by differential AFEs and ADCs, and is then converted into a digital angle by a CORDIC or tracking engine before reaching the motion controller.
In many resolver-to-digital ICs, excitation generation, analog front-ends, ADCs and the digital solver are integrated into a single device with angle outputs and diagnostics. In other designs, the resolver chain is implemented using discrete AFEs and ADCs around an MCU, DSC or FPGA. The rest of this page treats each block as a separate design decision so that the same mental model works for both integrated and discrete implementations.
The diagram below summarizes the resolver signal path and highlights the logical interfaces between blocks: excitation drive into the resolver, sine and cosine return paths through AFEs and ADCs, the digital solver and diagnostics inside the resolver-to-digital core, and the final angle and status reporting into the FOC and motion-control layers.
Sine excitation & resolver electrical interface
Resolver excitation is the starting point of the entire resolver-to-digital chain. The excitation frequency and amplitude set the available signal-to-noise ratio for the sine and cosine returns, while the waveform linearity and drive capability determine how much distortion and drift appear before the analog front-ends and ADCs. Typical resolver systems operate in a few kilohertz range, balancing transformer efficiency, cable losses and EMC behaviour against the bandwidth and sampling constraints of the drive controller.
Excitation drive can be handled by an integrated driver inside a resolver-to-digital IC or by an external power stage that buffers the IC reference. An integrated driver reduces design effort and keeps amplitude and phase closely tied to the internal solver, but is limited by its maximum output current and cable length capability. External buffers or power amplifiers support higher current, longer cables and multiple resolver loads, at the cost of extra layout effort, distortion control and thermal design for the driver and its supply rails.
The electrical interface between the excitation source and the resolver windings must also account for single-ended versus differential drive, cable impedance and common-mode noise. Differential excitation with twisted, shielded pairs and carefully chosen output impedance improves rejection of common-mode interference from high dv/dt power stages. As cable length increases, the resistance and capacitance of the harness introduce attenuation and phase shift, so the excitation driver must be specified against realistic line parameters rather than ideal conditions.
From a sourcing and data-sheet point of view, resolver excitation planning comes down to a short set of key questions: whether the resolver-to-digital IC provides sufficient drive current on its own, whether the available frequency range and distortion performance align with the resolver and axis requirements, and whether protection and diagnostics around the excitation path are adequate for the safety and reliability targets. EMC filtering, shielding and insulation monitoring are handled at the system level and should be cross-checked against the EMC Subsystem and Insulation & Safety Monitor topics.
- Define target excitation frequency range, amplitude and current based on the resolver and cable.
- Decide between integrated excitation drivers and external power buffers or amplifiers.
- Plan single-ended or differential drive, shielding and common-mode suppression for the harness.
- Check data sheets for drive capability, THD, adjustable frequency range and protection features.
Differential AFE & ADC architecture
After the resolver and cables, the sine and cosine signals enter differential analog front-ends that set the effective signal-to-noise ratio and linearity delivered to the ADCs. Instrumentation amplifiers and programmable-gain stages must provide high common-mode rejection, precise gain and low noise while keeping both channels well matched in gain and phase. Anti-alias filters shape the bandwidth around the chosen excitation and sampling frequencies so that switching noise and harmonic content do not fold back into the angle computation band.
The choice between SAR and sigma-delta conversion affects both timing and achievable resolution. SAR ADCs offer moderate resolution with short latency and flexible triggering, which simplifies alignment to PWM or FOC time bases. Sigma-delta modulators and converters deliver excellent linearity and noise performance through oversampling and digital filtering, at the cost of group delay that must be accounted for in the resolver tracking loop and motion-control bandwidth planning. In either case, simultaneous sampling or tightly synchronized conversions of the sine and cosine channels are essential to avoid time skew turning into angle error.
Error mechanisms in the resolver AFE and ADC path include gain and offset mismatch between the two channels, phase mismatch from unequal filters and sampling instants, wideband and low-frequency noise, and imbalances introduced by the cables and termination network. Gain errors distort the Lissajous circle into an ellipse, offset errors shift it away from the origin and phase errors twist the effective angle mapping. Noise and jitter limit the usable resolution of the angle output even when the ADC resolution appears high on paper, so ENOB and dynamic range must be interpreted in the context of the resolver’s operating bandwidth and expected signal levels.
From a sourcing perspective, the resolver AFE and ADC chain is defined by a small set of parameters: input common-mode range, differential input range and CMRR in the excitation frequency band; noise density and programmable gain granularity for the AFE; and ENOB, SNR, sampling rate, group delay and synchronization features for the converter. The same front-end techniques used in phase and bus current sensing also apply here, but resolver applications typically impose tighter matching requirements between the sine and cosine paths because any mismatch is directly translated into angle error. The Phase/Bus Current Sensing page covers current-measurement specific trade-offs that complement this resolver-focused view.
- Specify differential AFEs with adequate CMRR, noise and programmable gain for resolver levels.
- Design matched anti-alias filters so sine and cosine channels share the same gain and phase profile.
- Choose SAR or sigma-delta ADCs based on latency, resolution and tracking-loop timing needs.
- Budget gain, offset, phase and noise errors as contributors to final resolver angle accuracy.
- Verify simultaneous or synchronized sampling support for the resolver channels in the converter.
Digital angle solver & timing integration
After the resolver sine and cosine signals are sampled, a digital angle solver converts the samples into a position value that is stable, low noise and suitable for field-oriented control and motion loops. Typical implementations combine CORDIC engines and tracking loops so that the system can resolve fine angle steps while following rapid mechanical motion without losing lock. Solver design defines practical limits on resolution, maximum tracking speed, lock-in time and total delay through the resolver-to-digital path.
Resolution in bits describes how finely the angle output is quantized, but effective usable precision is also influenced by noise, linearity and error sources in the analog and digital chain. Maximum tracking rate and lock-in time determine how fast the axis can accelerate or change speed before the solver slips or reports degraded status. Combined group delay through ADC filtering and digital processing dictates how far behind real mechanical motion the reported angle sits, which must be accounted for in current and torque-loop stability analysis.
At the interface level, digital angles are delivered to the motion controller over parallel ports, SPI, SSI or other synchronous serial links. Some devices provide index and synchronization pulses that define reference positions or allow deterministic alignment between angle samples and PWM or FOC interrupt boundaries. The motion controller needs a clear contract about update rate, latency and data-valid timing so that current sampling, angle acquisition and control computations remain phase aligned over temperature, speed and fault conditions.
From a sourcing perspective, the digital solver is characterized by a small set of timing and accuracy parameters: delay from analog input to valid angle, maximum tracking rate and lock-in behaviour, angle jitter, static angle linearity and the details of the digital output protocol. These parameters must be checked against servo bandwidth, worst-case mechanical speed and safety requirements so that the resolver-to-digital chain supports the intended motion profile without hidden stability or accuracy penalties.
- Understand how CORDIC and tracking loops combine to set angle resolution, speed and lock-in limits.
- Budget total latency and jitter from resolver samples to angle words used in FOC and motion loops.
- Align digital angle outputs with PWM and current-sampling timing using sync pulses or deterministic reads.
- Check data sheets for delay, maximum tracking rate, jitter and angle linearity versus axis targets.
Error budget & calibration options
Resolver-based position feedback accuracy is determined by multiple error contributors spread across the mechanical resolver, excitation path, analog front-ends, ADCs and digital angle computation. A structured error budget separates these contributions into manufacturing and installation tolerances, amplitude and phase variations from excitation and cabling, AFE gain and offset mismatch, ADC quantization and noise, and residual error from the angle solver and filtering. Breaking the problem into these blocks makes it clear which errors can be reduced by component selection and which require calibration and compensation.
Resolver manufacturing and mechanical alignment errors introduce periodic angle deviation over one revolution, affected by rotor eccentricity, winding asymmetry and mounting. Excitation amplitude changes with supply and temperature, and cable resistance and capacitance modify the effective signal delivered to the AFEs. Analog front-ends then add gain and offset mismatch and finite CMRR, while filter and sampling skew create phase mismatches between sine and cosine channels. ADC resolution and noise limit the minimum angle step that can be resolved without excessive jitter, even when the nominal resolution is high.
Digital angle calculation adds its own layer of imperfection through finite internal bit width, CORDIC implementation details, numeric approximations and the dynamics of tracking loops and digital filters. Some of these contributions are essentially static and can be mapped and compensated, while others behave as random noise or slowly drifting bias with temperature, ageing or load. A practical resolver error budget therefore combines worst-case static error terms with noise and drift terms and defines what level of correction must be applied in production and what level of residual error the drive and motion-control system can tolerate.
Calibration strategies range from factory turntable calibration, where high-accuracy reference encoders or rotary tables are used to measure and correct angle error over a full revolution, to online self-test and health monitoring that track drift over temperature and lifetime. Compensation can be implemented using lookup tables, polynomial or harmonic correction and built-in gain and offset trimming registers in the resolver-to-digital IC. For sourcing and specification, each error source can be associated with an approximate magnitude, a preferred mitigation method and a set of data-sheet parameters that need to be checked so that the combined system meets the positioning and safety targets of the motion axis.
- Identify error contributions from the resolver, excitation, AFEs, ADCs and digital solver separately.
- Decide which errors will be reduced by selection and layout and which require calibration and compensation.
- Plan factory calibration, online self-test and lookup or polynomial correction against target accuracy.
- Use a structured table to map each error source to magnitude, mitigation and key resolver-to-digital parameters.
Diagnostics, redundancy & safety hooks
Resolver-to-digital ICs carry a rich set of diagnostic functions that monitor the resolver excitation, cable harness and sine/cosine return paths for open and short circuits, amplitude imbalance and excessive distortion. Many devices analyse the shape of the incoming resolver signals, detect tracking errors in the angle loop and provide built-in self-test for internal references, converters and logic. These health indicators are essential for deciding whether the reported angle can be trusted in motion control and safety-related applications.
Cable fault and imbalance diagnostics typically cover excitation winding open or short conditions, short to ground or supply on the sine and cosine lines and large deviations in signal amplitude. More advanced devices provide metrics for harmonic distortion or deviations from an ideal Lissajous circle, which reveal saturation, non-linear loading or wiring issues. Tracking-error flags indicate loss of lock or operation outside the defined tracking rate, while lock indicators confirm that the digital angle has settled and follows actual shaft motion within specified limits.
In safety projects, these diagnostics form one layer of defence in a broader architecture. A single resolver channel with high diagnostic coverage can support applications where functional safety is achieved through a combination of hardware monitoring and defined safe-state reactions. For higher integrity levels, system designers often deploy dual resolvers, dual resolver-to-digital channels or resolver plus encoder combinations and then compare the two position paths in a safety monitor or safety PLC. The resolver chain contributes health and plausibility information rather than serving as the only arbiter of axis safety.
Resolver-to-digital ICs expose their diagnostic findings through fault pins, dedicated safety outputs and status words on SPI, SSI or fieldbus links. Safety monitors and safety PLCs use these signals alongside torque-path information from Safe Torque Off functions and isolation status from insulation monitors to decide whether torque can remain enabled. By planning how each diagnostic flag, error code and quality metric propagates into the overall safety function, the resolver feedback chain can support safe position, safe speed and controlled stop functions rather than simply feeding a single angle value into the drive firmware.
- Leverage cable, amplitude, distortion and tracking diagnostics to assess resolver signal quality.
- Choose between single-channel with diagnostics and multi-channel resolver architectures for safety goals.
- Route fault pins and detailed status words into safety monitors and safety PLC logic.
- Cross-link resolver diagnostics with Safe Torque Off and insulation monitoring in the overall safety concept.
Application examples & system hooks
Resolver-to-digital chains appear across a wide range of motion systems, from compact servo drives and robot joints to long-stroke linear axes and harsh-environment actuators. The same core building blocks are reused, but each application places different emphasis on angle resolution, bandwidth, cable length, safety integration and lifetime robustness. Mapping these differences helps match specific resolver and R/D IC combinations to axis-level requirements instead of treating the resolver feedback as a generic position encoder.
Servo drives and robot joints
In servo drives and robot joints, the resolver-to-digital chain sits at the centre of the field-oriented control loop. The digital angle feeds high-bandwidth current and torque loops, as well as outer position and velocity loops that handle precise point-to-point moves and contouring. Joint cabling and rotating harnesses often require long, flexible resolver cables with strong immunity to inverter switching noise, making differential excitation, robust AFEs and high-quality tracking essential. Safety-related robot functions such as safe position and safe speed rely on resolver diagnostics and redundant channels combined with safety PLC logic and Safe Torque Off mechanisms.
Lifts, linear axes and conveyors
In lifts, linear drives and conveyor systems, resolver feedback supports safe and repeatable stopping at floors, stations or mechanical end positions. The required bandwidth is often lower than in high performance servos, but cable runs from control cabinets to mechanisms can be long and exposed to industrial interference. The resolver chain must tolerate voltage drops, common-mode disturbances and environmental noise while still providing reliable angle information to position loops and safety functions. Resolver diagnostics feed into safety controllers that supervise overspeed, overshoot and limit conditions alongside brake control, soft-start and controlled-stop power-stage functions.
High-temperature and high-vibration drives
Machine-tool spindles, high-speed grinding heads and wind-turbine pitch actuators operate in conditions where temperature, vibration and contamination make optical encoders difficult to apply. Resolver-based feedback combined with a suitable resolver-to-digital chain provides robust position sensing for spindle orientation, C-axis control or blade pitch positioning. The resolver and R/D IC must support wide temperature ranges, tight drift control and long-term stability, while safety functions depend on redundancy, insulation monitoring and reliable brake and torque-off behaviour. In these systems, the resolver chain contributes both precise angle information and long-term survivability under demanding environmental stresses.
- Use resolver-to-digital chains as the primary FOC feedback in servo drives and robot joints.
- Exploit cable robustness and diagnostics to support long runs in lifts, linear axes and conveyors.
- Apply resolver feedback in high-temperature and high-vibration drives where optical encoders struggle.
- Connect resolver chains to power stages, safety monitors and communication interfaces as a system-level design.
IC mapping & sourcing checklist
This section turns the resolver-to-digital discussion into a practical sourcing checklist that can be used when comparing resolver ICs, mixed-signal front-ends and MCU-based solutions. Each group of items links back to the signal-chain requirements: excitation drive capability, angle resolution and tracking behaviour, analog front-end robustness, digital interface choices and safety diagnostics. The goal is to align data-sheet parameters and vendor proposals with the mechanical, electrical and safety targets of the motion axis instead of judging parts by resolution alone.
The checklist can support design reviews and supplier discussions across multiple vendors. Excitation drive capability and frequency range must match the selected resolver and cable harness. Angle resolution, maximum tracking speed and group delay must be consistent with field-oriented control, maximum mechanical speed and servo bandwidth. Analog input ranges, common-mode tolerance and cable fault diagnostics indicate how well an IC will survive real-world plant environments. Interface modes, status reporting and safety documentation determine how smoothly the resolver chain can be integrated with servo power stages, safety monitors and industrial networks.
Leading resolver-to-digital suppliers span several profiles: some specialise in automotive and safety applications with ISO 26262 documentation and high diagnostic coverage; others focus on industrial servo drives and EtherCAT-based motion controllers, offering resolver interfaces as part of dedicated motor-control MCUs; still others deliver high-resolution mixed-signal front-ends that rely on FPGA or DSP-based angle solvers. Using the checklist below makes it easier to map these vendor profiles to the needs of servo drives, robot joints, lifts, linear axes and harsh-environment actuators without tying the design to a single brand.
Key resolver-to-digital sourcing checkpoints
- Excitation capability and frequency range for the chosen resolver and cable length.
- Angle resolution, maximum tracking speed, lock-in behaviour and total delay through the chain.
- AFE input range, common-mode tolerance, noise performance and cable fault diagnostics.
- Digital and analog interface options for integration with FOC MCUs, FPGAs and servo drives.
- Safety diagnostics, safety documentation and long-term availability for the motion platform.
Resolver-to-digital IC mapping & supplier questions
| Check item | Questions for vendors | Key data-sheet fields | Notes / target level |
|---|---|---|---|
| Excitation capability & frequency | Supported excitation frequency range and recommended operating band? Ability to drive the selected resolver and cable without an external power stage? Typical amplitude accuracy and distortion over temperature? | Excitation frequency range, output amplitude or current, load range, THD vs frequency, thermal limits. | Match resolver spec (for example 2–10 kHz) and cable length; reserve margin for ageing and temperature. |
| Angle resolution & effective accuracy | Nominal angle resolution in bits and typical repeatability or noise at the intended excitation frequency? Any curves of angle jitter versus speed or temperature? Guidance on effective ENOB in real servo applications? | Angle resolution, angle noise or jitter, repeatability, ENOB, static linearity plots. | Align with required torque ripple, speed smoothness and position accuracy of the axis. |
| Maximum tracking speed & lock-in behaviour | Maximum mechanical speed and tracking rate for the planned excitation frequency? Conditions that cause lock loss or degraded tracking? Typical lock-in time after power-up or after a transient disturbance? | Maximum tracking rate, maximum mechanical speed, tracking-error flags, lock indicator behaviour. | Ensure margin over worst-case speed profile and acceleration for the motor and gearbox. |
| Delay & angle jitter | Group delay from analog inputs to valid angle output under the intended filter settings? Angle update period and timing jitter? Mechanisms to latch angle synchronised to PWM or current-sense sampling points? | Pipeline delay, latency vs filter mode, angle update rate, timing jitter, latch or sync features. | Compare with FOC and current-loop bandwidth; maintain sufficient phase margin in control design. |
| AFE input range & common-mode tolerance | Supported differential input range for sine and cosine channels and allowed common-mode range? Recommended front-end topology for the expected cable length and noise environment? Any limits on input impedance or shielding? | Input range, common-mode range, input impedance, CMRR vs frequency, recommended circuits. | Verify compatibility with resolver output levels, cable characteristics and EMC constraints. |
| Cable diagnostics & distortion monitoring | Which cable faults are detectable: open circuits, shorts between lines, shorts to ground and to supply? Any distortion or Lissajous-shape monitoring to flag non-linear behaviour? How quickly are faults reported and through which pins or registers? | Fault detection list, detection thresholds, diagnostic response time, fault pins, status bits. | Map diagnostic coverage to the safety concept and maintenance strategy for the axis. |
| Interface modes & system integration | Available digital interfaces (SPI, SSI, parallel or micro-parallel) and their timing limits? Options for sin/cos pass-through to MCUs or FPGAs? Any safety-oriented protocols or frame protection features available? | Interface types, maximum clock rates, frame formats, CRC support, pass-through options. | Align interface choices with FOC controller architecture, fieldbus and safety-channel needs. |
| Safety diagnostics & documentation | Available diagnostics beyond cable faults, including internal BIST, memory checks and tracking error flags? Any functional-safety documentation such as safety manuals, FMEDA data or certified libraries? Typical use cases and achievable safety levels? | Diagnostic feature list, safety manual, FMEDA, certification status, recommended safety use cases. | Ensure compatibility with required ASIL or SIL levels and planned safety architecture. |
| Environment, lifetime & ecosystem support | Supported temperature and voltage ranges, lifetime data and derating guidelines? Reference designs and software support for typical servo and motion platforms? Long-term availability and roadmap for resolver-capable devices? | Operating range, lifetime data, reference designs, motor-control libraries, longevity program details. | Match lifetime, environmental and software-ecosystem needs of the target market segment. |
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FAQs about resolver-to-digital planning & selection
1. When do I actually need a dedicated resolver-to-digital IC instead of using my motion MCU’s ADC channels?
When the axis needs higher resolution, synchronized sampling and built-in tracking loops than the generic ADC can provide, I move to a dedicated resolver-to-digital IC. I also switch when I need integrated excitation drive, line diagnostics, safety documentation or when the MCU’s CPU load cannot tolerate continuous CORDIC or tracking calculations.
2. How much resolver angle resolution is really needed for a typical servo axis?
For most servo axes, I size angle resolution so that quantisation and noise are well below the torque ripple and mechanical backlash I can tolerate. That often means targeting at least 12–14 effective bits at the shaft, then checking that speed loops and position accuracy targets are still comfortably met.
3. How do I estimate the maximum tracking speed for my resolver and target motor speed profile?
I start from the maximum mechanical speed and gear ratio, convert that to electrical speed with the resolver pole count, then compare it with the data-sheet tracking rate. I also add margin for acceleration and transients so that the tracking loop does not unlock during fast moves or faults.
4. What level of delay and angle jitter is acceptable for real-time field-oriented control?
I treat resolver-to-digital delay as part of the current-loop phase lag budget. If the total group delay pushes phase margin too low at the target bandwidth, I tighten the specification. I also limit angle jitter so that torque ripple, acoustic noise and position dither stay within acceptable limits.
5. What excitation frequency range should I plan for, and when do I need external excitation drivers?
I first check the resolver’s recommended excitation band, then choose an IC that comfortably covers that range with good distortion and thermal headroom. When the cable is long or the resolver load is heavy, I look for either stronger on-chip excitation drive or a documented path to add external drivers.
6. Which resolver cable length and EMC conditions force me to care about differential AFEs and line diagnostics?
Once cable runs leave the cabinet or share space with inverter and contactor wiring, I move to fully differential AFEs with good CMRR and clear layout guidance. I also insist on built-in cable diagnostics so open, short or imbalance conditions are reported before they become unsafe or hard to debug.
7. What are the main error sources in a resolver-to-digital chain, and how are they usually calibrated?
I treat resolver manufacturing tolerances, excitation amplitude variation, AFE gain and offset, phase mismatch, ADC quantisation and angle-algorithm non-linearity as separate contributors in the error budget. Factory calibration, online self-calibration and table or polynomial compensation let me trim out systematic components and leave only random residual error.
8. Can resolver diagnostics alone support my functional safety goals, or do I need redundant sensors?
If the safety concept relies mainly on detecting faults and transitioning to a safe state, rich resolver diagnostics and fault pins may be enough. When continuous safe position or speed is required at higher integrity levels, I usually plan for redundant position channels and use resolver diagnostics as an additional safety layer.
9. Which interface mode works best with a field-oriented control MCU or motion controller?
For a single-axis FOC MCU, I often prefer a fast SPI or SSI style interface with deterministic timing and angle latching aligned to PWM interrupts. In multi-axis or FPGA-based drives, parallel or micro-parallel outputs or sin–cos pass-through paths can simplify timing closure at very high update rates.
10. How do I judge whether an AFE’s common-mode range and CMRR are strong enough for industrial noise?
I compare the AFE common-mode range with expected ground shifts along the resolver cable and check CMRR across the excitation frequency and its harmonics. If the environment includes noisy inverters, long cables or multiple grounding points, I look for data or application notes that prove robust performance under those conditions.
11. What functional safety documentation should I request when sourcing resolver-to-digital components?
For safety-related axes, I ask vendors for a safety manual, FMEDA data, diagnostic coverage figures and any certification reports that relate to the intended standard. Clear guidance on recommended safety mechanisms, test intervals and safe-state behaviour makes integration with safety PLC logic and STO functions much more straightforward.
12. What criteria tell me whether a vendor is truly motion- and industry-focused rather than general purpose?
I look for long-term availability commitments, reference designs for servo drives and robots, motor-control software libraries and experience with safety standards. Vendors that understand resolver cabling, EMC, thermal behaviour and lifecycle issues in real factories are usually better partners than those offering only generic mixed-signal components.
