Bus and Phase Voltage Sensing in Motor Drives
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This page is a working guide for designing bus and phase voltage sensing in motion drives, from dividers and ADC front-ends to over-voltage protection and IC choices. The goal is to turn DC-link and phase voltage into clean, reliable signals that support FOC/V or F control and protect the power stage under real-world operating and fault conditions.
What this page solves
This page focuses on how to sense DC-bus and phase voltages in motor drives so that the control loops, modulation and protection logic are all working from realistic voltage information instead of assumptions. The goal is to turn the “just divide it down into the ADC range” mentality into a structured design flow for dividers, buffers, filters and over-voltage comparators.
In FOC and V/f control, the measured DC-link voltage is the reference that converts a normalized modulation index into an actual phase voltage, and phase-voltage feedback is often used by sensorless observers and flux estimators. If the bus or phase voltage is mis-measured, the drive can deliver the wrong torque, drift into field-weakening too early, or fail to limit voltage during regeneration events.
At the same time, the DC-link voltage is the primary quantity used to decide when a drive is safe to start, when a pre-charge is complete and when an over-voltage condition requires the power stage to shut down or switch energy into a brake resistor. The sensing chain must therefore balance several trade-offs: divider power dissipation versus accuracy and bandwidth, RC filtering versus ADC timing and phase delay, and comparator thresholds and hysteresis versus noise and temperature drift. This page focuses only on the electrical path from the high-voltage bus and phases into the low-voltage measurement and protection domain; DC-link topology, pre-charge design and current sensing are covered by their own dedicated pages.
Where bus and phase voltage sensing sits in the drive architecture
In a typical motor drive, the DC-bus and phase voltage sensing chains sit between the high-energy power stage and the low-voltage control and safety domain. On the power side, an AC source is rectified and optionally processed by a PFC stage to build the DC link. An inverter bridge then generates the three phase outputs that feed the motor. On the control side, a FOC or motion MCU receives scaled copies of the DC-link and phase voltages on ADC inputs and, in many designs, dedicated over-voltage comparator inputs for fast hardware protection.
The DC link usually fans out into at least two distinct low-voltage paths. One path passes through a precision divider and optional buffer or filter stage into an ADC channel so that the controller can track the actual DC-bus voltage for modulation scaling, soft-start and diagnostics. A second path feeds a divider and comparator that implement over-voltage detection and generate a fault signal for the gate-driver or safety logic. If the controller sits on a separate control board, these signals may cross an isolation barrier via an isolated amplifier, a sigma-delta modulator or an isolated comparator output.
Phase-voltage sensing is attached to the inverter outputs and provides per-phase voltages to the ADC for sensorless observers, field-weakening strategies and advanced diagnostics. Some designs sense a single phase, while others sense all three phases to reconstruct the applied voltage vector more accurately. This page focuses on the highlighted measurement and comparator paths between the bus and phase nodes and the controller. DC-link topology and pre-charge schemes are treated in the DC-Link and Pre-Charge page, and phase or bus current sensing is handled in the dedicated current-sensing page.
Typical bus and phase voltage sensing topologies
Bus and phase voltage sensing in motor drives can be implemented with several recurring circuit topologies. At the DC-link level, the simplest option is a resistive divider that scales the bus voltage directly into a single-ended ADC channel referenced to the control ground. For noisy systems or complex grounding structures, the divider output is often followed by a differential amplifier or fed into a differential ADC so that common-mode disturbances and ground offsets are rejected more effectively.
When the control electronics and power stage are galvanically isolated, the DC-link sensing path typically includes an isolation element such as an isolated amplifier, a sigma delta modulator or an isolated comparator output. In these schemes, the high-voltage side handles the divider and primary filtering, and only a conditioned analog or digital representation of the bus voltage crosses the isolation barrier. The choice between direct, differential and isolated topologies is strongly tied to system voltage, safety requirements, noise levels and board partitioning.
Phase voltage sensing is usually derived from the inverter phase outputs using per-phase dividers. Some drives measure a single phase for basic monitoring, while higher performance drives sense all three phases for modulation verification, fault diagnostics and sensorless observers. The phase dividers feed dedicated ADC channels and are designed to coexist with phase current sensing without disturbing shunt or current sensor performance. Current sensing is treated in a separate phase and bus current sensing page, while this section focuses purely on voltage measurement topologies.
Precision divider design: resistors, ratings and layout
The precision divider is the core element that scales high bus or phase voltages into a safe and measurable range. Its behaviour is set by resistor tolerance, temperature coefficient, voltage coefficient and power rating, as well as the total divider current. For motor drives operating on 400 volt or 800 volt DC buses, the resistor technology, value range and series configuration must be chosen to keep absolute error and drift within acceptable limits while avoiding undue heating and stress.
The divider ratio must be matched to the ADC full scale range and to any over-voltage comparator thresholds that share the same tap point. A typical design starts from the maximum expected DC-link voltage, including regeneration and surge margins, then selects a divider ratio that maps this value into the desired ADC span with some headroom. The same ratio is used to calculate the comparator input level at the intended trip voltage, so that the chosen reference and comparator input range are both well utilised. Divider current is then adjusted to balance noise immunity and ADC drive capability against continuous power dissipation.
Physical ratings and layout are equally important. Individual resistors must not exceed their working voltage and power limits, so high bus voltages often require several series resistors, which also help with creepage distance along the divider chain. On the PCB, the high-voltage end and low-voltage end need appropriate clearance and creepage, and the divider tap should connect into a clean analog reference region away from high dv by dt switching nodes. Conformal coating, slots and careful routing can significantly improve robustness in humid or polluted industrial environments. Detailed energy measurement error budgets are covered in the current sensing and power measurement content; this section concentrates on practical divider design for control and protection purposes.
ADC front-end and filtering for motion control
The front-end between the voltage divider and the ADC input has a direct impact on how well a drive can run its current and speed loops. Bus and phase voltage channels must reject switching noise and dv/dt spikes without adding excessive delay or phase shift around the loop bandwidth. In practical designs this usually means a carefully chosen RC network combined with a buffer or dedicated ADC driver, rather than a generic low-pass filter attached to a high-impedance divider.
The sampling behaviour of the ADC also matters. A typical SAR ADC presents a sample-and-hold capacitor that must be charged through the source impedance within the configured sampling window. Divider resistance, any series RC filter and the output impedance of the buffer together determine how fast the input settles to the correct value. If the source impedance is too high or the sampling window too short, the measured bus or phase voltage will be biased towards previous samples, especially when the ADC multiplexes several channels such as phase currents and voltages.
With motion-control MCUs, the ADC acquisition instants are normally synchronised to the PWM carrier so that sampling occurs in quiet windows, for example around the mid-point of each PWM period. The front-end time constants must be fast enough that the bus and phase voltage channels have settled by the time the sampling window opens. At the same time, the RC corner frequency should be well above the current-loop bandwidth but low enough to attenuate switching edges and high-frequency components that would otherwise alias into the control band. Detailed control-loop design and sampling strategies are covered in the FOC controller and motion MCU content; this section concentrates on the electrical front-end and its interaction with ADC timing.
Over-voltage comparators and protection hooks
The over-voltage comparator path is the fast hardware branch of the bus voltage sensing chain. A scaled copy of the DC-link is compared against a reference threshold, and the comparator output feeds gate drivers, latch logic and MCU fault inputs. This path is responsible for shutting the power stage down or steering energy into braking elements before semiconductor limits are exceeded, even if software has not yet reacted. The same divider that feeds the ADC can often be reused for the comparator, but the threshold, hysteresis and transient behaviour must be engineered explicitly.
Threshold setting starts from the system voltage profile. The rated DC-link voltage, the maximum continuous allowable level and the absolute hardware limit together define a band where an over-voltage trip point makes sense. The divider ratio converts this desired trip voltage into a comparator input level that matches the available reference. Comparator offset, reference tolerance and divider drift then define the error band, and the chosen trip level must leave margin to the absolute limit even under worst-case combinations of these errors. Hysteresis around the trip point prevents the system from chattering on noise or small regeneration ripples.
The comparator output is usually wired into a protection tree together with over-current and under-voltage events. Gate drivers may integrate basic OVP comparators with fixed or programmable thresholds, while external comparators give more flexibility for multi-level schemes. In both cases, the fault signal typically drives a latch or fault manager that enforces gate-off and then informs the motion controller through a dedicated fault pin or status interface. Detailed sequencing, restart policies and interaction with over-current and under-voltage protection are handled in the dedicated OC, OV and UV protection content; this section focuses on the link from the divider to the comparator and the main protection hooks.
Design checklist and IC mapping
Design checklist for bus and phase voltage sensing
This checklist collects the main decisions needed to turn bus and phase voltage sensing from a schematic sketch into a robust implementation. Each question focuses on system limits, channel planning, ADC front-end constraints and reliability targets, so that divider design, filtering, over-voltage comparators and isolation choices stay consistent with the overall drive architecture.
- What are the nominal and maximum DC-link voltages, and how high can the bus rise during regeneration, inrush or grid disturbances?
- How many DC bus voltage channels are required, and are there secondary or local buses that also need monitoring?
- How many phase voltage channels are required: single-phase monitoring, two phases, or full three-phase sensing for diagnostics and sensorless observers?
- Are bus and phase voltages measured on the power board only, or must they cross an isolation barrier to a separate control board?
- What is the ADC full-scale range and reference choice for the voltage channels, and how much dynamic range is needed for both normal operation and over-voltage conditions?
- What divider power dissipation is acceptable per channel, and how does this interact with resistor technology, series elements and PCB creepage constraints?
- Is a dedicated hardware over-voltage comparator required for fast shutdown, or is ADC polling by the motion controller sufficient for the application?
- What update rate is required for DC bus and phase voltage channels, and how does this fit within the available ADC sampling windows alongside phase current channels?
- What voltage accuracy is required: coarse monitoring, control-grade accuracy or energy measurement grade, and how does this influence tolerance and drift limits on the divider and front-end?
- What ambient temperature range, pollution level and humidity conditions apply, and is conformal coating planned around the divider and front-end components?
- Which safety or industry standards constrain creepage distance, insulation coordination and protection behaviour for the bus voltage measurement path?
- How is the over-voltage fault expected to interact with over-current and under-voltage protection, and which protection manager or latch block coordinates these events?
IC mapping and solution tiers
The component choices for bus and phase voltage sensing can be mapped into a small set of roles and solution tiers. Divider resistors or resistor networks, op-amps or ADC drivers, comparators and any isolated amplifiers or sigma-delta modulators form the core of the measurement path. On top of this, the design can use either flexible discrete combinations, integrated AFEs and drivers with built-in monitoring, or safety-oriented devices with documentation for higher integrity applications.
- Precision dividers and resistor networks: high-voltage resistors, matched resistor arrays and thin-film options define accuracy, drift and power handling for bus and phase voltage scaling.
- Op-amps and ADC drivers: rail-to-rail input and output stages, low offset and low drift amplifiers and dedicated differential drivers are used to buffer divider nodes and drive ADC sampling capacitors.
- Comparators and window comparators: devices with suitable input common-mode range, internal references and hysteresis implement over-voltage and window detection, feeding gate drivers or protection managers.
- Isolated amplifiers and sigma-delta modulators: isolated front-ends support measurement when the control MCU and power stage are galvanically separated and must meet insulation and timing requirements.
- Solution tiers: discrete implementations, integrated AFEs or drivers with built-in monitoring, and high-reliability or safety-certified solutions cover different cost, flexibility and qualification levels.
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Bus and phase voltage sensing – FAQs
These twelve questions are the way bus and phase voltage sensing decisions are checked before a motion control design is frozen. Each answer stays compact enough for reviews and sourcing discussions, and the visible text is kept identical to the FAQ structured data so that search snippets and internal checklists stay aligned.
When is it sufficient to monitor only the DC-link bus voltage, and when is phase voltage sensing also required?
For simple drives and V or V or F control, monitoring only the DC link is usually enough to protect hardware and map modulation to available voltage. I add phase voltage sensing when sensorless FOC, detailed diagnostics or EMI optimisation are needed, or when phase reconstruction and fault analysis justify the extra channels and layout effort.
How should the DC-link divider resistor values be chosen to balance power dissipation, noise performance and ADC accuracy?
I start from the ADC full scale and target divider current. Too little current makes the node sensitive to leakage, noise and sampling charge kicks, while too much wastes power and pushes resistor ratings. I usually aim for microamp to low milliamp currents, then check thermal rise, noise bandwidth and that the source impedance suits the ADC front end.
How can power dissipation and voltage rating for divider resistors be calculated and checked in 400 V and 800 V systems?
I calculate the current at the highest credible DC link voltage, square it and multiply by each resistor value to get power. Then I compare the working voltage across each part with its datasheet rating and check creepage on the PCB. If either margin is thin, I split the chain or move to higher power or higher voltage parts.
Given an ADC input sampling time and sampling capacitor, how can the maximum practical source resistance and RC time constant be estimated?
I treat the divider, filter and buffer output as a single source resistance driving the ADC sampling capacitor. For a given sampling time, the product of source resistance and sampling capacitance must be small enough that the input settles within a fraction of an LSB. If not, I either lower resistance, add a buffer or increase the sampling window.
When should a buffer amplifier or dedicated ADC driver be added after the divider instead of feeding the ADC directly?
I add a buffer when the divider resistance must be high for power or creepage reasons, when the ADC input capacitance is large or when several channels are multiplexed quickly. A rail to rail or differential driver lets the divider run with lower current while still charging the sampling capacitor cleanly and isolating the sensing node from switching artefacts.
At what multiple of the rated DC-link voltage should the over-voltage comparator threshold typically be set?
I anchor the threshold between the maximum continuous operating voltage and the absolute hardware limit. In many industrial drives that works out around one point one to one point two times the nominal DC link, adjusted for derating, device tolerances and thermal headroom. The exact factor depends on braking capability, grid conditions and how aggressive the protection strategy needs to be.
How can regeneration-induced DC-link voltage spikes be handled so that the OVP comparator does not trigger on short transients?
I handle regeneration spikes with a combination of threshold margin, hysteresis, small input filtering and sometimes blanking around known events. A braking chopper or load must be sized so the DC link does not linger near the limit. The comparator path then filters very narrow spikes while still reacting quickly to sustained or repeated over-voltage conditions.
In multi-axis drive systems, should each inverter measure its own bus voltage or can a shared DC-link sensing channel be used?
If several inverters share a stiff common DC link, a single well designed bus voltage channel is often enough for protection and modulation. I add per axis sensing when cable drops, local bus capacitors or protection policies differ, or when diagnostics must pinpoint which inverter bay is experiencing over-voltage or supply quality issues.
What techniques help phase voltage sensing stay robust in high dv/dt environments with fast switching edges and common-mode noise?
I keep phase sensing robust by referencing dividers carefully, using short and symmetric routing, adding modest RC filtering and, when needed, differential or isolated front-ends. Sampling is aligned to calmer parts of the PWM period and the layout keeps measurement nodes away from gate drive loops, snubbers and high dv or dt copper pours.
How should PCB layout around the divider and front-end be planned to meet creepage and clearance requirements while keeping errors under control?
On the PCB I reserve a clear high voltage corridor for the divider chain with suitable creepage, avoid leakage paths and keep the low voltage tap short and guarded. I group precision resistors and front-end parts away from hot components, use solid reference planes where allowed and apply coating or slots where pollution or humidity are concerns.
When the motion-control MCU is galvanically isolated from the power stage, how should bus and phase voltage information cross the isolation barrier?
I decide early whether voltage information crosses isolation as analogue, sigma delta or already digitised data. Isolated amplifiers or modulators keep an analogue feeling interface, while smart drivers and AFEs can present voltage flags or measurements digitally. The choice depends on required accuracy, bandwidth, isolation rating, pin budget and how much the control side can offload filtering and scaling.
When does it make sense to use gate drivers or AFEs with integrated bus monitoring and OVP instead of an external divider plus comparator?
Integrated bus monitoring in gate drivers or AFEs is attractive when layout simplicity, time to market and reference designs matter more than fine grained control of thresholds. I lean on those devices in standard voltage ranges and volume platforms, and stay with external dividers plus comparators when unusual limits, multi level thresholds or special standards must be met.
