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OV/OC/SCP protection decides whether a power supply sacrifices MOSFETs, rectifiers and transformers during a fault, or shuts down gracefully and recovers without damage. Many controllers expose only a basic current limit and thermal shutdown, which react too slowly or too softly to hard shorts, mis-wiring and feedback failures.

This page focuses on the missing piece between “simple current limit” and real protection: fast comparators observing the right nodes, well-chosen voltage and current thresholds, and time strategies such as blanking, time-over-threshold, hiccup and latch-off. Together they turn raw fault energy into controlled, repeatable behavior instead of random meltdown.

Without independent OV/OC/SCP protection, typical failure scenarios include:

• A shorted or miswired output pulls huge current until primary MOSFETs, rectifiers or current-sense resistors fail, because the internal limit responds after significant energy has already been dumped.
• A broken feedback path or wrong reference value drives the loop to maximum duty cycle, forcing the output far above nominal with no independent over-voltage guardrail.
• A failed current-sense network hides real peak current from the controller, so built-in cycle-by-cycle limits and thermal shutdown never see the danger in time.

The scope of this page is intentionally narrow to avoid overlap with sibling topics. The focus is on:

• Comparator-based detection of over-voltage, over-current and short-circuit conditions.
• Definition of voltage thresholds such as OVhi, OVlo and UVLO, and current thresholds such as ILIMfast and ILIMslow.
• Time behavior around those thresholds: blanking, filtering, time-over-threshold, hiccup and latch-off strategies.

Topics such as MOSFET safe operating area, hot-plug inrush and ideal diode OR-ing belong to the dedicated eFuse & hot-swap section. Precision current and voltage measurement techniques are covered under current/voltage sensing, and thermal derating and fan control are treated in the thermal & fan control section. This separation keeps each page focused while still allowing a complete protection chain when all blocks are combined.

Fault map & protection thresholds

A structured fault map links real-world events to measurable quantities and then to clear thresholds. Instead of treating “it sometimes blows up” as a mystery, the power path is decomposed into output symptoms, internal electrical symptoms and root causes. Protection thresholds then sit at key nodes to detect when a value leaves a safe window.

Typical fault families in OV/OC/SCP design include:

• Output over-voltage (OV) from loop runaway, feedback breaks or incorrect reference values.
• Output over-current or short-circuit (OC/SCP) from hard shorts, miswired loads or down-stream component failures.
• Primary protection blind spots when peak current limit or the sense path fails, causing internal protection to see nothing while real current rises dangerously.

Each fault type is mapped onto specific thresholds: output voltage windows with OVhi and OVlo values, UV/UVLO points that mark undervoltage, and current limits split into fast short-circuit response (ILIMfast) and slower continuous overload protection (ILIMslow).

Output OV from loop runaway and feedback errors

When the feedback signal collapses or is scaled incorrectly, the controller believes the output is too low and drives maximum duty cycle. The actual output then climbs until something else limits it: the transformer insulation, rectifier voltage ratings, output capacitors or the load itself. An independent over-voltage comparator watching the scaled output is the last line of defence in this situation.

The fault map places a threshold OVhi slightly above the nominal regulation range. As long as the feedback loop keeps Vout within its target window, the comparator output remains inactive. When Vout drifts past OVhi, a dedicated path can shut the converter down, regardless of what the main control IC thinks. For tighter applications, a lower OVhi limit forces the design to treat even modest over-voltage as a fault instead of “close enough.”

Output OC and SCP from shorts and overloads

Down-stream faults such as hard shorts, damaged cables or failed modules appear as an abrupt rise in output current and a collapse of output voltage. If only the slow, averaged current limit in the controller reacts, the silicon and magnetics experience a large current spike on each cycle before the loop reduces drive.

The fault map therefore introduces two current thresholds. ILIMfast sits high enough to ignore benign peaks but low enough to protect power devices during a true short. It feeds a fast comparator that can shut the switch off in a few cycles and hand control to a hiccup or latch-off mechanism. ILIMslow sits closer to the rated current and defines how much sustained overload the supply will tolerate before reducing output or shutting down.

Sense failures and primary blind spots

When the current sense resistor opens, the controller sees almost no sense voltage, so internal peak current limit never triggers. When the sense path shorts, the effective resistance is lower than expected and the real peak current at the designed threshold is much higher than intended. In both cases the built-in protection logic is blind while the converter operates closer to device limits.

A robust fault map therefore includes voltage windows on key nodes such as the PFC or bulk rail, and possibly secondary-side windows on regulated outputs. If sensed currents and voltages no longer agree with the expected operating envelope, window comparators around UV/UVLO, OVlo and OVhi force the supply into a safe state, even when primary current sensing is compromised.

Comparator architectures for OV/OC/SCP

OV/OC/SCP protection depends not only on where thresholds are placed, but also on how the comparators behave in real switching conditions. Different comparator architectures trade off speed, input range, noise immunity and ease of integration into the power supply fault tree. Selecting an unsuitable structure can leave the design blind to fast faults or vulnerable to nuisance trips.

Simple rail-to-rail comparators are widely used to implement independent over-voltage and over-current thresholds. They are attractive through low cost and flexible supply ranges, but propagation delay, input common-mode limits and output topology all influence whether a particular device is robust enough for primary-side short-circuit protection or only suitable for slower window checks on secondary rails.

Multi-channel comparators with built-in references and OR-ing or window logic provide a more integrated approach. Several rails share a common reference and each channel monitors a specific over- or under-threshold condition. Internal OR-ing combines faults into a single FAULT pin, simplifying wiring of complex supplies with multiple outputs. Window modes allow a channel to assert one output when a quantity is above its window and another when it is below, which is useful to distinguish undervoltage and over-voltage on a given rail.

Protection-grade comparators extend these ideas by adding blanking, filtering and hysteresis tailored for switching environments. Blanking masks the input during known noisy intervals, such as immediately after a MOSFET turns on, so that short spikes do not trip protection. Internal filtering or time-over-threshold logic requires the input to exceed the threshold for a defined duration before a fault is generated. Built-in hysteresis prevents oscillation around the trip point and ensures a clean, single transition during brown-out or recovery.

Input common-mode range determines whether the comparator can correctly observe the chosen sense node across the full operating envelope. For low-side current shunts, the input must remain accurate close to ground, while for high-side shunts or heavily attenuated output voltages, the input can sit near the supply rails. If the common-mode range does not include the actual signal levels, protection may fail silently or respond unpredictably near the boundaries.

Output type also shapes how comparators integrate into the PSU. Open-drain outputs are well suited to wired-OR FAULT buses that combine multiple OV/OC/SCP sources and can be level shifted to the logic domain of a PWM controller or digital PSU manager. Push-pull outputs provide fast edges and can directly drive enable or reset pins, but are less convenient for sharing a line across multiple devices. In all cases, the comparator input is ultimately driven by a front-end sampling circuit: shunts or current transformers for current, and resistor dividers and clamps for voltage. The detailed design of those sensing front-ends, including bandwidth, isolation and accuracy, is handled in the dedicated current/voltage sensing topic, while this section focuses on the comparator behavior itself.

Programmable limits & references

OV/OC/SCP thresholds translate the desired protection policy into real voltage and current trip points in silicon. The simplest limits are formed by fixed resistor dividers against a reference, but manufacturing spreads, temperature drift and reference accuracy all affect the effective margin. More advanced schemes use trim pins, OTP-selected ranges or on-chip DACs controlled through I²C or PMBus to tighten production distributions or to enable field-tunable protection.

Fixed resistor dividers remain the default choice for many offline adapters and LED drivers. A stable reference, a pair of resistors and a comparator input produce a repeatable threshold with minimal complexity. The trade-off is that all tolerances add up: reference initial accuracy, divider resistor tolerances, comparator input offset and PCB leakage. To avoid false trips, the nominal OV or OC threshold often needs to be placed slightly further from the normal operating point than would be ideal on paper.

Adding a trim pin or using OTP-selectable thresholds allows a production line to nudge protection points after characterising real hardware. A trim scheme might offer several discrete steps around the target OV or OCP level, selected by burning fuses or wiring option resistors. This approach preserves a simple external network, but reduces spread by aligning the threshold of each design or variant to measured behaviour instead of relying entirely on worst-case calculations.

Controllers and supervisors with internal DACs and digital registers go further by letting firmware or a digital power manager program the limits in the field. OV, UV, OC and SCP thresholds can be adapted to different operating modes, derating profiles or firmware updates, and can be profiled in manufacturing using automatic test equipment. The default power-on values still need to be safe enough before any configuration traffic arrives, but once the system is up, the protection policy can follow system-level constraints rather than being frozen at design time.

All of these schemes depend on reference and bias quality. If the reference voltage shifts with temperature, supply ripple or ageing, the effective trip points also drift and protection can become either too permissive or too aggressive. Low-drift references, suitable line and load regulation on bias rails and adequate PSRR are therefore essential building blocks. In addition, power-good signalling or internal reference ready flags are needed so that comparators do not act on partially settled references during startup.

This section focuses on how thresholds are implemented and adjusted around OV/OC/SCP comparators. Detailed selection of reference topologies, bias LDO structures and how these rails support the rest of the system, including precision measurement channels, is handled in the dedicated references & bias topic. Keeping these aspects modular avoids duplication while enforcing consistent error and drift assumptions across the entire power supply platform.

Blanking, debounce & time-over-threshold

OV/OC/SCP comparators work around fixed thresholds, but switching noise and inrush currents can cross those limits without representing real faults. If every threshold crossing immediately triggered shutdown, normal turn-on spikes, transformer leakage ringing and benign inrush events would cause unstable behavior. Blanking, debounce and time-over-threshold techniques add a time dimension to the decision so that fast spikes are ignored and only persistent violations become protection events.

Leading-edge blanking (LEB) masks the current-sense signal during the first tens or hundreds of nanoseconds after a switch turns on. In this interval, parasitic inductances and capacitances generate sharp peaks that can exceed over-current thresholds even though semiconductor and magnetics stress remain within their safe area. By suppressing the comparator output during this window, LEB prevents these artifacts from falsely tripping cycle-by-cycle current limit or short-circuit protection, while still allowing the comparator to respond during the rest of the on-time.

RC filters in front of comparators provide a slower, analog form of debounce. A small series resistor and capacitor to ground smooth the sensed waveform so that very narrow spikes are averaged away before reaching the comparator input. This approach works well for over-voltage and under-voltage detection, where true changes are inherently slower than switching edges, and for moderate-speed over-current checks on secondary rails. However, a large RC time constant also delays the response to genuine faults and can reduce the apparent peak, so fast short-circuit detection on primary switches still relies more on LEB and well-controlled layout than on heavy filtering.

Digital time-over-threshold (ToT) counters add a further layer of selectivity by considering how long a threshold is exceeded rather than only whether it is crossed. A ToT scheme may require several consecutive switching cycles above ILIM, or a total exceed time above a certain duration, before classifying the condition as a fault. Short bursts due to inrush or transient load steps fall below this integration window, while sustained overloads accumulate enough ToT to trip protection. This lets designers align protection behavior with energy and thermal limits instead of reacting to instantaneous peaks alone.

In practice, robust OV/OC/SCP designs combine all three mechanisms. Leading-edge blanking handles the nanosecond-level artifacts at switch edges, modest RC filtering cleans up residual ringing and high-frequency noise, and time-over-threshold logic distinguishes short, acceptable inrush currents from sustained overloads or hard shorts. The result is a protection system that maintains immunity to nuisance trips without giving up fast response when a real fault injects dangerous energy into the power stage.

Hiccup, latch-off & auto-restart strategies

Once OV/OC/SCP comparators and time filtering have classified a condition as a true fault, the power supply must decide what to do next. The protection action determines device stress, user experience and compliance with safety expectations. Common strategies include hiccup, where the converter shuts down, waits and periodically retries; latch-off, where it remains off until a manual or system reset; and auto-restart with limited duty, where the supply continues to operate in a constrained mode while monitoring the fault.

Hiccup mode is widely used in adapters and chargers. When a short-circuit or severe over-current is detected, the controller turns off the power stage and starts an off-timer. After the timer expires, a fresh soft-start sequence attempts to bring the output up again. If the fault persists, the cycle repeats. This pattern drastically reduces average fault power and semiconductor heating compared with continuous current limit, and helps meet safety requirements for maximum fault energy. It also gives benign, short-lived faults an opportunity to clear without requiring the user to unplug the supply.

Latch-off strategies are preferred where automatic restart could be unsafe or confusing. When a defined fatal condition occurs, such as output over-voltage beyond a narrow margin, insulation fault indications or repeated failed restart attempts, the converter is shut down and held off. Recovery requires cycling the input supply or issuing a dedicated reset command from a system controller. This behavior makes the fault clearly visible to maintenance staff or supervisory software and prevents a PSU from repeatedly energizing a circuit that may pose a shock, fire or equipment damage risk.

Auto-restart with limited duty offers a middle ground for intermittent or soft faults. Instead of fully shutting down, the PSU clamps duty cycle, output voltage or current to a lower level and continues to supply essential rails while monitoring for improvement or worsening of the condition. This can suit loads that draw high current during startup and then settle, or systems where maintaining partial power is better than a full outage. The protection must still guarantee that device ratings and safety limits are met even under continuous limited-duty operation.

Timing capacitors, digital counters and soft-start circuits are used together to implement these behaviors. A timing capacitor can define both the duration of a soft-start ramp and the off-time of a hiccup cycle, depending on how it is charged and discharged in each state. Digital state machines can count how many restart attempts have failed and upgrade the response from hiccup to latch-off after a programmable number of cycles. In all cases, every restart must reapply soft-start to avoid another surge of inrush and a new round of false OC events as soon as the converter resumes switching.

Typical mappings emerge across applications. Compact offline adapters and USB-C chargers usually pair time-over-threshold detection with hiccup restart for short-circuit faults, while reserving latch-off for severe output over-voltage conditions. Industrial and medical PSUs more often require latch-off for critical protections so that operators must explicitly acknowledge faults, though hiccup can still be used for non-critical overloads. Server and digital PSUs frequently express these strategies as configurable PMBus parameters, combining local hardware actions with system-level fault logging and coordinated recovery policies.

Coordination with PWM / digital controllers

OV/OC/SCP blocks rarely act in isolation. Once a comparator and time-filtered fault decision have been made, the protection signal must interact cleanly with the main PWM or digital controller. The goal is to guarantee that MOSFETs turn off quickly enough to stay within their safe operating area, while the system-level controller still understands what happened and can apply appropriate restart or derating policies.

On analog-controlled supplies, secondary-side comparators often drive optocouplers into primary-side EN, SD or COMP pins. Pulling EN or a dedicated shutdown pin low forces the PWM controller into an off state, independent of the error amplifier. Pulling COMP low reduces duty cycle and can implement a controlled foldback or current-limit shape instead of an abrupt stop. These paths bypass firmware and provide a direct, hardware-determined shutdown route when over-current or over-voltage conditions are present.

Digital power stages use FAULT and GPIO lines in a similar way. Protection comparators or multi-channel supervisor ICs expose open-drain FAULT outputs that fan into both the gate-driver enable pins and a digital controller interrupt input. Hardware gating ensures that PWM outputs are immediately disabled when a severe fault occurs, regardless of software state, while the digital controller records the event, categorises it and decides whether to attempt restart, enter latch-off or transition into a limited-power mode based on configured policies.

Many designs include both a primary current limit inside the PWM controller and separate secondary-side OC comparators. The internal primary current limit protects the switch and magnetics on a cycle-by-cycle basis and must always be present as the fastest layer of defence. Secondary OC comparators observe load behaviour and rail-specific constraints; they decide whether a sustained overload represents a short-circuit, a miswired cable or an abnormal load mode and then request a shutdown or hiccup sequence from the main controller. Primary protection therefore guards device physics, while secondary protection and digital logic set the behaviour seen by the rest of the system and by users.

In digitally managed PSUs, the controller can also timestamp faults, track how many times each type has occurred and limit the number of automatic restarts. Once a threshold is exceeded, the policy may escalate from hiccup to a latched shutdown that requires remote or manual intervention. Telemetry, PMBus fault logs and coordinated multi-rail responses belong to the broader digital power-management layer, which is covered in the dedicated Digital PSU Controller (PMBus) topic. The OV/OC/SCP block described here focuses on delivering timely, unambiguous fault signals into that control framework.

Design checklist & IC role mapping

OV/OC/SCP design checklist

• Distinguish clearly between fast short-circuit protection and average over-current protection. Fast OC/SCP should be tied to primary current sense and device SOA, while average OC limits should align with thermal constraints and copper loss.
• Define thresholds for all relevant modes: constant-voltage rails, constant-current stages, battery-charging profiles, LED drivers and motor loads. Check that inrush and startup surges are not misclassified as permanent faults.
• Include margin for reference accuracy, resistor tolerances, comparator offset and layout leakage when placing OV/OC thresholds. Verify that sense signals always stay within comparator common-mode range.
• Use blanking, RC filtering and time-over-threshold logic to suppress switching spikes and short transients. Confirm that ToT settings and hiccup off-times still allow legitimate transient loads to operate without nuisance trips.
• Evaluate the impact of protection action on control-loop stability and audible noise. Rapid toggling between limit and normal mode or repeated soft-starts can create low-frequency ripple and acoustic artefacts if not properly damped.
• Size hiccup and auto-restart timing so that device junction temperatures remain within limits under worst-case faults. Check that energy delivery during fault conditions complies with relevant safety and equipment standards.
• Define which faults are allowed to auto-restart and which must latch-off until mains or a control input is cycled. Map each protection channel (OV, OC, SCP, OTP, insulation faults) to a clear recovery policy.
• For digitally managed PSUs, specify maximum restart counts and escalation rules: for example, after N unsuccessful hiccup attempts, the supply enters a latched fault state and waits for a remote reset.
• Plan a test matrix covering different load types, input voltages and temperatures. Include cold-start at minimum line, hot-start at maximum line, long cable runs, capacitive loads and deliberate short circuits on each output.
• Document the protection behaviour in timing diagrams and state charts so that system integrators know how the PSU reacts during faults and how quickly it can recover in each scenario.

IC role mapping and example devices

The OV/OC/SCP function can be partitioned across several IC types. The following roles illustrate how common devices are used in real designs, together with representative part numbers for deeper investigation.

Fast single- / multi-channel protection comparators

High-speed comparators provide the first line of defence for OC and SCP thresholds. Useful traits include rail-to-rail inputs, low input offset, nanosecond to low-microsecond propagation delay and open-drain outputs for wired-OR fault buses.

• Micropower dual comparator families such as TLV6700/TLV6702 for window OV/UV detection on DC rails.
• High-speed comparators such as LMV7235 or LT1713 for fast short-circuit detection on primary or secondary sense nodes.
• Quad low-voltage comparators such as LM339A or TLV1704 to supervise multiple outputs and combine faults into a single FAULT line.

Programmable protection and supervisor ICs

Dedicated protection and supervisor devices integrate precision references, multiple comparators, OR-ing logic and sometimes trim pins or digital configuration. They centralise monitoring of several rails and generate unified fault signals.

• Over-voltage / under-voltage supervisors such as TPS3702 or LTC2965 for wide-input OVP/UVP with accurate thresholds and open-drain outputs.
• Current-limit monitors such as INA300 or MAX9643 for threshold-based OC detection with adjustable sense limits and fast indication outputs.
• Multi-rail supervisors such as LTC2919 or MAX16054 that watch several supply rails and present a consolidated reset/FAULT signal.

PWM controllers with integrated OV/OC/SCP

Many offline PWM controllers already include primary current limit, VCC over-voltage protection, feedback-pin short-circuit detection and built-in hiccup logic. External comparators then extend protection to secondary rails and system-level conditions.

• Flyback controllers such as UC3845A, NCP1207 or UCC28740 with cycle-by-cycle current limit and overload protection tied to feedback or CS pins.
• LLC and PFC controllers such as UCC256403 or L6563H combining line sensing, OVP and OCP mechanisms inside the control IC.
• Integrated primary controllers for adapters, for example TEA1755 or ICE3BR4765J, which embed soft-start, SCP hiccup and brown-in/brown-out logic.

Digital power controllers and monitors with event logs

Digital power controllers supervise multiple rails using ADCs and comparators, generate DAC-set limits and expose PMBus or similar interfaces for configuration and telemetry. They implement higher-level fault handling, logging and coordinated restart policies.

• Digital power controllers such as UCD3138 or NCP81233 for PFC + DC-DC stages with programmable protection and PMBus control.
• Multi-rail digital power managers such as LTC2977 or MAX16046 that sequence, monitor and log faults across several POL converters.
• Isolated digital gate drivers and monitors such as ADuM4135 or Si823x that combine fault detection, desaturation protection and fault reporting for high-side switches.

These device classes work together to implement a complete OV/OC/SCP scheme: fast analog comparators catch the physics of short circuits, supervisor ICs centralise thresholds and fault outputs, PWM controllers provide core current limiting, and digital power managers orchestrate logging and recovery. The exact mix depends on power level, application domain and how much telemetry and configurability the system requires.

Application mini-stories: OV/OC/SCP in real designs

The previous sections describe OV/OC/SCP building blocks in isolation. This section ties those blocks together in three concrete application stories—a 65 W USB-C adapter, a server PSU with multiple 12 V rails and a constant-current LED driver—to show how thresholds, comparators, time filtering and fault coordination map to real failures and user-visible behaviour.

Mini-story 1 · 65 W USB-C adapter with secondary OC and hiccup

A 65 W USB-C adapter typically uses an AC front-end, an isolated flyback or LLC stage and a secondary-side USB-C PD controller that manages VBUS negotiation. On the primary side, the PWM controller already includes cycle-by-cycle current limit tied to the current-sense pin to protect the main MOSFET and transformer. On the secondary side, an additional shunt and over-current (OC) comparator are added on the VBUS path to supervise the USB-C output and implement short-circuit protection closer to the connector.

When a user drags a live USB-C plug across a metallic surface or connects a device with an internal short, the VBUS pin can be hard shorted. Current rises well above the 3.25 A nominal level and quickly crosses the secondary fast OC threshold, which is set using a shunt and comparator at around 5–6 A. A small RC filter removes very narrow spikes from cable inductance, while time-over-threshold logic requires several consecutive switching cycles above the OC threshold before declaring a true fault. This avoids nuisance trips during normal plug-in transients or negotiation bursts.

Once the ToT window is exceeded, the secondary OC comparator asserts a FAULT signal. One branch of this FAULT turns off the VBUS MOSFET driving the USB-C connector. Another branch crosses the isolation barrier and pulls down the primary EN or dedicated shutdown pin of the PWM controller. The controller then enters a hiccup mode defined in the OV/OC/SCP strategy: the power stage is fully disabled for a programmed off-time, such as 50–100 ms, and then a fresh soft-start ramp is attempted. If the short remains, the fault is re-detected and the hiccup cycle repeats.

From the user perspective, a hard short at the connector does not generate smoke or continuous clicking; the adapter simply stops delivering power and periodically tries to recover. After the problematic cable or device is removed, the next hiccup restart succeeds, VBUS returns to the negotiated voltage and the USB-C PD controller resumes normal operation without requiring the mains to be unplugged. Internally, the primary MOSFET sees only short bursts of current separated by long off-times, keeping junction temperature and transformer stress within safe limits even under extended short-circuit conditions.

System partitioning note: AC inrush, X-cap discharge and input-side eFuse or NTC control are handled in the AC Front-End & PFC and eFuse & Hot-Swap topics. This mini-story focuses specifically on secondary OC detection and hiccup coordination around the USB-C output.

Mini-story 2 · Server PSU with multi-rail 12 V OC and latch-off

A server or CRPS PSU delivers a high-power 12 V bus that is further distributed to CPU VRs, GPU boards, storage backplanes and fans. To prevent a fault in one branch from collapsing the entire system, each critical 12 V rail often employs its own shunt, OC comparator and hot-swap or eFuse FET. The main PSU controller still enforces global primary current limits and input protections, but branch-level OV/OC/SCP decisions are delegated to these local protection channels.

Consider a storage backplane slot where a new card is inserted. Due to contamination on a connector or a failed capacitor on the card, that slot presents an effective short across its 12 V supply. As soon as the slot is powered, current through its shunt rises above the configured OC threshold for that rail. The local comparator, tuned with only a small amount of filtering and a very short time-over-threshold window, asserts its FAULT output almost immediately. This FAULT signal drives the gate of the slot’s hot-swap FET low, isolating the faulty card from the main 12 V bus, and also feeds a digital PSU controller as a discrete fault input.

Instead of hiccuping that rail, the hot-swap device is configured for latch-off behaviour. Once the FAULT is set, the FET remains off and that slot stays unpowered until a deliberate reset command is issued from the management controller or the PSU is cycled. The digital PSU controller timestamps the event, records the rail identifier and OC type in its fault log and exposes the status over PMBus to the system BMC. The rest of the 12 V rails and the main bus remain in regulation, so the server continues to operate with reduced functionality rather than suffering a complete power loss.

From a data-center perspective, this behaviour is preferable to repeated automatic retries. The faulty card cannot draw more energy after the initial event, which protects PCB copper, connectors and downstream components. Operators see a clear indication such as “slot over-current, power latched off” in the management interface and can schedule maintenance or replacement without risking further damage. Analog comparators and eFuses perform the fast disconnection, while the digital controller handles fault visibility, event logging and controlled re-enablement when the slot is safe to use again.

System partitioning note: detailed eFuse SOA profiles, dV/dt control and hot-plug waveform shaping are covered in the eFuse & Hot-Swap topic, and high-level PMBus sequencing and redundant PSU management in the Form Factors & Systems – Server PSU and Digital PSU Controller topics.

Mini-story 3 · LED driver output OV shutdown for open-string protection

A constant-current LED driver regulates current through a series string of LEDs. The control loop compares the sensed LED current against a reference and adjusts the duty cycle or switching frequency to maintain the target current. Under normal conditions, the output voltage settles at the sum of LED forward voltages plus wiring drops, with some margin. However, if the LED string opens due to a loose connector, broken solder joint or failed LED package, the driver continues to increase output voltage in an attempt to force current through an effectively open circuit.

Without explicit over-voltage protection, the output can climb close to the maximum rating of the transformer, rectifier and output capacitors. To prevent this, the LED driver design adds an output OVP comparator fed from a resistive divider on the LED terminals. The OVP threshold is chosen slightly above the maximum expected LED string voltage across the full dimming range, temperature drift and component tolerances. A small RC network filters fast spikes from long cable harnesses or ESD events so that only sustained over-voltage conditions trigger the comparator.

When the LED string opens and the control loop drives the output beyond the OVP threshold, the comparator asserts its FAULT. Depending on the driver IC, this either pulls down the feedback or COMP pin to collapse the duty cycle, or directly trips a dedicated OVP input that moves the controller into a shut-down state. Many offline LED controllers latch off on OVP, requiring mains cycling or a control input toggle to restart. Others implement an OVP hiccup scheme, periodically attempting a soft-start to check whether a replacement LED string has been connected.

The end-user sees a luminaire that simply turns off when the LED string opens rather than one that flickers or produces a burnt smell. The OVP scheme prevents overstress of output capacitors, connectors and cable insulation by clamping the maximum voltage the driver can generate in fault conditions. At the same time, careful choice of the OVP threshold avoids false trips during normal dimming, LED forward-voltage variation and temperature changes. This mini-story highlights how an apparently simple output OV comparator, when combined with appropriate thresholds and latch or restart behaviour, becomes an essential safety boundary in constant-current drivers.

System partitioning note: dimming modes, flicker performance, PFC compliance and EMI aspects of LED drivers are addressed in their respective application topics. This example focuses strictly on output OV protection as part of the OV/OC/SCP layer.

OV/OC/SCP protection – FAQs