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Software-Defined Radio (SDR): Transceiver, ADC/DAC, FPGA

Software-Defined Radio (SDR): Transceiver, ADC/DAC, FPGA

← Back to: Avionics & Mission Systems

A practical avionics SDR is a repeatable radio platform: it pushes the analog-to-digital boundary closer to the antenna, then controls spurs, jitter, calibration, and deterministic latency so EVM/ACLR stay stable across modes and temperature. The core engineering work is not “a better ADC,” but a closed loop of clocking + data-plane + calibration + validation that proves the radio is healthy and debuggable.

H2-1 · What this SDR page covers (and what it does NOT)

This page is a platform-level SDR hardware guide for avionics and mission systems: it explains the end-to-end signal chain (antenna → bits) and the data plane that makes wideband reconfiguration practical. The focus stays strictly on RF transceiver + high-speed ADC/DAC + clocking + JESD/SerDes + FPGA DFE + calibration + validation.

Solves architecture boundary decisions Solves spec-to-metric mapping (SFDR/ENOB → EVM/ACLR) Solves bring-up & validation flow (clock/data/RF isolation)
  • Architecture: where the analog-to-digital boundary sits (superhet / zero-IF / direct sampling) and what it costs (bandwidth, power, spurs, dynamic range).
  • Data plane: converter interfaces (e.g., JESD204B/C), lane rate planning, clock domain crossing, buffering, and practical deterministic latency boundaries inside the SDR chain.
  • Clocking: phase noise and sampling jitter budgets, how they cap SNR/EVM, and how to diagnose clock-limited performance with repeatable tests.
  • Calibration: IQ imbalance, DC offset, LO leakage loops that turn “works on the bench” into stable spectrum/EVM across tuning and temperature.
Not covered here (only referenced as dedicated pages): waveform/protocol implementations such as SATCOM terminals, Link-16 or IFF/SSR specifics; radar/EW receiver chains as a separate discipline; aircraft power front-end standards and system timing networks. Those topics should remain on their own pages to avoid cross-over.
Search intents covered by this chapter: “what is SDR hardware architecture”, “SDR vs radio transceiver vs modem FPGA”.
Figure F1 — SDR platform boundary map (what is inside this page)
SDR platform scope: antenna → bits (hardware + data plane) RF Input Antenna RF Front-End Filter / switch (generic) Signal RF → I/Q I/Q → samples SDR Core Platform RF Transceiver mix / gain / I-Q High-speed ADC/DAC wideband sampling Clocking phase noise / jitter JESD / SerDes lanes / latency FPGA Digital Front-End DDC / DUC • NCO • filters • rate planning calibration hooks • loopback tests Host / Bits Processor control + data Bits / Streams IQ, channels, packets Metrics EVM • ACLR • SFDR NOT about (separate dedicated pages): SATCOM Link-16 IFF Radar EW Timing net

H2-2 · Definition: SDR in one extractable answer block

Definition (extractable): A software-defined radio (SDR) is a reconfigurable RF platform where the analog-to-digital boundary is pushed close to the antenna. Wideband RF transceivers plus high-speed ADC/DAC, low-jitter clocks, and programmable DFE/FPGA create a signal chain that can adapt bandwidth, tuning, and modulation in software while maintaining deterministic latency.

Step 1 RF capture Step 2 I/Q translation Step 3 wideband sampling Step 4 DDC/DUC + rate change Step 5 transport & metrics
  • Boundary closer to the antenna increases flexibility and instantaneous bandwidth, but tightens the requirements on clock phase noise/jitter, data-plane throughput, and spurious control.
  • Converter and clock quality set hard floors for EVM/ACLR and the usable dynamic range; “better DSP” cannot recover performance that is lost to jitter-limited sampling.
  • Deterministic latency inside the SDR chain depends on interface and buffering discipline (lane alignment, elastic buffers, and stable rate planning), not on waveform software.
  • Calibration loops (IQ/DC/LO) are part of the platform definition—without them, wideband tuning looks unstable even when hardware is healthy.
Search intents covered by this chapter: “software defined radio meaning”, “SDR analog vs digital partition”.
Figure F2 — Analog-to-digital boundary “slider” (3 common partitions)
Where the analog-to-digital boundary sits defines the platform trade-offs A) Superhet + IF B) Zero-IF / Low-IF C) Direct RF Sampling RF Front-End Mixer + LO IF Filter / VGA ADC (narrow IF) DSP / FPGA Typical trade-offs Lower data load • More analog complexity RF Front-End I/Q Mixer + LO Baseband LPF ADC/DAC (I/Q) DFE / FPGA Typical trade-offs Good bandwidth • Needs IQ/DC/LO calibration RF Front-End High-speed ADC DDC / Channelize FPGA Data Plane Tx: DAC + DUC Typical trade-offs Max bandwidth • Hard clock/data/spur demands

H2-3 · End-to-end architecture: RFIC + converters + FPGA data plane

An SDR platform becomes “real hardware” when the full path from RF → samples → bits is defined as a disciplined data plane: RF transceiver functions shape I/Q, high-speed ADC/DAC convert bandwidth into throughput, and the FPGA front-end (DDC/DUC) turns that throughput into deterministic, testable streams. This chapter defines the minimum complete architecture and the interfaces that must align.

Rx path RF → I/Q → ADC → JESD → FPGA DDC Tx path FPGA DUC → JESD → DAC → RF out Critical clocks + sync lines + lane mapping
  • Receiver chain (platform level): front-end (generic) → LNA/VGA → mixer/IQ → baseband/IF filtering → high-speed ADC → JESD lanes → FPGA DDC/channelize → bits/streams.
  • Transmitter chain (platform level): bits/streams → FPGA DUC/filter → JESD lanes → high-speed DAC → reconstruction filtering → upconversion/mixer → RF output (power stage not expanded here).
  • Data plane responsibility: throughput, lane alignment, buffering, rate planning, clock-domain crossings, and repeatable loopback tests.
Interfaces that must align (common failure symptom → likely layer):
• “JESD link is up but samples are wrong” → lane mapping / sync reference / alignment boundary
• “Spectrum looks unstable across tuning” → LO / clock / calibration hooks (IQ/DC/LO)
• “EVM caps early” → clock phase noise/jitter or converter dynamic-range ceiling (not a DSP issue)

Bring-up MVP (fast isolation path): clock present → JESD link integrity → digital loopback → DAC→ADC analog loopback (single tone) → modulation metrics (EVM/ACLR).

Figure F3 — Antenna-to-bits architecture with key interfaces (RF, I/Q, JESD, sync)
End-to-end SDR architecture: signal path + interfaces that must align RF domain Antenna / RF in Front-end (generic) filter • switch LNA / VGA noise • gain RF Transceiver mix • I/Q • AGC Sampling domain I/Q High-speed ADC Rx samples SFDR • ENOB • bandwidth High-speed DAC Tx samples recon filter • spurs Clocking phase noise jitter budget Sync SYSREF TRIG Digital domain FPGA DFE DDC / DUC • NCO filters • rate change Buffers & Alignment lane mapping deterministic boundary Host / Bits streams • metrics EVM • ACLR • SFDR JESD lanes JESD lanes Control & telemetry (generic)

Search intents covered by this chapter: “SDR RFIC ADC DAC FPGA architecture”, “JESD204 SDR reference design”.

H2-4 · Frequency plan & spurs: where unwanted tones come from

Spur control starts at the plan stage. An SDR has multiple “frequency engines” (LO/PLL, sampling clock, digital NCOs, and lane clocks), so unwanted tones can originate from LO/PLL behavior, sampling/aliasing, clock harmonics, or coupling paths. A good plan uses guard bands and a fingerprint method to identify which engine is responsible.

LO-related PLL / divider / reference Fs-related clock harmonics / folding Alias/Image Nyquist-zone effects Coupling digital activity / power paths
  • Reserve guard bands: avoid placing critical channels exactly where expected LO/Fs harmonics or known folding boundaries land; leave tuning room for “spur dodge”.
  • Pick the Nyquist zone deliberately: decide whether the desired band is captured directly or via sampling translation; folding boundaries must stay outside the protected channel mask.
  • Keep a stable tuning grid: fractional-N behavior can create repeatable spur patterns; a plan may prefer a cleaner step grid even if it reduces tuning granularity.
Spur fingerprint method (3 steps):
1) Change LO while keeping Fs fixed → tones that track LO are LO-related.
2) Change Fs while keeping LO fixed → tones that move with Fs or Fs/2 are sampling/clock-related.
3) Keep LO and Fs fixed, change digital activity (lane rate / DFE features / throughput) → tones that correlate with activity are coupling-related.
Figure F4 — Spur fingerprint map (which tones move with LO vs Fs vs neither)
Spur fingerprint: move LO or Fs and observe how each tone moves Frequency axis (conceptual) Nyquist Zone 0 Nyquist Zone 1 Fs/2 boundary LO IF Fs LO-related Fs-related Fixed position moves when LO moves moves with Fs / Fs/2 amplitude changes How to use this map Step 1: change LO only • Step 2: change Fs only • Step 3: change digital activity (lane rate / DFE throughput) Classify each tone by movement: LO-related vs Fs-related vs fixed (coupling/power paths).

Search intents covered by this chapter: “SDR spur analysis”, “Nyquist zone aliasing spurs”.

H2-5 · High-speed ADC/DAC selection: ENOB, SFDR, EVM and what they really mean

Converter selection is not about chasing a single headline number. ENOB/SNR sets a noise-limited floor for modulation quality, while SFDR/IMD predicts spurious leakage and adjacent-channel risk. Full-scale range, input bandwidth, and the front-end driver determine whether the chain stays linear under real signals. This chapter translates datasheet specs into system metrics (EVM, ACLR, adjacent-channel mask risk) and provides a model-agnostic selection checklist.

ENOB / SNR → EVM floor (noise-limited) SFDR / IMD → ACLR & spurious leakage Full-scale → headroom vs clipping Input BW + Driver → distortion budget
  • ENOB/SNR → EVM lower bound: when quantization/noise dominates, improving SNR reduces constellation scatter; when jitter or distortion dominates, EVM stops improving even if ENOB is higher.
  • SFDR/IMD → adjacent-channel risk: a low noise floor can still fail a channel mask if a deterministic spur or IMD product lands near/inside protected offsets.
  • Full-scale and headroom: leaving margin avoids compression/clipping under blockers; oversizing full-scale wastes resolution and raises the effective noise floor for small signals.
  • Input bandwidth + driver linearity: the driver and converter form one distortion budget; weak or non-linear drive can erase SFDR advantages on paper.
Selection checklist (model-agnostic, practical):
• Sample-rate range: supports target instantaneous bandwidth plus rate-planning margin for decimation/interpolation.
• Input/output type: differential vs single-ended, common-mode range, impedance/matching approach, and acceptable swing.
• Driver requirement: required output swing at frequency, linearity target, and whether a dedicated RF/IF driver is needed.
• Full-scale strategy: define headroom for blockers; avoid “always max” scaling that forces clipping under real scenes.
• Spur & IMD budget: identify which stage dominates (driver vs converter) and reserve margin for calibration residuals.
• Power/thermal envelope: verify performance stability across temperature (ENOB/SFDR drift) within the cooling budget.
• Multi-channel coherence: channel-to-channel alignment and sync capability for phase-critical paths (platform-internal only).
• Built-in DDC/DUC (if present): reduces data-plane throughput and FPGA load; it does not “fix” jitter- or distortion-limited EVM.

Common traps: (1) selecting by ENOB only (ignores jitter-limited EVM), (2) trusting SFDR without validating the driver/distortion chain, (3) forgetting headroom (rare blockers cause intermittent mask failures).

Figure F5 — Converter specs → system metrics mapping (why each number matters)
Converter specs → system outcomes (EVM, ACLR, mask risk) Converter specs System metrics Mapping ENOB / SNR noise-limited floor SFDR spurious leakage IMD (e.g., IMD3) intermod risk Full-scale / Headroom clip vs wasted range Input BW + Driver distortion budget EVM modulation quality ACLR adjacent leakage Adjacent-channel mask risk spurs + IMD placement Blocking behavior headroom under blockers Spur budget margin how much headroom remains noise floor spur leakage IMD placement headroom distortion

Search intents covered by this chapter: “ENOB vs EVM”, “ADC SFDR SDR receiver performance”.

H2-6 · Clocking & jitter budget: phase noise → sampling uncertainty → SNR/EVM

Clock quality is a hard ceiling for an SDR platform. Sampling jitter turns into equivalent noise that grows with input frequency, and phase noise can appear as “mysterious” EVM limits or spur-like artifacts. A usable platform defines a jitter budget from reference source through cleaner/PLL and distribution to the ADC/DAC clock pins, and verifies which stage dominates.

Engineering relationship (kept practical):
Lower jitter is always better, but the penalty rises quickly as RF/input frequency increases. When EVM stops improving despite adequate ENOB, the chain is often jitter/phase-noise limited rather than DSP-limited.
Stage 1 reference source Stage 2 PLL / jitter cleaner Stage 3 distribution / fanout Stage 4 ADC/DAC clock pins
  • Define the master clock point: identify which clock ultimately times the ADC/DAC sampling (not merely link clocks or FPGA fabric clocks).
  • Allocate margin per stage: reference → cleaner/PLL → distribution → final additive jitter; treat the converter pins as the acceptance point.
  • Validate by symptom + change: if EVM caps with clean noise floor, try controlled changes in clock chain to see whether the limit shifts (clock-limited) or stays (distortion/other).
  • Watch for spur fingerprints: spur-like artifacts that correlate with PLL settings or reference frequency steps typically originate in the clock chain.
Typical failure fingerprints:
• EVM plateaus early while the spectrum floor looks acceptable → phase noise/jitter ceiling (clock chain dominates).
• Spur “ghosts” appear at repeatable offsets and change with PLL configuration → PLL/reference-related spurs.
• Performance drifts with temperature without waveform changes → clock chain sensitivity (reference/PLL/distribution).
• Different bandwidth modes behave inconsistently → rate planning changes expose clock-domain margin problems.
Figure F6 — Jitter budget flow (who dominates the final RMS jitter at the converter)
Jitter budget flow: stage contributions accumulate at ADC/DAC clock pins Conceptual Sankey-style budget (not to scale) Reference source PLL / Cleaner Distribution ADC/DAC pins ref phase noise additive jitter fanout / routing final RMS jitter Dominant stage decides EVM ceiling Practical reading Budget is verified at the converter clock pins; improving a non-dominant stage yields little EVM gain. If EVM saturates across waveforms and bandwidth modes, suspect jitter/phase-noise limits before changing DSP.

Search intents covered by this chapter: “sampling clock jitter SNR”, “phase noise EVM SDR”.

H2-7 · Digital front-end (DFE): DDC/DUC, rate planning, and deterministic latency

The digital front-end (DFE) is where an SDR becomes repeatable: it defines how samples become streams, how throughput is conserved across decimation/interpolation, and how timing remains predictable for triggers and frame boundaries. A robust DFE combines DDC/DUC blocks with disciplined rate planning, well-defined clock-domain crossings, and buffering that prevents intermittent underflow/overflow.

DDC NCO → Mix → CIC → FIR → Decimate DUC Interp → FIR → CIC → Mix → NCO Rate planning Fs ↔ lane throughput ↔ fabric clocks Deterministic latency trigger + frame boundary
  • NCO + mixing: translate the desired channel to baseband (or move baseband up), enabling channelization and frequency agility.
  • CIC stage: efficient large-factor decimation/interpolation; great for throughput relief, but it shifts passband/stopband responsibility downstream.
  • FIR stage: defines channel shape and rejection; it is where EVM/adjacent leakage often becomes “visible” as configuration changes.
  • Rate-change discipline: each mode (bandwidth, decimation factor) must re-check throughput, buffering, and latency expectations.
Rate planning checklist (platform-internal):
• Anchor on converter Fs: start from ADC/DAC sample rate and compute every downstream rate after each decimation/interpolation step.
• Lane throughput margin: keep headroom for framing, overhead, and burstiness; “link up” is not the same as “safe margin”.
• Clock-domain crossings (CDC): explicitly mark link/fabric/stream domains and define CDC boundaries with buffering and backpressure rules.
• Buffer depth: size for worst-case bursts and mode transitions; shallow buffers create intermittent dropouts that look like random faults.
• Mode completeness: validate every supported bandwidth/mode; deterministic latency must remain predictable (fixed offsets are acceptable if known).
Deterministic latency (SDR chain scope):
The goal is that a trigger or sync pulse maps to a repeatable sample index at the output stream. Maintain stable boundaries for trigger alignment, frame markers, and rate-change group delay across modes without expanding to network-wide timing systems.

Failure fingerprints: bandwidth mode changes break alignment (rate/latency not locked), sporadic spikes/dropouts (CDC/buffer margin), or EVM jumps with the same RF/clock (filter chain configuration and folding risk).

Figure F7 — Rate staircase: how Fs becomes lower-rate streams through DDC/DUC
Rate staircase (conceptual): each block changes rate and latency expectations Top: Rx DDC (Fs → streams) • Bottom: Tx DUC (streams → Fs) Rx DDC path Tx DUC path NCO Mix rate: Fs CIC Decimate rate: Fs/4 FIR Channel rate: Fs/16 Streams Frame marks rate: Fs/16 Streams Packets rate: Fs/16 FIR Interp rate: Fs/4 CIC Interp rate: Fs Mix NCO rate: Fs CDC boundary + buffer lane throughput margin deterministic boundary

Search intents covered by this chapter: “DDC DUC SDR FPGA”, “deterministic latency SDR”.

H2-8 · Calibration loops that make SDR usable: IQ imbalance, DC offset, LO leakage

Many “hardware-looking” SDR failures are calibration problems. IQ imbalance creates a visible image mirror, DC offset builds a spike at zero frequency, and LO leakage leaves a stubborn carrier component. A usable platform defines calibration loops with measure → estimate → compensate → verify, chooses when to run them (factory, boot, online), and sets acceptance metrics such as IRR, DC spur level, LO leakage level, and drift stability.

IQ imbalance → poor image rejection DC offset → zero-frequency spike LO leakage → carrier residue Goal → stable metrics vs temperature
  • Mirror image appears: gain/phase mismatch between I and Q reduces image rejection and can masquerade as “bad RF”.
  • Spike at zero frequency: DC bias in the I/Q path or digital offsets create a baseband spur that blocks weak signals near DC.
  • Carrier residue at center: LO feedthrough or leakage produces a persistent tone that may not follow desired modulation behavior.
Calibration strategy (when to use what):
• Factory calibration: removes unit-to-unit static errors and sets a baseline for IQ/DC/LO terms.
• Boot-time self-cal: corrects startup state and temperature-dependent offsets before operation.
• Online tracking: compensates slow drift during operation; focus on stability and non-intrusive measurement windows.
Acceptance metrics (verification-oriented):
• IRR: image suppression after IQ calibration.
• DC spur level: residual baseband spike after DC correction.
• LO leakage level: carrier residue after LO feedthrough mitigation.
• Drift stability: metric stability across temperature and time within the intended operating profile.
Figure F8 — Calibration closed loop: measure → estimate → compensate → verify (IQ / DC / LO)
Calibration loop: Measure → Estimate → Compensate → Verify (repeat until stable) Measure spectrum / tone Estimate gain • phase Compensate matrix • offsets Verify IRR • DC • LO Target: IQ Target: DC Target: LO leakage Factory • Boot • Online Acceptance IRR improves • DC spur reduces • LO residue drops • metrics remain stable vs temperature

Search intents covered by this chapter: “IQ imbalance calibration”, “LO leakage DC offset SDR”.

H2-9 · Gain control & linearity management: AGC, crest factor, keeping EVM/ACLR stable

Stable radio metrics come from disciplined gain staging. The receiver must avoid front-end compression and ADC clipping while keeping the signal high enough above the noise/quantization floor. The transmitter must keep DAC headroom under high crest-factor waveforms so that EVM and ACLR remain predictable across modes and scenes.

Rx boundary compression ↔ headroom ↔ noise floor Tx boundary crest factor ↔ DAC headroom ↔ spectral regrowth Health check EVM vs gain should show a “sweet spot”
  • Compression-first failure: IMD and ACLR worsen early while the noise floor stays acceptable; strong blockers trigger non-linear growth before ADC clips.
  • Clip-first failure: intermittent clipping produces sudden EVM jumps and spur-like artifacts; headroom is insufficient for peaks and blockers.
  • Noise/quantization-first failure: gain too low raises effective EVM floor; improvement is seen as gain increases until other limits dominate.
  • AGC goal (practical): maintain usable headroom while preventing gain pumping; fast attack protects headroom, slower release preserves modulation integrity.
  • Crest factor management (baseband/DAC scope): preserve peak margin in the digital scaling chain so peaks do not saturate the DAC; validate EVM and ACLR together.
Quick self-check: expected EVM vs gain behavior
• Low gain region: EVM improves clearly as gain increases (noise/quantization dominated).
• Sweet spot: EVM flattens (balanced headroom, linearity, and noise).
• High gain / blocker region: EVM degrades (compression or clipping); ACLR/IMD usually worsens at the same time.
If EVM plateaus at all gain settings, revisit clock/jitter ceiling and deterministic alignment (platform-internal).
Example part numbers (AGC / gain chain / measurement aids)
These are widely used SDR-relevant building blocks and references; selection depends on band, bandwidth, and linearity targets.

• Integrated SDR transceiver w/ internal AGC (RFIC): Analog Devices AD9361, AD9363, ADRV9002, ADRV9009
• Wideband VGAs / IF gain blocks: Analog Devices ADL5240, ADL5330 (VGA class), HMC625A (VGA class)
• Digital step attenuators (gain trim / leveling): Analog Devices HMC540B, HMC624A
• RF power / envelope detectors (AGC sensing): Analog Devices ADL5519, ADL5920
• DAC headroom / high-speed Tx converters (examples): Analog Devices AD9164, AD9172; Texas Instruments DAC38J84
• High-speed Rx converters (examples): Analog Devices AD9208, AD9680; Texas Instruments ADC12DJ3200
Figure F9 — Three-way gain squeeze: front-end linearity, ADC headroom, and digital scaling
Keep metrics stable by balancing three limits (who breaks first?) Front-end linearity ADC headroom Digital scaling LNA / VGA Mixer / Driver IMD / ACLR risk fails: compression first Full-scale (FS) Peaks + blockers Clip / overload fails: clip first Digital gain / AGC Crest margin Noise / quantization fails: noise first Stable EVM / ACLR region enough headroom • no compression • adequate SNR • controlled peaks

Search intents covered: “AGC design SDR”, “crest factor EVM ACLR”.

H2-10 · Bring-up, validation & troubleshooting: proving the radio is healthy

A healthy SDR is proven by an ordered bring-up sequence and repeatable measurements. The fastest path is dependency-driven: power and clocks first, then high-speed link integrity, then controlled stimuli (loopback, single-tone, two-tone), and finally modulation tests where EVM/ACLR must remain stable across modes and temperature.

Bring-up sequence (practical gates):
1) Power stable → 2) Clocks present/stable → 3) High-speed link stable → 4) Loopback passes → 5) Single-tone checks → 6) Two-tone linearity → 7) Modulation (EVM/ACLR) → 8) Stability vs temperature/time.
Noise & spur floor + spur map + DC/LO residues Linearity two-tone IMD + blocking behavior Modulation EVM + ACLR + mode repeatability Stability drift vs temperature/time
  • Poor EVM with normal noise floor: clock/jitter ceiling or deterministic alignment/sync issues (platform-internal).
  • High image mirror: IQ imbalance and calibration residuals (IRR not meeting target).
  • Fixed spur(s): PLL/reference coupling or clock-chain related spurs (configuration-correlated tones).
  • Metrics collapse with temperature: drift sensitivity (reference/clock chain, gain staging margins, or thermal stability).
  • ACLR poor while EVM acceptable: non-linearity or clipping/crest margin issues (gain staging and headroom).
Example part numbers (bring-up anchors and reference components)
• Jitter cleaner / clock synthesizer: Analog Devices HMC7044, AD9528; Texas Instruments LMK04828
• Low-noise PLL / RF synthesizer (LO/reference building blocks): Analog Devices ADF4371, ADF5355
• Timing / clocking control (platform clock mgmt examples): Analog Devices AD9545
• High-speed ADC/DAC examples for validated chains: Analog Devices AD9208, AD9680, AD9164, AD9172; Texas Instruments ADC12DJ3200, DAC38J84
• Integrated transceiver reference platforms: Analog Devices ADRV9002, ADRV9009, AD9361
• RF detector for leveling / sanity checks: Analog Devices ADL5519, ADL5920
Figure F10 — Bring-up flowchart: stepwise proof with PASS/FAIL gates
Bring-up checklist flow (conceptual): prove each dependency before moving on Step-by-step gates If FAIL, check 1) Power stable 2) Clocks present & stable 3) High-speed link stable 4) Loopback passes 5) Single-tone checks 6) Two-tone linearity (IMD) 7) Modulation: EVM + ACLR PASS PASS PASS PASS PASS PASS PASS Clock chain phase noise / jitter / spurs Link integrity errors / alignment / margin Single-tone signs spur / image / DC / LO Two-tone signs IMD growth / headroom Modulation signs EVM / ACLR / mode repeat Stability temperature / drift

Search intents covered: “SDR bring up checklist”, “EVM troubleshooting SDR”.

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H2-11 · FAQs (Software-Defined Radio / SDR)

These FAQs target the most common SDR bring-up and architecture questions for an avionics/mission SDR platform (RFIC + high-speed converters + clock tree + FPGA/DFE + calibration + validation).

Q1 What is the practical boundary between an SDR “transceiver IC” and an SDR “platform”?
A transceiver IC mainly covers RF/analog signal conversion (tuning, mixing or direct conversion, gain blocks, and sometimes basic DDC/DUC). An SDR platform adds what makes results repeatable: clock tree/jitter control, converter/link integration, deterministic data-plane handling, calibration loops, and a validation workflow. Typical transceiver ICs: AD9361/ADRV9002; typical platform blocks span H2-3, H2-6, H2-7, H2-10.
Mapped: H2-2/H2-3 (definition + end-to-end architecture)
Q2 Zero-IF vs low-IF vs direct sampling—how to choose for wideband?
Choose by which error is easiest to control. Zero-IF simplifies filtering but requires strong handling of DC offset, LO leakage, and IQ imbalance. Low-IF reduces DC sensitivity but re-introduces image management and IF-related spurs. Direct sampling can widen coverage but raises clock/jitter sensitivity, alias planning, and blocker dynamic-range demands. Validate the choice using spur tracking and calibration closure (H2-4, H2-8).
Mapped: H2-2/H2-4 (partition + spur sources)
Q3 Why does EVM refuse to improve even with a “better” ADC?
EVM often hits a ceiling set by sampling clock jitter/phase noise, spurs coupled into the clock tree, deterministic alignment issues, or clipping/linearity limits—not by ENOB alone. If EVM is flat across gain settings, the limiter is usually clock/synchronization or deterministic latency. If EVM improves with gain then worsens, headroom/linearity is likely dominant. See converter mapping (H2-5) and jitter budgeting (H2-6).
Mapped: H2-5/H2-6 (converter metrics + jitter budget)
Q4 How do sampling clock jitter and phase noise show up in spectrum/EVM?
Clock phase noise lifts the close-in noise “skirt” around tones and can create correlated spurs if PLL/reference coupling exists. Sampling jitter raises an effective noise floor that worsens with higher input frequency, producing an EVM floor that does not respond to gain tweaks. A quick diagnosis is to vary carrier frequency or clock source and observe whether EVM/noise skirt changes accordingly. See H2-6 for budget and isolation points.
Mapped: H2-6 (clocking & jitter budget)
Q5 JESD204 link is up, but samples look wrong—what are the top causes?
“Link up” does not guarantee correct framing. Common causes are lane mapping/bit order issues, framing/multiframe alignment mismatches, deterministic latency assumptions not met, and clock-domain crossings with insufficient buffering/backpressure. The fastest isolation path is: digital/link loopback → known single-tone injection → rate sanity checks at each DFE stage. This keeps RF variables out until the data plane is proven. See H2-3, H2-7, and H2-10.
Mapped: H2-3/H2-7/H2-10 (data plane + DFE + bring-up)
Q6 How to recognize LO leakage vs DC offset vs IQ imbalance from a spur plot?
DC offset typically appears as a spike at zero frequency in baseband. LO leakage presents as a stubborn carrier component at the center frequency (especially visible in Tx). IQ imbalance produces a mirrored image tone symmetric about DC (or the carrier), reducing image rejection (IRR). A practical discriminator is spur tracking: change LO or Fs and observe which tones move with LO, with Fs, or remain fixed. See H2-4 and H2-8.
Mapped: H2-4/H2-8 (spur fingerprints + calibration loops)
Q7 What IRR (image rejection) is “good enough,” and what sets the limit?
IRR is “good enough” when the image no longer drives system metrics (EVM/ACLR or spur mask failures) in the intended operating modes. The limit is set by residual gain/phase mismatch, temperature drift, quantization/DFE compensation resolution, and how often calibration can run (factory, boot, or online). Verify IRR across temperature and bandwidth modes rather than at a single point. See H2-8 for closure and acceptance checks.
Mapped: H2-8 (IQ/DC/LO calibration + acceptance)
Q8 Why does changing LO or Fs move some spurs but not others?
Spurs fall into families. LO-related products typically shift with LO tuning. Sampling/clock-related products shift with Fs or with reference/PLL settings. Some tones remain fixed because they come from digital coupling, power-supply ripple, or static interference paths. The minimal experiment is to vary one variable at a time (LO, Fs, reference/PLL) and classify which spurs track which knob; the tracking result points to where shielding, isolation, or clock cleanup is needed. See H2-4.
Mapped: H2-4 (frequency plan + spur tracking)
Q9 How should AGC be split across RF gain, ADC headroom, and digital gain?
Split AGC by what each stage protects. RF gain handles blocker resilience and prevents front-end compression (linearity/IMD). ADC headroom management prevents peak clipping and preserves deterministic performance under crest factor and interference. Digital gain is best for fine trimming and mode-to-mode leveling without pumping analog stages. A useful check is EVM/ACLR versus gain: a stable “sweet spot” indicates the split is balanced. Example detector aids: ADL5519/ADL5920. See H2-9.
Mapped: H2-9 (gain & linearity management)
Q10 What measurements prove wideband linearity without relying on a specific waveform?
The most waveform-agnostic evidence is two-tone IMD (3rd/5th products), blocker tests (gain compression and intermod growth under a strong adjacent tone), and a spur map across tuning states. These tests expose nonlinearity and headroom limits directly, then modulation EVM/ACLR becomes a confirmation rather than the only proof. Tie results back to converter SFDR/IMD expectations and gain staging decisions. See H2-5 and H2-10.
Mapped: H2-10/H2-5 (validation flow + converter limits)
Q11 How to maintain multi-channel phase coherence in a practical SDR chassis?
Coherence requires three locks: a common low-jitter reference distribution, deterministic alignment (trigger/frame boundaries), and consistent NCO/DFE reset behavior across channels. Breakage usually comes from independent PLL drift, unbounded CDC buffering, or mode changes that alter group delay without compensation. A practical method is to define a coherence bring-up mode that freezes rate planning and latency, then verify repeatability across temperature. Typical clock-tree parts: AD9528, HMC7044, LMK04828. See H2-7 and H2-6.
Mapped: H2-7/H2-6 (deterministic latency + jitter budget)
Q12 What is the fastest bring-up sequence to isolate clock vs data-plane vs RF issues?
Use a dependency-first sequence: power stability → clocks/jitter sanity → high-speed link integrity → loopback → single-tone checks → two-tone IMD → modulation EVM/ACLR → temperature drift repeatability. This isolates data-plane mapping and deterministic latency before RF complexity, then isolates spur fingerprints before waveform dependence. The method prevents “random chasing” by proving one layer at a time. See H2-10 for the step gates and failure fingerprints.
Mapped: H2-10 (bring-up, validation, troubleshooting)

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