Smart Stylus / Active Pen: Hardware, IC Blocks & Debug Guide
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Core idea: Portable storage enclosures and card readers fail in repeatable ways—mode fallback, random disconnects, unstable CFexpress/UHS links, and “10Gbps but slow” performance—most of which can be proven quickly by checking power droop, high-speed margin, protection return paths, and thermal signatures.
What this page delivers: An evidence-first workflow (two probes + key logs) to isolate whether the root cause is power/hot-plug, SI/layout, ESD/EMI protection, firmware telemetry, or heat—then apply the first fix with minimal iterations.
H2-1 — Page Intent, Boundary, and Fast Triage Map
This chapter prevents “wrong-layer debugging” by routing symptoms into four hardware evidence chains: Sense Chain, Link & Timing, Power & States, and Robustness (ESD/EMI). Only pen-side hardware, signal-level coupling, low-power/charging rails, and EMC/ESD evidence are covered.
30-second triage: pick the matching symptom group, take the first two measurements, then jump to the deep chapter.
| Symptom group | First 2 measurements (fast proof) | Go to (deep chain) |
|---|---|---|
| Pressure / tilt feels wrong drift, jump, non-linearity |
(1) Raw sensor/ADC codes (no post-processing) (2) AFE reference / excitation stability (ripple, settling) |
H2-3 Pressure stack H2-4 Tilt/orientation H2-5 Buttons/hover robustness |
| Disconnect / not recognized / big lag pairing issues, strokes drop |
(1) Coupling waveform envelope / amplitude (margin) (2) Link counters (retry, sync-lost, CRC-fail if available) |
H2-6 Coupling link budget H2-7 Latency & sampling budget |
| Power issues reboot, fast drain, cannot charge |
(1) VBAT droop during write/burst + reset cause flags (2) Three-mode current: shipping / standby / active |
H2-8 Power tree & state machine H2-9 Charging & power-path |
| Intermittent / environment-sensitive winter worse, near phone worse |
(1) Repro matrix + failure rate (condition → probability) (2) Pre/post-ESD: standby current shift + function degradation |
H2-10 EMC/ESD injection paths H2-11 Field debug SOP |
Common misroutes to avoid: pressure accuracy issues are often AFE/reference or mechanics before “software tuning”; link failures are often coupling margin or power/EMI modulation before “protocol blame”; fast drain is often AoN leakage or periodic scanning before “bad battery.”
H2-2 — System Architecture of an Active Pen (Block-Level)
This chapter establishes a shared language for the whole page by separating the data path (sensor → AFE/ADC → processing → modulation) from the energy path (battery → protection → charging/power-path → rails/domains). The goal is not a parts list, but a cause-and-evidence map: where drift, lag, dropouts, and intermittency are born, and where to measure first.
Data path (what is sensed and emitted):
- Tip inputs: pressure (FSR/capacitive/strain-class), tilt/orientation (IMU or capacitive/magnetic), buttons/eraser, and optional hover/proximity.
- AFE + ADC: excitation/reference, front-end filtering, sampling schedule, and raw-code integrity are the first checkpoint for accuracy and stability.
- Processing: debouncing, filtering, linearization, and temperature compensation are treated as parameterized blocks tied to evidence (raw codes, references, timing), not app-layer handwriting algorithms.
- Modulator/driver: generates the coupling waveform and timing windows used by the display/digitizer; link margin is observed by envelope/amplitude + error counters.
Energy path (what keeps it alive and quiet):
- Source & protection: battery, reverse/short protection, and ESD-sensitive external nodes (tip, charge contacts, buttons).
- Charging & power-path: pogo/dock/inductive receiving (device-side) with power-path decisions that determine whether noise leaks into sensing or coupling.
- Rails & domains: split rails into AoN (wake logic), Active (sampling/processing), and Burst (coupling transmit / optional RF). Domain separation is the hardware lever for both battery life and noise control.
Evidence probes (where to measure first):
| Probe | What to capture | What it proves (fast discriminator) |
|---|---|---|
| P1 VBAT | Droop during write/burst; transient sag vs reset timing | Peak-current path or weak source; separates “power collapse” from pure link/sense issues |
| P2 Core rail | Ripple + brownout threshold crossing; reset cause flag correlation | SoC stability vs peripheral noise; confirms UVLO/brownout-driven symptoms |
| P3 AFE ref/excite | Reference/excitation ripple + settling during pressure sampling | Accuracy drift/noise rooted in analog reference rather than mechanics or processing |
| S1 Coupling envelope | Amplitude/envelope stability; dropouts aligned with burst events | Link margin loss from EMI/rail noise vs protocol-level guesses |
| S2 Raw sensor codes | Unfiltered pressure/tilt codes; saturation/clipping; step response | Distinguishes sensor/AFe/ADC faults from later-stage filtering/linearization |
| L1 Reset cause | Brownout flags, watchdog, hard fault, last-state snapshot | Separates “power integrity” from “logic deadlock” and speeds root-cause loops |
| L2 Link counters | Retry/sync-lost/CRC-fail (if present) vs time and conditions | Quantifies compatibility vs random noise; enables failure-rate A/B tests |
| L3 State transitions | Shipping/standby/hover/write entry/exit timing + current | Finds AoN leakage and wake-latency sources without guessing |
H2-3 — Pressure Sensing Stack (Mechanics → AFE → ADC → Linearization)
Pressure “feels wrong” is rarely one problem. It is a chain: force path (mechanics) → sensor element → AFE (excitation/reference/filtering) → ADC (raw codes) → linearization (tables + temperature parameters). The fastest isolation strategy is to attach evidence to each stage, then eliminate stages one by one.
Stage A — Mechanics (force path)
Mechanical creep, friction, and assembly bias can reshape the force delivered to the sensor. Evidence is found by repeatability under the same load profile and sensitivity to press location / pen rotation.
Stage B — Sensor element (boundary comparison)
FSR tends to show creep and hysteresis; strain-based sensing is more linear but highly sensitive to preload and temperature; capacitive sensing is sensitive to parasitics/contamination; piezo is strong on dynamic changes but weak for static force.
Stage C — AFE (excitation / reference / filtering)
Excitation stability and reference ripple directly modulate the measured force. Front-end filtering and sampling schedule determine noise floor, 50/60 Hz pickup, and “jump” perception.
Stage D — ADC + Linearization (parameters + evidence)
Linearization is treated as parameterized blocks (breakpoints, slopes, offsets, temperature tables). Debug focuses on raw codes and table behavior, not application handwriting algorithms.
Evidence set (how to prove the root stage fast):
| Test | What to record | Fast discriminator |
|---|---|---|
| 10–20 s static hold drift shape |
Raw ADC code vs time under constant load; capture AFE ref/excitation ripple in parallel if possible. | Drift that scales strongly with load suggests sensor/mechanics creep; drift that tracks rail/reference changes suggests AFE/power coupling. |
| Load / unload loop hysteresis |
Rising and falling curves over the same force range; repeat across press locations if feasible. | Stable gap between curves points to element hysteresis; gap that changes with press point/rotation suggests mechanics (friction/return path). |
| Raw code + reference ripple noise/jump |
Raw ADC codes aligned with AFE reference/excitation ripple; repeat during charging or burst events. | Noise that rises synchronously with ripple/burst indicates electrical coupling; noise independent of rails indicates sensor/mechanical sources. |
H2-4 — Tilt / Orientation Sensing (IMU vs Capacitive/Magnetic Methods)
Tilt instability (angle drift, direction jumps, broken slanted strokes) can be classified by three verifiable buckets: (1) sensor error (bias/scale/temperature/vibration), (2) geometry and coordinate definitions (assembly angle, axis mapping), and (3) electrical coupling (charging/burst EMI) that injects synchronous noise into tilt measurement.
Method A — IMU-based tilt
Bias drift and temperature sensitivity dominate “slow angle walk” at rest; saturation/clipping dominates “direction jumps” during fast motion; timestamp jitter can appear as stroke discontinuity when sampling is not uniform.
Method B — Capacitive / magnetic tilt
Geometry and parasitics dominate: assembly eccentricity creates fixed offsets; magnetic demagnetization/temperature drift changes scale; capacitive methods can be sensitive to contamination and external coupling paths.
Most common engineering misses
Coordinate-frame mismatch (sensor axis vs pen body vs screen), assembly angle bias, and insufficient range/bandwidth are repeat offenders. Each produces a distinct evidence signature.
Evidence set (simple, repeatable discriminators):
| Test | What to record | Fast discriminator |
|---|---|---|
| Rest drift trend Allan-like |
Tilt output (or raw accel/gyro) at rest for 60–120 s; log temperature if available. | Slow monotonic walk suggests bias/thermal drift or fixed axis bias; low-frequency wandering that tracks temperature suggests missing compensation. |
| Fast swing check clip/saturate |
Repeat a fast tilt change; watch for plateau/clipping in raw sensor channels or derived angle. | Flat-topped or cut waveforms indicate insufficient range; noisy but not clipped indicates bandwidth/filtering or vibration pickup. |
| Noise sync with burst/charge coupling |
Tilt noise amplitude while triggering charging or coupling burst; align with VBAT/Burst-rail events if accessible. | Synchronous noise rise implies EMI/power coupling (route to power/robustness chapters); no sync points back to sensor/geometry causes. |
H2-5 — Buttons, Eraser, Hover/Proximity: Input Robustness & Debounce
“False taps”, intermittent eraser switching, and unstable hover are best debugged as an input chain: input source → front-end bias/protection → sampling window → debounce/state machine → event output. Robustness is proven by statistics (edge jitter, false-trigger rate) and post-ESD state checks (stuck pins, current rise).
Input boundary: mechanical vs touch / Hall
Mechanical buttons show bounce timing clusters near press/release. Touch/cap inputs drift with environment and parasitics. Hall methods are geometry/magnet dependent (offset/temperature/demagnetization) and can be affected by external fields.
Bias & leakage: pull-up/down is a robustness knob
Pull choices and leakage paths decide whether a line floats into “almost pressed”. Leakage can come from ESD devices, contamination, humidity, or clamp paths. Evidence is found by temperature/humidity correlation and static input current checks.
Debounce: describe only what is observable
Debounce is a windowed confirmation policy: sampling period (Ts), confirm count (N), long-press threshold (Tlong). Debug uses edge counts, minimum pulse width, and per-hour false-trigger statistics—no OS/app behavior required.
ESD-after anomalies: stuck pins and latch-up signatures
Post-ESD failures often appear as stuck-high/low inputs, shifted thresholds, or a sudden rise of IO-domain current. The most valuable discriminator is “stuck + current rise” (latch-up / clamp damage) versus “stuck without current rise” (threshold shift).
Evidence checklist (record + statistic + discriminator):
| Evidence | Record | Fast discriminator |
|---|---|---|
| GPIO edge jitter bounce vs noise |
Raw edge timestamps or sampled GPIO trace; annotate charging/burst state and temperature if available. Compute: edge count per press, minimum pulse width, and p95 bounce duration. | Jitter clustered at press/release suggests mechanical bounce/RC; jitter synchronized with charging/burst suggests EMI/power coupling; strong temperature/humidity dependence suggests leakage/parasitics. |
| Long-press false rate false activation |
Long-press events per hour when no intentional press occurs; correlate with posture, proximity, and environment. | Events rising with humidity/skin contact points to threshold drift/leakage; events rising during charging points to coupled noise or ground reference movement. |
| Post-ESD state stuck / latch-up |
After an ESD event: GPIO level state, IO-domain current, and reset behavior. Optional: input pin voltage under known pull state. | Stuck + IO current rise suggests latch-up/clamp damage; stuck without current rise suggests threshold shift or pull network damage. |
H2-6 — Coupling to the Screen: Signal-Level Link Budget (AES/MPP/USI Only as Needed)
Recognition failures, disconnects, and latency spikes are best reduced to signal evidence, not “protocol mystery”. This chapter stays at the signal layer: coupling amplitude/envelope, noise floor, timing windows, and observable counters (retry, sync lost, CRC fail) when available. No OS/driver/app discussion is included.
What coupling means (as observables)
Coupling is measured by envelope amplitude, spectrum/noise floor, and frame continuity. A stable link needs margin in both amplitude vs noise and timing alignment vs sampling windows.
Link budget: three common margin killers
Margin collapses when (1) screen-side noise floor rises (display/backlight/charging), (2) ground reference moves (ground bounce), or (3) ESD damage degrades the front-end (amplitude loss / spectral distortion).
Timing windows (describe by metrics, not standards)
Treat wake and sample windows as measurable alignment problems. Observable outputs include missed frames, retransmit bursts, and time-to-recognize changes across conditions.
Evidence toolkit: waveform + counters + A/B failure rate
Near-field probe or scope captures envelope/noise. Device counters (if exposed) separate CRC errors from sync loss. A/B failure-rate comparisons across screens, charging states, and posture distinguish compatibility from random noise.
Strong evidence triad (outputs that close the loop):
| Evidence | Output to capture | Fast discriminator |
|---|---|---|
| Coupling waveform envelope + noise |
Envelope peak/average, noise floor, and frame continuity (missing bursts / distorted envelope). Repeat during charging and non-charging. | Amplitude drop with stable noise suggests coupling efficiency loss; noise rise synchronized to charging suggests environment/power coupling; spectral spikes suggest screen noise or ESD-related distortion. |
| Counters if available |
retry count, sync lost events, CRC fail ratio, and time-to-recognize. Log per minute or per session for comparability. | CRC fail dominant suggests signal quality/noise; sync lost dominant suggests timing-window misalignment; retry bursts without CRC increase suggests contention/backoff window effects. |
| A/B failure rate compat vs random |
Failure rate (%) across screen A/B, charging on/off, and posture/distance. Use fixed trial counts per condition. | Consistent failure on one screen suggests compatibility/window or screen noise; broad degradation during charging suggests power/EMI coupling; posture-dependent failure suggests channel sensitivity. |
H2-7 — Latency & Sampling Budget (Where “Ink Lag” Really Comes From)
“Ink lag” is not a single number. It is the sum of sampling, windowed confirmation, filter group delay, frame/modulation time, and the screen-side capture window. First-stroke lag must be separated from steady-state lag because wake/lock/settle steps can dominate only the first stroke.
Latency decomposition (use observable terms)
Treat latency as a budget: Ttotal ≈ Tsample + Tdebounce + Tfilter + Tframe + Tscreencap. Each term has a measurable proxy: timestamps, window sizes, and frame continuity counters.
Sampling and windows create “hard delay”
Sampling period sets a floor (events are observed on the next sample). Debounce/confirmation windows add a deterministic delay (N×Ts or a fixed hold time). If inputs share a scheduler, queueing adds extra wait before a sample is serviced.
Filter group delay is the stability vs speed knob
Stronger smoothing reduces jitter but increases group delay and makes the output “follow behind”. Use shorter windows for fast ink, and reserve heavier smoothing for low-speed or stationary segments (policy-level choice without algorithm deep dive).
First-stroke penalty (wake / lock / AFE settle)
First-stroke lag often includes wake time, PLL/clock lock (if used), and AFE bias/settle before valid samples exist. This penalty can vanish after the system is already active, so it must be measured separately.
Evidence-first optimization order
Reduce first-stroke lag by shrinking wake/settle requirements, then tune debounce and filter windows, and only then revisit frame/screen windows if evidence shows a capture alignment problem.
Evidence checklist (minimal, repeatable):
- Measure first-stroke vs continuous lag separately: compare p50/p95 lag for “first visible stroke” versus steady 10 s writing.
- Timestamp alignment: log sample-start vs transmit-start markers; large jitter indicates scheduling/queueing; drift indicates cross-domain timing misalignment.
- Window mapping: record debounce window (N×Ts) and filter window length; verify whether the measured lag matches the configured window budget.
H2-8 — Power Tree & Ultra-Low-Power State Machine (Battery Life by Design)
Battery life is determined by domain boundaries (Always-on vs Active) and by the state machine duty cycle. Intermittent resets and “dies in a few days” complaints are validated by a brownout evidence chain: UVLO/BOR trigger, reset cause log, rail droop waveform, and peak current correlation.
AoN vs Active: a domain boundary rule
Always-on keeps only what is required for wake and minimal retention. Anything that can be deferred to “after wake” should live in Active: IMU high-rate sensing, proximity scanning, LEDs, and strong pull networks.
State machine determines average current
Average current is the sum of each state’s current times its duty cycle. Optimize by reducing the time spent in high-scan hover states and by ensuring no “active-only” domain leaks into standby.
Common current sinks (“black holes”) with proof
Persistent LED drive, pull-up leakage under humidity, IMU always-on, periodic scans, and clamp leakage after ESD all show up as elevated shipping/standby current. Proof is a stable current plateau under a fixed state.
Brownout evidence chain (reboot / freeze)
A brownout is proven by UVLO/BOR evidence, a reset-cause log, and correlated rail droop during peak events. Separate “VBAT droop” from “core-rail collapse” to localize source vs regulator causes.
Three-mode targets (write as ranges)
Shipping should be in the µA class, standby in tens of µA class (depending on wake policy), and active in the mA class with burst peaks. Peak current must be evaluated separately from average current when reboot symptoms exist.
Evidence checklist (first two measurements):
- Current modes: capture stable plateaus for shipping / standby / active; also capture peak current during hover/write/burst events.
- Reset cause + rails: correlate reset reason with waveforms on VBAT and core rail; add AFE rail when sensing noise or calibration jumps appear.
- Brownout discriminator: VBAT droop with matching core collapse points to source/peak load; stable VBAT with core collapse points to regulator/protection gating issues.
H2-9 — Charging & Battery Management (Pogo/Dock/Inductive) Without Drifting Into Charger Topology
Charging issues are solved on the pen side by separating entry/contact behavior, power-path states, protection/thermal limiting, and noise coupling into sensing and screen-coupling links. This chapter stays inside the pen: charge input → charger/power-path → battery/protection → domain rails and isolation.
Entry types (fault signatures, not topology)
Pogo/dock contacts show intermittent current plateaus and ripple from micro-disconnects; inductive entry shows fixed-band noise and heating under misalignment or foreign objects. Treat entry as a measurable “input quality” term before blaming the charger IC.
Power-path and “charge-while-write” isolation
Power-path routing decides whether the system rides on the charger input during charging. When writing while charging, isolate sensitive domains (AFE/IMU/coupling Tx) from switching and ground noise by domain gating and controlled return paths.
Protection and thermal limiting (symptom map)
OVP/OCP/OTP events appear as current step-down, re-try loops, or charging pause. Secondary battery protection can look like sudden “no charge” until re-seat or cooldown. Use status/fault indicators (if available) to avoid guesswork.
Charging noise that degrades sensing and coupling
Charging can raise the ground/noise floor and modulate the coupling envelope, causing recognition failures or “jumping” ink. Fixed-frequency spikes often correlate with charging switching; broadband floor rise correlates with return-path and load-transient issues.
Evidence-driven fix order
First prove entry/contact quality (current continuity). Next prove protection/thermal limiting (fault + temperature + current trend). Then prove noise injection (coupling envelope and IMU/AFE noise synchronized with charging state).
Evidence checklist (minimal, repeatable):
- Correlation test: toggle charging (on/off) and capture whether coupling envelope or IMU/AFE noise worsens synchronously.
- Status/fault capture: read charger IC state pins/interrupts/fault codes (if exposed) to confirm OVP/OCP/OTP limiting rather than “slow by design”.
- Thermal + current trend: log charge current and key hot-spot temperature; step-down following temperature rise indicates thermal regulation.
H2-10 — EMC/ESD/Robustness: Why “Intermittent” Happens
“Intermittent” failures are usually repeatable once the injection path and vulnerable node are identified. This chapter focuses on pen-side ESD/EMI entry points (tip, buttons, charging contacts, enclosure seams), common failure modes (latch-up, GPIO stuck, reference drift, burst interference), and evidence-driven design levers (TVS placement, return paths, partitioning, shield, filtering).
ESD/EMI injection paths (where energy enters)
Tip and button lines are exposed to hand and clothing discharge; charging contacts invite metal-to-metal discharge; enclosure seams support surface discharge paths. Path identification comes before adding protection parts.
Typical intermittent failure modes (what it looks like)
Latch-up shows as elevated standby current and heat; GPIO stuck shows persistent “pressed” or dead inputs; reference drift shows offset in pressure/tilt thresholds; burst interference shows correlation with nearby phones, charging, or RF activity.
Design levers (placement and return path first)
TVS placement near the entry, short return path, and controlled ground partition keep surge current out of AFE references. Shielding and filtering should reduce injected bandwidth and prevent return current from crossing sensitive domains.
Reproduction and failure-rate metrics
Define environment (humidity, clothing, carpet, charging state, phone proximity) and measure failure rate per 100 trials or per hour. Repeatability enables before/after comparison for layout or protection changes.
Before/after evidence (fast discriminator)
Capture standby current change after events, check whether any function is permanently degraded, and collect node-level evidence: waveforms, counters (retry/CRC if available), temperature rise, and current anomalies.
Evidence checklist (long-tail friendly):
- Reproduction recipe: record humidity/clothing/carpet/charging/phone distance and a numeric failure rate (per 100 trials or per hour).
- Before/after standby current: compare shipping/standby current pre/post event; persistent rise indicates leakage or latch-up damage.
- Node evidence: tip/AFE reference ripple and drift, button GPIO jitter/stuck, charge-contact ground noise, coupling envelope/CRC/retry, and local hot-spot temperature.
H2-11 — Validation & Field Debug Playbook (Symptom → Evidence → Isolate → First Fix)
This SOP converts common active-pen failures into repeatable steps using the smallest set of measurements. Each symptom card follows the same structure: Symptom, First 2 measurements, Discriminator, First fix. The page stays pen-side: input chain, coupling evidence, power states, charging noise, and EMC/ESD robustness.
1) Pressure drifts upward slowly (creep vs AFE drift)
Typical report: static press for 10–20 s and the value keeps rising or “breathes” with temperature.
First 2 measurements
- Raw evidence: ADC raw code (or AFE output) during a 20 s constant-force hold.
- Supply/reference: VREF or AFE rail ripple captured on the same time axis.
Discriminator
- If drift correlates with VREF/rail ripple changes → power/AFE coupling dominates.
- If drift shape follows hold time even with stable rails → mechanical creep/hysteresis dominates.
First fix (minimal change)
- Stabilize reference and AFE rail: add dedicated low-noise LDO / improve decoupling / isolate noisy domains.
- Shorten sensitive loops: keep sensor return and AFE reference return away from charging/Tx current.
- Use a “static-hold calibration gate” (parameter-level): treat slow drift as a separate regime from dynamic strokes.
2) Tilt/orientation drifts or jumps (IMU bias vs EMI vs assembly)
Typical report: tilt angle slowly walks when still, or jumps during fast motion or near RF/charging.
First 2 measurements
- Still test: tilt output mean + RMS noise during a 60 s stationary hold.
- State correlation: compare noise during charging ON/OFF or Tx burst ON/OFF.
Discriminator
- Noise rises synchronously with charging/Tx state → EMI/rail noise injection dominates.
- Bias shifts between units or after re-assembly → assembly angle/axis definition dominates.
- Clipping during fast motion → IMU range/ODR limits dominate.
First fix (minimal change)
- Gate IMU ODR: low ODR in standby/hover, high ODR only in write; avoid “always-high ODR”.
- Isolate IMU rail/ground: local decoupling; keep switching/charge return away from IMU/AFE reference return.
- Lock coordinate conventions in firmware parameters (axis swap/sign) and verify with a 3-point fixture test.
3) Not recognized / frequent drops (link margin vs rail noise vs ESD damage)
Typical report: pen is not detected, drops mid-stroke, or works on one screen but fails on another.
First 2 measurements
- Coupling evidence: capture coupling envelope/noise floor (scope + near-field probe or test pad if available).
- Stability metric: retry/CRC/sync-lost counters (if available) or failure rate across screens/charging states.
Discriminator
- Fails mainly on specific screens but stable on others → timing/window/compatibility dominates.
- Fails mainly during charging or high-load states → rail noise / ground bounce dominates.
- After ESD event, failure becomes persistent and standby current shifts → damage/leakage dominates.
First fix (minimal change)
- Raise margin: reduce noise on Tx/coupling domain rail; tighten return path for coupling loop.
- Improve ESD containment: clamp at the entry, keep ESD return short and away from AFE reference.
- Use a “compatibility matrix” test: screen A/B, distance near/far, charging on/off to isolate window vs noise.
4) Large first-stroke lag (wake/settle vs sampling/window)
Typical report: first stroke after idle is late, but continuous writing is acceptable (or both are slow).
First 2 measurements
- Time markers: GPIO timestamp markers for wake start → ready-to-sample → first transmit.
- End-to-end: measure first-stroke delay separately from steady-state delay (p50 + p95).
Discriminator
- If wake→ready dominates first-stroke delay → wake/PLL/AFE settle dominates.
- If steady-state delay is also high → sampling/filter/window dominates.
First fix (minimal change)
- Reduce settle: keep only the minimum always-on pieces needed for fast resume; avoid re-locking high-cost domains.
- Trim debounce/filter windows in “write-enter” path; use stronger smoothing only after the stroke stabilizes.
- Ensure AFE reference is stable before first sample; avoid enabling multiple noisy domains simultaneously.
5) Standby drain (AoN leakage vs periodic scan vs pull-up loss)
Typical report: fully charged pen loses battery after a few days with no use.
First 2 measurements
- Standby current: average + peak over 30–60 s after the state is stable.
- Wake signature: periodic spikes or wake logs indicating scan timers, IMU always-on, or GPIO chatter.
Discriminator
- Regular current spikes → periodic scan/polling dominates.
- High flat current with no spikes → leakage path (ESD parts, pulls, charger leakage) dominates.
First fix (minimal change)
- Move scanning to event-triggered wake (tip/hover) where possible; reduce scan duty cycle.
- Gate sensor domains with a load switch; keep AoN minimal (only wake + state memory).
- Audit pull-up/pull-down and “always-on LEDs”; verify charger leakage in shipping mode.
6) Jitter/jumping while charging (charging noise coupling)
Typical report: ink becomes noisy or jumps only when on dock/charger; improves immediately when removed.
First 2 measurements
- Coupling envelope: compare amplitude/noise floor with charging ON vs OFF.
- Sensor noise: compare IMU or pressure/AFE noise RMS with charging ON vs OFF.
Discriminator
- If envelope and sensor noise worsen together when charging → injected switching/ground noise dominates.
- If only envelope worsens (sensor noise stable) → coupling loop/return path dominates.
First fix (minimal change)
- Separate return paths: keep charging current return away from AFE reference and coupling loop return.
- Use staged enables: delay coupling Tx start until charger switching transients settle.
- Improve rail hygiene: dedicated LDO for AFE/IMU; ferrite bead partition where appropriate.
7) Intermittent after ESD / near phone (injection path → vulnerable node)
Typical report: failures cluster in winter/low humidity, after a static zap, or when placed near a phone.
First 2 measurements
- Before/after standby current: compare shipping/standby current pre/post event to detect leakage or latch-up.
- Node evidence: capture one vulnerable node (AFE ref ripple OR GPIO stuck OR coupling envelope) under the same trigger condition.
Discriminator
- Standby current permanently rises + local warm spot → latch-up/leakage damage dominates.
- GPIO remains stuck high/low after event → input protection/return path issue dominates.
- Only near-phone failures with stable current → burst EMI coupling dominates.
First fix (minimal change)
- Clamp at the entry: TVS placed close to tip/buttons/contacts with shortest return to chassis/ground reference.
- Control return path: keep ESD surge return out of AFE reference and coupling loop return.
- Add series damping/filter only where needed (entry bandwidth limit), avoiding extra loop area.
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H2-12 — FAQs (Evidence-First, Pen-Side Only)
Each answer uses a consistent rule: capture two probes that discriminate the dominant bucket (mechanics, power/rail noise, link margin/window, or ESD/EMI injection). Content stays pen-side and avoids OS/driver/app explanations.
1) Battery drops fast while idle — which two current evidences first?
Idle drain is almost always either periodic wake/scanning (spiky current) or flat leakage (pull-ups, ESD parts, charger path). Separate the two before changing firmware or power domains.
Probe B: spike signature / wake log (regular bursts imply polling, IMU always-on, or GPIO chatter).
Regular spikes point to scan duty cycle and wake sources; high flat current points to leakage and always-on rails. See H2-8 for state design and H2-11 for the SOP flow.
2) Same pen behaves very differently across screens — compatibility or low link margin?
Treat this as a failure-rate matrix problem. Compatibility issues are usually screen-specific and stable; margin/noise issues worsen with charging, distance, or high-load states.
Probe B: coupling envelope/noise floor (or retry/CRC/sync-lost counters if available).
Screen-specific failure with stable conditions suggests timing/window mismatch; broad failure that tracks charging or load suggests rail noise and reduced margin. Use H2-6 link evidence and H2-11 discriminators.
3) Pressure is accurate at first, then drifts after writing — creep or AFE reference drift?
Two buckets dominate: mechanical creep/hysteresis (time-under-load effect) and AFE/reference sensitivity (drift that tracks rails or temperature).
Probe B: VREF or AFE rail ripple captured on the same time axis.
Drift that correlates with VREF/rail ripple points to AFE coupling; drift that follows hold time with stable rails points to creep/hysteresis. H2-3 details the pressure chain; H2-11 gives the SOP steps.
4) Tilt gets much noisier while charging or near a phone — IMU issue or power/EMI coupling?
If noise rises synchronously with charging or RF proximity, it is rarely pure IMU bias; it is usually rail/ground noise or burst EMI coupling into the sensor domain.
Probe B: charging ON/OFF (or phone near/far) correlation test under identical mechanics.
Synchronous correlation indicates injection paths and vulnerable nodes (H2-10). If no correlation but slow drift exists, inspect IMU bias/assembly alignment in H2-4.
5) Strokes become “broken” — low sampling rate or wake/frame loss? Which two counters/waveforms?
Broken lines come from either time-base gaps (sampling/jitter/CPU gating) or link-window losses (missed frames, retries, envelope holes). Prove which one dominates.
Probe B: coupling evidence (envelope holes / retry or sync-lost counters if available).
If sample intervals stretch or jitter spikes, focus on H2-7 latency and filtering windows; if envelope holes and retries align, focus on H2-6 link margin and timing windows.
6) First-stroke lag is large but continuous writing is fine — common wake/settle causes?
This pattern usually means the wake and settle path is expensive (PLL lock, AFE settle, domain ramp), while steady-state sampling is acceptable. Split “first-stroke” from “steady” before tuning filters.
Probe B: first-stroke delay vs steady-state delay (p50 + p95).
If wake dominates, optimize H2-8 state machine and staged enables; if both are slow, optimize H2-7 sampling/filter windows and budget.
7) Button double-triggers or false triggers — mechanical bounce or post-ESD GPIO abnormality?
Mechanical bounce creates clustered short-interval edges; ESD damage often shows stuck lines, abnormal leakage, or behavior changes after a zap. Evidence must be time-aligned and repeatable.
Probe B: ESD event correlation: GPIO stuck state and standby-current delta before/after.
Short-interval edge clusters suggest bounce/thresholding (H2-5). Persistent stuck states or standby-current shift suggests injection paths and protection layout issues (H2-10).
8) Charging is slow or hot — input-limited or battery impedance/protection triggered? Which status bits?
Slow/hot charging is typically thermal regulation/protection (OTP/OCP/OVP) or input limitation (contact resistance, alignment, or source limits). The charger’s state is the fastest discriminator.
Probe B: Icharge vs temperature vs time (step-down indicates thermal regulation).
Thermal-regulate flags with current step-down point to heating paths; unstable or low input current with intermittent behavior points to contacts/alignment. H2-9 stays pen-side (no adapter topology).
9) Winter/dry air causes more drops or jumps — how to pinpoint the ESD injection point?
Make “intermittent” measurable: lock conditions and quantify failure rate vs humidity/clothing/flooring. Then compare pre/post-event electrical signatures to locate the vulnerable node (tip, buttons, charge contacts, seams).
Probe B: before/after delta: standby current shift or one node waveform change (AFE ref ripple / coupling envelope / GPIO stuck).
Strong environment correlation points to ESD injection; permanent standby-current shift suggests leakage/damage. Use H2-10 node map and H2-11 SOP to isolate.
10) “Writing feels floaty” — pressure noise, tilt noise, or link jitter? How to capture all evidence at once?
Use a synchronized capture that separates input noise (pressure/tilt) from transport jitter (coupling envelope/window). Repeat the same stroke pattern several times and compare variance under identical conditions.
Probe B: repeatability metric (variance across 5 repeats, plus failure rate if gaps occur).
Stable envelope with noisy pressure/tilt points to sensor/rail/EMI; envelope fluctuation or frame loss points to link margin/window. Use H2-3/H2-4 for inputs and H2-6 for link evidence.
11) Standby is fine but random reboots happen — check UVLO first or peak transient current?
Random resets usually come from brownout/UVLO caused by transient current peaks, or from an event path (ESD/EMI) that triggers a reset without large droop. Prove droop-first vs reset-first.
Probe B: VBAT + core rail waveform around the reset (droop amplitude and timing).
Rail droop that precedes reset points to transient current and sequencing; no droop but frequent resets points to robustness and injection paths. Use H2-8 for power states and H2-11 for isolate steps.
12) Same hardware, different batches behave differently — assembly bias or component tolerance? How to design A/B evidence?
Batch variation is best separated by an A/B plan: mechanical geometry deltas (tip preload, magnet position, IMU mounting angle) vs electrical deltas (VREF noise, gain, RC tolerance, coupling amplitude). Correlate deltas to symptom variance.
Probe B: electrical checkpoints (VREF/AFE ripple, gain/offset codes, coupling envelope amplitude distribution).
If geometry explains variance, tighten assembly tolerances; if electrical metrics shift with symptoms, audit BOM tolerances and sensitive nodes. Use H2-2 architecture, H2-3 pressure chain, and H2-4 orientation chain.
