What this page solves

Module and cell monitoring boards sit directly on high-voltage battery modules, surrounded by long sense harnesses, switching transients and tight PCB area limits. Small mistakes in the way voltages, temperatures, balancing switches and isolated links are arranged often turn into millivolt errors, drifting readings and hard-to-debug stack failures in the field.

This page focuses on the hardware design of module-level BMU/CMU boards in ESS and EV packs: how to achieve high-precision cell voltage and temperature acquisition with delta-sigma or multi-channel ADCs, how to keep measurement bandwidth and phase usable across many cells, how to route isoSPI or similar daisy chains through noisy stacks, and how to prevent balancing switches from corrupting the very measurements they rely on.

The goal is to provide a practical checklist for module-board schematics. Engineers can use the framework on this page to define the BMU/CMU measurement chain, select suitable AFEs, ADCs, isolation devices and balancing elements, and review common error patterns before layout begins. Pack-level energy management, PCS control and station EMS topics are covered on other pages; the scope here stays strictly at the module board level.

BMU/CMU in the BMS hierarchy

A complete energy storage system usually separates responsibilities across several layers: cells and modules, module-level BMU/CMU boards, rack or pack BMS controllers, and site-level EMS or PCS units. The BMU/CMU layer sits directly above the cells, acting as the primary interface between raw electrochemistry and higher-level control, but it does not decide how the entire pack or site should be charged, discharged or dispatched.

Typical BMU/CMU duties include accurate cell voltage and temperature measurement, basic module-level protection such as over-voltage or under-voltage thresholds, execution of passive or simple active balancing and communication with other BMUs and the main pack BMS. The pack-level controller then aggregates data from multiple modules, runs state-of-charge and state-of-health algorithms and coordinates with PCS and EMS functions.

Different deployment styles are common. Some systems attach one BMU to each module carrying dozens of series cells. Others use smaller CMU devices that monitor a subset of cells and report into a local BMU. High-voltage stacks often rely on long isoSPI-style daisy chains linking many BMUs back to a single pack BMS. Higher-level EMS architectures and grid-facing communication are handled on separate pages; this section only defines how BMU/CMU hardware fits into the overall BMS hierarchy.

What this page solves

Module and cell monitoring boards sit directly on high-voltage battery modules, surrounded by long sense harnesses, switching transients and tight PCB area limits. Small mistakes in the way voltages, temperatures, balancing switches and isolated links are arranged often turn into millivolt errors, drifting readings and hard-to-debug stack failures in the field.

This page focuses on the hardware design of module-level BMU/CMU boards in ESS and EV packs: how to achieve high-precision cell voltage and temperature acquisition with delta-sigma or multi-channel ADCs, how to keep measurement bandwidth and phase usable across many cells, how to route isoSPI or similar daisy chains through noisy stacks, and how to prevent balancing switches from corrupting the very measurements they rely on.

The goal is to provide a practical checklist for module-board schematics. Engineers can use the framework on this page to define the BMU/CMU measurement chain, select suitable AFEs, ADCs, isolation devices and balancing elements, and review common error patterns before layout begins. Pack-level energy management, PCS control and station EMS topics are covered on other pages; the scope here stays strictly at the module board level.

BMU/CMU in the BMS hierarchy

A complete energy storage system usually separates responsibilities across several layers: cells and modules, module-level BMU/CMU boards, rack or pack BMS controllers, and site-level EMS or PCS units. The BMU/CMU layer sits directly above the cells, acting as the primary interface between raw electrochemistry and higher-level control, but it does not decide how the entire pack or site should be charged, discharged or dispatched.

Typical BMU/CMU duties include accurate cell voltage and temperature measurement, basic module-level protection such as over-voltage or under-voltage thresholds, execution of passive or simple active balancing and communication with other BMUs and the main pack BMS. The pack-level controller then aggregates data from multiple modules, runs state-of-charge and state-of-health algorithms and coordinates with PCS and EMS functions.

Different deployment styles are common. Some systems attach one BMU to each module carrying dozens of series cells. Others use smaller CMU devices that monitor a subset of cells and report into a local BMU. High-voltage stacks often rely on long isoSPI-style daisy chains linking many BMUs back to a single pack BMS. Higher-level EMS architectures and grid-facing communication are handled on separate pages; this section only defines how BMU/CMU hardware fits into the overall BMS hierarchy.

Cell voltage front-end & wiring: sense leads, filters and open-wire detection

Cell sense wiring and the front-end network between the stack and the BMU or CMU input often determine whether millivolt accuracy is achievable in practice. Each cell should be sensed with Kelvin-style connections that land as close as possible to the actual terminals, using a consistent sequence that matches the internal ordering of the AFE. Routing must avoid regions with fast dv/dt, large di/dt loops and strong magnetic fields, because long, high-impedance sense pairs act as antennas. Harness design, contact resistance and the way shields and drains are terminated all contribute directly to IR drops and noise pickup that show up as apparent cell imbalance.

The RC network in front of each measurement channel serves multiple roles: limiting surge current into the AFE, providing basic anti-alias filtering and defining the settling time before each conversion. Typical resistor and capacitor values should be chosen to attenuate switching noise from power stages without making the delta-sigma converter or multi-channel ADC miss dynamic events. Excessively large series resistance amplifies the impact of input bias currents and can create millivolt offsets, while large capacitance can slow step responses enough to distort fast charge or discharge transients. Selecting and placing these protection and filter elements with the converter’s oversampling ratio and filter response in mind is essential for a predictable error budget.

Robust open-wire detection and a clean measurement reference complete the front-end. Many BMS AFEs use internal excitation currents or switched resistors to create distinct voltage signatures when a sense lead is intact, broken, shorted to a neighboring cell or shorted to the pack positive rail. The BMU or CMU must be wired and configured so that these patterns can be detected reliably, with clear reporting back to the pack BMS. At the same time, the local measurement ground on the BMU board must be kept well-defined and coupled to pack ground only through the intended isolation and reference paths, rather than through accidental shield terminations or leakage across the PCB. This section focuses on module-level harness and front-end issues; system-wide DC bus and ground fault localization is covered elsewhere.

Temperature sensing network: multi-point monitoring and protection linkage

Thermal behavior across an ESS or EV module is rarely uniform. Cells near busbars, tabs and compression plates experience different heating than cells in the middle of the stack. Cold plates, manifolds and coolant lines add further gradients, while the BMU or CMU PCB and its power devices introduce their own hotspots. A robust temperature sensing network therefore places NTCs or RTDs at a mix of locations: cell tabs and mid-points, coolant inlet and outlet points and on-board components whose temperature correlates with long-term reliability or safety. The number and placement of sensors define how early emerging hot spots or thermal imbalances can be detected and reported.

Multi-point temperature measurements can be implemented with simple analog multiplexers feeding a shared ADC, multiple ADCs partitioned across different thermal zones or dedicated BMS AFEs that integrate temperature channels alongside cell voltages. Each approach has different implications for sampling rate, noise coupling and wiring complexity. Slow-moving thermal dynamics usually allow modest sampling rates, but oversubscription of a single ADC or poor channel grouping can still create blind spots or slow reaction at the hottest points. Careful grouping of sensors by thermal zone, combined with a clear understanding of the required response time for each protection limit, helps select an architecture that balances channel count and latency.

Protection thresholds should be layered. Local BMU hardware or firmware can enforce hard limits using fast comparators or dedicated temperature channels to ensure that extreme over-temperature events trigger an immediate response. Softer warning levels and long-term derating thresholds can be computed at the pack BMS level using filtered temperature data and models of cell aging or coolant flow. To prevent thermal measurements from being corrupted by balancing currents or switching noise, layout and sampling strategies must keep temperature networks away from high di/dt nodes, avoid measuring during the most aggressive balancing phases or rely on separate ADC resources. Control of fans, pumps and valves is handled on the Battery Thermal Management Controller page; this section concentrates on how the BMU or CMU acquires and forwards reliable temperature data and protection signals.

Balancing network: passive equalization and interfaces to active converters

Passive cell balancing on a BMU or CMU board is usually implemented with a resistor and switch across each cell. The value and power rating of these resistors set the available balancing current and dictate local heating on the PCB. For a given cell voltage, smaller resistor values shorten balance time but increase power dissipation and temperature rise, while larger values reduce thermal stress at the cost of slower equalization. Designs can place resistors close to each cell in a distributed scheme or group them in a centralized hot zone with enhanced copper area or heatsinking. The choice affects loop length, IR drops and how easily thermal hotspots can be managed within the module housing.

Balancing strategy is constrained by these hardware limits. The BMU must respect maximum allowed balancing current, MOSFET and driver capabilities and safe duty cycles for each channel. Because drawing current through a shunt resistor changes the observed cell voltage, measurement sequences and balancing timing must be aligned. Common approaches include pausing voltage conversions while a cell is being discharged, inserting short idle windows to capture unloaded cell voltages or applying compensation based on known resistor values and estimated current. Balancing actions are typically concentrated in periods when the pack is at rest or near the top of charge, where small deviations have the greatest impact on usable capacity and cell stress.

When an external active balancing converter is present, the BMU serves as the interface between precise cell measurements and energy-moving hardware. The BMU supplies voltage, temperature and status information that identifies candidate cells for charge removal or injection, and exposes enable, inhibit and mode pins or registers that control when the active converter is allowed to operate. In return, the active balancing module feeds back diagnostics such as fault flags, temperature and optionally estimated transferred charge. This section focuses on the passive balancing network and control signals at the BMU boundary; the internal DC-DC topology and energy transfer paths of active converters are covered on the dedicated Active Balancing Converter page.

Isolated communications and daisy-chain robustness

A high-voltage battery stack often contains multiple modules, each with a BMU or CMU board that must send measurements and status back to a central pack BMS. These boards sit at different potentials, so their communications links require galvanic isolation and strong immunity to common-mode disturbances. IsoSPI and transformer-coupled serial links provide one common approach, allowing an SPI-like interface to traverse the stack via small isolation transformers. Alternative schemes combine capacitive or magnetic digital isolators with UART or SPI signals. In all cases, the objective is to maintain reliable data transfer across long harness runs and large voltage differences without exposing the BMS controller to the full stack potential.

The communications channel must withstand ESD and surge events on cabinet wiring, as well as strong dv/dt and di/dt from inverters and contactors. Differential signaling, controlled-impedance routing, shielded twisted pairs and carefully placed protection components such as surge arresters or common-mode chokes all contribute to robustness. Daisy-chained architectures, where BMU nodes are connected in series, bring additional challenges: an open connector, failed board or broken transformer winding can interrupt traffic from all modules further up the stack. Many BMS AFEs therefore support bypass modes or dual-path topologies that allow the chain to be re-routed around a failed node, keeping the remainder of the stack visible to the pack controller.

Functional safety depends on more than just the physical layer. Each frame should carry CRC protection and sequence information so that corrupted or repeated messages are detected. Timeouts and heartbeat monitoring allow the pack BMS to identify loss of communication with one or more BMU boards and enter a controlled degradation mode, reducing power capability or commanding an orderly shutdown if coverage drops below the required level. These mechanisms operate between the stacked BMU boards and the central BMS controller; higher level station communications such as Ethernet, IEC 60870-5-104 or DNP3 are handled on an EMS or gateway controller and are outside the scope of this page.

Functional safety and diagnostics in BMU / CMU

BMU and CMU boards in traction and stationary energy storage systems contribute to safety goals under standards such as ISO 26262, IEC 61508 and IEC 62933 by providing trustworthy measurements and diagnostic information. Typical requirements include redundant or cross-checked sampling paths, self-test coverage for references, ladders and measurement front-ends, and integrity protection for stored parameters and communications. The measurement chain is periodically exercised using internal references, resistor ladders or injected test currents so that offset, gain and linearity errors can be detected before they grow beyond the allowed budget. Diagnostic results are captured as status bits and counters rather than left implicit in application software, allowing higher-level safety functions to make structured decisions.

Common fault modes include stuck ADC channels, reference drift, balancing switches that fail short and communications drop-outs. Stuck converters can be identified through conversion watchdogs, repeated identical results or inconsistencies with secondary comparators. Reference drift is revealed when periodic readings of known internal points fall outside a calibrated window. A balancing switch that no longer opens manifests as a cell that remains lower than neighbours even when balancing is disabled and often as local heating near the resistor bank. Loss of a BMU in a daisy-chain appears as missing data from a group of cells, heartbeat timeouts or a requirement to engage a bypass path if supported by the AFE. For each case, the BMU or CMU records which functions are no longer trustworthy so that the pack-level safety manager does not rely on compromised signals.

Integrity of configuration and communications is as important as analogue self-test. Thresholds, calibration coefficients and balancing limits stored in non-volatile memory are typically protected by checksums or CRCs, with power-on self-test routines that either confirm their validity or switch the BMU into a safe default configuration while reporting a fault. Serial links to the pack BMS use CRC-protected frames, rolling counters and heartbeat messages so that corrupted commands are rejected and missing updates are detected within a bounded time. The BMU exposes its diagnostic results through structured status words and error counters, enabling the pack BMS and higher-level safety logic to implement system-level strategies such as derating, controlled shutdown or maintenance requests. System-level safety goals, ASIL or SIL allocation and FMEA remain the scope of the Battery Systems & Safety or pack BMS pages; this section concentrates on what the BMU or CMU can detect and report.

Mini design stories: BMU and CMU implementation examples

48 V telecom and UPS module BMU

A 48 V telecom or UPS module usually contains a relatively small number of series cells but is expected to operate for many years with minimal drift. The BMU tends to be built around a multi-channel delta-sigma AFE that integrates cell-voltage and temperature measurement, an internal reference and support for passive balancing. Long-term stability and EMI robustness are more critical than extreme isolation ratings. The design often uses a compact isolated SPI or UART link to a local pack controller, with careful filtering and layout to reject noise from rectifiers and inverters while still resolving millivolt differences between cells.

Diagnostic coverage focuses on reference and ADC self-tests, open-wire detection and monitoring of balancing resistor temperature. The BMU exports a clean set of voltage, temperature and health flags to the pack BMS, which in turn coordinates multiple parallel modules and commands cooling fans or room-level HVAC. The combination of an integrated AFE, modest isolation and structured diagnostics provides high availability over long service intervals without imposing excessive cost on each module.

1500 V utility-scale ESS module BMU

A utility-scale ESS string operating up to 1500 V is composed of many stacked modules, each with a BMU that must withstand harsh surge and EMI conditions. Here the BMU typically uses a specialised high-voltage BMS AFE with integrated isoSPI or transformer-coupled serial links so that multiple boards can be daisychained along the stack. The AFE offers open-wire detection, internal reference and ladder-based self-tests, and native drivers for passive balancing networks. Cabling and connectors are designed for long runs inside cabinets exposed to switching transients from bidirectional PCS and grid-side equipment.

The pack BMS polls each BMU over the isolated chain, using CRC-protected frames and heartbeat monitoring to detect missing or corrupted data. Daisy-chain bypass features allow sections of the stack to remain visible even when a board fails, and BMU diagnostics distinguish between local measurement faults and communication problems. Temperature and cell data feed into pack-level safety logic and into a separate thermal controller that manages liquid cooling. This combination addresses high-voltage, high-stack-count challenges while keeping module-level BMU hardware focused on measurement, balancing and reporting.

800 V EV pack sub-module CMU

In an 800 V electric vehicle traction pack, space constraints and functional safety targets push CMU designs toward high integration. Each sub-module carries a compact CMU board that often combines a dense BMS AFE, a microcontroller and isolated communications within a small footprint. The AFE provides cell-voltage and temperature channels, passive balancing drivers and built-in diagnostics, while the microcontroller can add a second sampling path or consistency checks to support ASIL C or ASIL D allocations. Mechanical design must tolerate vibration, thermal cycling and limited airflow around the module.

Communications to the central vehicle BMS frequently use isolated CAN FD or a robust isoSPI chain, with CRC and frame counters ensuring that traction and charging decisions are based on consistent data. The CMU shares condensed health and temperature information with the pack BMS and with a dedicated thermal controller ECU that manages cold plates, heat pumps and cabin conditioning. This arrangement allows each sub-module to implement the measurement, balancing and diagnostic concepts described across this page while still fitting into the tight packaging envelope of an automotive battery pack.

Design checklist and IC mapping for BMU / CMU

This section provides a schematic review checklist for BMU or CMU module boards and maps each group of items to typical IC roles and example part numbers. It focuses strictly on circuitry located on the module or cell monitoring board: voltage and temperature front-ends, balancing hardware, isolated communications and local diagnostics. Pack BMS, PCS, EMS or gateway controllers are outside the scope of this checklist.

Voltage measurement checklist

• A suitable BMS AFE or multi-channel ADC architecture is selected for the required number of series cells (dedicated multi-cell monitor AFE versus generic delta-sigma ADC plus external MUX).
• Open-wire detection covers all cell sense lines, either through built-in test current and switching inside the AFE or via a discrete injection and switching network.
• Each cell sensing path includes RC filtering and ESD or surge protection sized to suppress switching noise without excessively limiting the effective bandwidth of the delta-sigma ADC.
• Target cell voltage accuracy and long-term drift limits are defined, and an error budget is closed across AFE INL and gain error, reference tolerance and drift, divider resistor tolerances and leakage paths.
• The reference voltage source and its self-test path are defined, including the ability to route an internal or external reference node into at least one ADC channel for periodic verification.
• Cell refresh rate requirements are established and checked against the chosen oversampling ratio, filter bandwidth and channel count of the delta-sigma front-end.
• Common-mode range, CMRR and creepage / clearance rules are satisfied for the intended stack voltage and insulation coordination level.
• Calibration or production test injection points exist, such as headers or DAC-driven nodes, to exercise the measurement chain with known voltages.

Temperature measurement checklist

• The topology and excitation for NTC or RTD sensing are defined (pull-up versus pull-down, constant-current source versus divider) and compatible with available AFE or ADC inputs.
• Sufficient temperature points cover cell tabs or mid-points, coolant inlet and outlet locations and electronic hotspots on the BMU or CMU PCB.
• Resolution and accuracy targets are set for temperature channels, and ADC resolution, sensor tolerance and linearisation errors are checked against these limits.
• Local hard limits for over-temperature are implemented (for example, comparator or temperature switch near balancing resistors), with softer warning thresholds reported upstream to pack BMS or thermal controllers.
• Multiplexing and sampling sequences ensure temperature acquisition does not compromise required voltage refresh rates or diagnostic timing.
• Sensors are placed close enough to self-heating components such as balancing resistors, isoSPI transformers, digital isolators and power FETs to detect local hotspots.
• At least one relatively stable reference temperature point is monitored to help distinguish sensor drift from genuine environmental changes over life.

Balancing network checklist

• Target balancing current per cell is calculated, and corresponding resistor values and power ratings are chosen with adequate thermal margin for worst-case duty.
• Placement of balancing resistors is decided (centralised hot zone versus distributed near each cell tap) with attention to current loop length, IR drops and board-level thermal management.
• Measurement strategy during balancing is defined, including any pause windows, compensation methods or separate sampling phases for high-accuracy readings.
• Interfaces to any external active balancing converter are defined, such as enable, mode and fault pins or register fields and any required sense or handshake lines.

Communications and isolation checklist

• The physical layer and topology between BMU or CMU and pack BMS are defined (isoSPI, transformer-coupled SPI, isolated UART or isolated CAN FD, daisy-chain versus star).
• Connectors, cabling and board entries incorporate appropriate ESD and surge protection components and, where needed, common-mode chokes and controlled-impedance routing.
• Frame formats include CRC protection, frame counters and heartbeat or timeout mechanisms so that corrupted or missing messages are detected within a bounded time.
• For multi-board stacks, daisy-chain bypass or redundant paths are defined so that a single failed node or link does not blind the entire stack.

Diagnostics and logging checklist

• Diagnostic coverage is defined for key measurement, balancing and communications paths, including which fault modes each self-test or monitor can detect.
• BMU or CMU firmware exposes fault and degradation information in structured status words or registers that the pack BMS can read and log.
• Event and fault logging includes time information, either from a local RTC or from time stamps synchronised by the pack BMS, so that intermittent issues can be correlated with operating conditions.
• Behaviour in local degradation modes is specified: which measurements are no longer considered trustworthy, which functions such as balancing are disabled and which minimal information is still provided to the pack controller.

IC roles and example part numbers for BMU / CMU designs

The following IC roles and example part numbers illustrate typical choices for BMU or CMU implementations. Listings are indicative only and intended as starting points for detailed selection. Devices for PCS, EMS or gateway controllers are deliberately excluded.

• BMS AFE / multi-cell monitor ICs
  Role: multi-cell voltage and temperature measurement, open-wire detection, passive balancing drivers, often with isoSPI or similar stack communications.
  Example families: TI BQ76PL455A, BQ79616; ADI LTC6811-2, LTC6813-1; NXP MC33771 / MC33772.
• Delta-sigma and multi-channel precision ADCs
  Role: high-resolution cell or sense measurements where a generic ADC is preferred over a dedicated BMS AFE, often paired with external multiplexers.
  Example families: TI ADS131A04 / ADS131A08, ADS127L11; ADI AD7768, LTC248x series.
• Isolated communications and digital isolators
  Role: galvanically isolated links between BMU or CMU and pack BMS, including isoSPI chains, isolated SPI or UART and isolated CAN FD.
  Example families: ADI isoSPI interfaces integrated in LTC681x devices; digital isolators such as ADuM141D / ADuM125x, Skyworks Si86xx series; isolated CAN FD transceivers such as TI TCAN1042-Q1 / TCAN1145-Q1.
• Balancing MOSFET arrays and load switches
  Role: switching paths for passive cell balancing resistors or simple active balancing interfaces at the BMU edge.
  Example families: small-signal MOSFET arrays such as AOZ88xx, Diodes Incorporated DMNxxx series; dedicated active balancing controllers such as ADI LTC3300-1 for use on the Active Balancing Converter page.
• Precision voltage references and resistor networks
  Role: establishing stable reference voltages and accurate divider ratios for voltage measurement and self-test ladders where external components are required.
  Example families: ADI ADR4550, LTC6655; TI REF5025 / REF5050; thin-film resistor networks such as Vishay ACAS / ACAT and similar 0.1 % or 0.5 % arrays.
• Temperature sensors and interfaces
  Role: NTC-based sensing at cells, cold plates and hotspots, and in some designs RTD interfacing for higher accuracy locations.
  Example families: automotive or industrial NTC series from Vishay, TDK and Murata; RTD front-ends such as MAX31865 when RTDs are used on selected points.
• Local RTC and non-volatile logging memory
  Role: time stamping diagnostic events and storing compact fault histories on the BMU or CMU board.
  Example families: low-power RTCs such as Micro Crystal RV-3028-C7 or NXP PCF85063A; SPI Flash or EEPROM families such as 25xx and 24xx series from multiple vendors.
• Supervisors and supply protection for BMU / CMU
  Role: monitoring local supply rails and enforcing brown-out behaviour so that diagnostics are meaningful and balancing or communications hardware does not operate with undefined logic levels.
  Example families: TI TPS37x / TPS38x supervisors; ADI ADM83x supervisors; integrated eFuses or high-side switches such as TPS2594x for local supply protection.

Frequently asked questions about BMU / CMU design

These questions summarise common decisions and trade-offs when designing module or cell monitoring units. Each answer points back to the sections on measurement fundamentals, wiring, balancing, isolated communications, functional safety and the design checklist so that the underlying reasoning can be reviewed in more detail.