What this microgrid islanding and resynchronization interface solves

At the point of common coupling (PCC), a microgrid needs more than a generic protection relay or a PCS firmware option. A dedicated islanding and resynchronization interface provides the measurement chain and control logic that decide when to leave the utility grid, how to stay safely islanded, and when it is safe to reclose.

This page focuses on the interface layer between utility, protection, PCS and microgrid controller, viewed from a distribution / microgrid engineer’s perspective:

• During grid-connected operation, the interface monitors voltage, frequency and phase at the PCC to detect abnormal conditions and initiate controlled islanding.
• While the microgrid runs islanded, the interface maintains awareness of PCC conditions and coordinates with PCS and protection so that no unsafe reclosing can occur.
• After grid restoration, the interface evaluates phase, voltage and frequency differences and only permits reclosing when synchronization criteria and interlocks are satisfied.

To keep the scope tight and avoid overlap with other pages, this topic does not try to be a full microgrid design guide:

• Not covered: PCS / ESS power-stage topologies, modulation and filter design; these belong to dedicated PCS and hybrid inverter pages.
• Not covered: full microgrid controller logic, economic dispatch and long-horizon load optimization; these are handled by ESS EMS and microgrid controller topics.
• Not covered: complete HV protection coordination and grading across feeders; those details live in protection relay and switchgear content.

Instead, the page concentrates on measurement and decision chains and how they map to IC roles: islanding detection AFEs and ADCs, isolation and digital inputs, fast comparators, MCU or FPGA control, and precise timing sources for event logging.

The figure below shows the high-level position of the microgrid islanding and resynchronization interface between utility grid, PCC breaker and microgrid / ESS, with the three core internal blocks that the rest of the page will explore.

Scope, boundaries and interfaces at the PCC

The microgrid islanding and resynchronization interface sits between utility, protection, PCS and high-level control. It receives raw measurements and status from the grid side, makes decisions based on local criteria and system commands, and then drives breakers, PCS enable inputs and load shedding paths.

Understanding its upstream and downstream interfaces helps to keep responsibilities clean and avoid overlap with PCS, protection relay and ESS EMS functions.

Upstream inputs: what the interface observes

• PT / CT measurement paths: voltage transformers and current transformers at the PCC feed differential AFEs, isolated amplifiers or ΣΔ modulators and ADCs, providing the waveforms needed for voltage, frequency, phase angle and power calculations.
• PCS and inverter status: run mode, ready-for-sync flags and fault states from PCS or string inverters act as additional inputs when deciding whether islanding or reconnection are allowed.
• Protection relay and switchgear feedback: trip indications, close blocks, breaker position (open/closed) and spring charged status ensure that reclosing commands are only issued when the breaker is truly ready and no protection action is in progress.
• SCADA / EMS / microgrid controller commands: high-level policies such as “islanding allowed”, “reclosing disabled” or “preferred source” arrive over Ethernet or serial links and constrain what local logic is permitted to do.

Downstream outputs: what the interface controls

• PCC breaker trip and close coils: isolated drivers or relay outputs energize trip and close coils according to islanding and resync decisions, with interlocks to prevent unsafe or rapid-fire reclosing.
• PCS / inverter enable and mode inputs: digital outputs and communication messages instruct PCS to ramp down, switch to island mode, track phase for resync or block reconnection when criteria are not met.
• Load shedding and microgrid reconfiguration: optional outputs towards load controllers or downstream breakers support fast disconnection of non-critical feeders during islanding, while leaving detailed shedding policy to the EMS or microgrid controller.

Typical PCC topologies and where the interface fits

• Single-PCC radial microgrid: a single breaker separates utility from a local bus that carries PCS, PV inverters and loads. The interface supervises this one PCC and coordinates PCS and load shedding for that bus.
• Multiple DER / ESS on a shared bus: several PCS, PV and gensets connect to the same PCC. The interface broadcasts status and commands to multiple units and must support more I/O and protocol endpoints without taking over full dispatch logic.
• ATS and bypass arrangements: automatic transfer switches can connect the microgrid to alternative sources. The interface still supervises the PCC but also considers additional source presence and guarantees that only a safe path is ever closed.

Detailed economic dispatch, long-term forecasting and feeder-level protection grading remain outside this page and are handled by ESS EMS, microgrid controller and protection relay topics. Here the concern is the clean definition of measurement inputs, control outputs and communication links that ICs must support at the islanding and resynchronization interface.

Islanding phenomena and detection requirements

Islanding and resynchronization decisions are driven by how voltage, frequency and phase behave at the point of common coupling. Understanding the key phenomena helps define realistic requirements for measurement bandwidth, accuracy and timing instead of relying only on abstract standards tables.

Typical grid-side phenomena around islanding

• Voltage sags and interruptions: faults or switching events upstream can cause deep sags or complete loss of PCC voltage. The interface must distinguish brief, tolerable dips from sustained abnormal conditions that require islanding.
• Frequency drift and ROCOF: when the upstream system becomes weak or unstable, PCC frequency may slowly drift or change rapidly. The rate-of-change of frequency is often more telling than instantaneous frequency and drives requirements on sampling rate and time-base stability.
• Phase jumps and vector shift: reclosing, line switching or fault clearance can produce sudden changes in voltage phase. Islanding schemes that rely on vector shift need coherent three-phase measurements and controlled latency through the AFE and ADC chain.
• Asymmetrical and ground faults: single-phase-to-ground and unbalanced faults introduce negative- and zero-sequence components, voltage unbalance and additional harmonics. Zero-sequence current and voltage channels can help avoid blind spots in islanding detection.

Consequences of misdetection and unsynchronized reclosing

• False islanding: tripping away from a healthy grid transfers all support to local DER and ESS. Poor discrimination between transient disturbances and true faults can lead to unnecessary island operation and stress on local resources.
• Failure to island: remaining connected to a collapsing or heavily disturbed grid can cause wide voltage swings, equipment trips and non-compliance with grid-code disconnect times.
• Unsynchronized reclosing: reclosing with excessive phase, frequency or voltage mismatch effectively forces two sources together. The resulting inrush, torque shocks and voltage jumps can damage motors, transformers and power electronic equipment.
• Overly conservative reclosing: keeping the microgrid islanded long after the grid has recovered wastes capacity and may degrade power quality. Practical sync windows are required, not just theoretical limits.

From grid-code windows to measurement-chain targets

Interconnection and microgrid standards usually define time windows and thresholds for disconnection and reconnection. Typical patterns include:

• Maximum allowed time to detect and disconnect after a voltage or frequency limit is violated.
• Distinct regions for shallow sags or small frequency deviations where remaining connected is permitted.
• Upper limits on phase angle, voltage magnitude and frequency error before reclosing at the PCC is allowed.

For the islanding and resynchronization interface, these rules translate into concrete requirements on the measurement chain rather than full standards tables:

• Sampling rates and filter windows must be fast enough to identify abnormal behaviour before disconnect deadlines expire.
• Voltage and frequency resolution must support reliable operation around thresholds, separating acceptable disturbances from violations.
• Time-stamping and event logging need adequate accuracy to show that trips and reclosing actions were taken within required windows.

Measurement-chain implications for ICs

• Bandwidth and sampling rate: AFEs and ADCs must cover the fundamental and relevant harmonics with sampling rates high enough to estimate voltage, frequency, ROCOF and vector shift over a few cycles.
• Resolution and dynamic range: the measurement chain must handle deep sags and overvoltages while still resolving a few percent changes around nominal levels.
• Phase and channel alignment: accurate phase angle, power direction and unbalance assessment requires well-matched channels and predictable latency through AFE and ADC paths.
• Time-base and timestamp quality: stable oscillators and RTCs are needed so that ROCOF and event logs reflect real timing and can be aligned with SCADA or PMU data.
• Single-phase, three-phase and zero-sequence coverage: support for three-phase measurements plus zero-sequence current or voltage improves detection of asymmetrical and ground faults.

Islanding detection AFEs and measurement chains

Reliable islanding detection depends on how PT and CT signals are brought into the digital domain. The choice of AFEs, ADCs, isolation and timing architecture determines whether voltage, current, frequency and phase can be measured with the speed and accuracy that grid codes and microgrid stability demand.

Voltage, frequency and phase measurement from PTs to digital

• PT outputs and scaling: primary voltages are translated by PTs to standardized secondary levels. Simple resistance dividers and anti-alias filters then shape the signal into the input range of differential AFEs or isolation amplifiers.
• AFE selection: instrumentation amplifiers, high-voltage differential amplifiers and isolated amplifiers or ΣΔ modulators are used to condition three-phase voltages. Key parameters include common-mode range, gain accuracy, linearity, drift and surge withstand capability.
• ADC and ΣΔ converters: multi-channel SAR ADCs or multi-bit / single-bit ΣΔ modulators feed the controller with synchronized samples. Suitable sampling rates support RMS, frequency, ROCOF and vector shift calculations over several cycles.
• Channel matching and latency: phase angle and power direction estimations rely on closely matched channels and predictable latency through the AFE and ADC path so that three-phase signals remain coherent.

Power, ROCOF and vector shift estimation support

• Active and reactive power direction: three-phase voltage and current samples with aligned timing allow the controller or FPGA to compute power and its direction, supporting detection of abnormal power flow patterns during grid disturbances.
• ROCOF: accurate rate-of-change-of-frequency estimates require a stable time base and sufficiently dense samples over several cycles. This drives oscillator quality and ADC sampling strategies.
• Vector shift: detecting sudden phase-angle steps relies on coherent phase estimation before and after events. AFE and ADC designs with low jitter and deterministic group delay help avoid false indications.

Auxiliary inputs: zero-sequence, breaker status and interlocks

• Zero-sequence channels: residual current from a zero-sequence CT or derived measurements provides additional sensitivity to ground faults and asymmetrical conditions, complementing phase voltage and current.
• Breaker position and mechanism status: auxiliary contacts indicating open or closed state and spring charged status are brought in through digital input ICs and digital isolators, ensuring that trip and reclose commands are based on the real mechanical state.
• Interlocks and trip-permit signals: protection relays, safety circuits and manual selectors provide discrete “allow” or “block” inputs. Robust isolated digital inputs filter noise and provide clean logic levels to the islanding and resync controller.

In some architectures, the interface also consumes phasor or synchrophasor data from a dedicated PMU. In such cases, the local AFEs and ADCs may be simplified, but the need to align time bases and event logs with external measurements remains. Detailed PMU architectures are treated in dedicated synchrophasor content; this page focuses on the local measurement chain at the PCC interface.

Phase re-match and reclosing control chain

Once islanding has occurred and the microgrid is running in island mode, the islanding and resynchronization interface must coordinate how and when to reconnect to the utility grid. This section links measurement results to the reclosing action through a controlled sequence of sync checks, interlocks and limited reclose attempts.

From island operation to synchronized reconnection

• Islanded state: the PCC breaker remains open while the microgrid operates as an autonomous island. PCS and local controllers regulate voltage and frequency for local loads, and the interface tracks both microgrid and utility-side conditions.
• Grid restoration and sync arming: when the upstream grid recovers and protection or EMS remove block-close conditions, the interface enters a synchronization-arming state. In this state it begins actively checking if both sides can be safely reconnected.
• Continuous phase re-match monitoring: the interface monitors the differences in voltage magnitude, frequency and phase angle between the microgrid and the utility side at the PCC. PCS usually adjusts its outputs to follow the grid so that these differences shrink into a defined sync window.
• Entering the sync window: when ΔV, Δf and Δφ are all within configured limits for a minimum dwell time, the interface considers the electrical conditions acceptable for reclosing and transitions to a “ready to reclose” state.
• Close pulse and post-close verification: after all interlocks are satisfied, the interface issues a timed close command to the breaker coil. Immediately after closing, it checks that voltage and frequency remain within allowed limits; if severe deviation appears, it can force a rapid trip or raise alarms.

Reclosing logic, interlocks and attempt limits

• Soft and hard interlocks: phase, voltage and frequency windows are only one part of the decision. Breaker mechanism readiness, PCS readiness, protection relay close-permit and EMS or remote commands must all agree before a close command is allowed to reach the coil.
• Dead time between attempts: between reclosing attempts, a configurable dead time allows transients to decay and mechanical components to cool down, and ensures that measurements reflect steady conditions rather than momentary disturbances.
• Reclose attempt counters: the interface maintains a counter of attempted recloses within a time window. If several attempts fail, the interface moves into a lockout state and requires operator or EMS action before further attempts are possible.
• State-machine behaviour: implementations typically follow a clear state sequence such as “Islanded → Sync arming → In sync window → Close pulse → Verified connected or Reclose lockout”. This makes behaviour easier to verify and to audit.

IC roles in phase comparison and breaker actuation

• Phase comparison and sync circuits: zero-crossing comparators, time-to-digital converters, FPGA counters or MCU timers can measure phase and frequency differences based on PT signals or digitised waveforms from the AFEs and ADCs. Surge-tolerant inputs and adequate timing resolution are essential.
• Reclose decision engine: the MCU or FPGA implements the synchronization window checks, state-machine logic, attempt counters and dead-time timers using the phase and voltage estimates from the measurement chain.
• Breaker coil drivers: isolated gate or high-side drivers, solid-state relay drivers or relay-driving ICs provide the actual close pulse to breaker coils. Designs may use redundant channels with mutual monitoring to meet reliability and safety objectives.
• Diagnostics and feedback: drivers and digital inputs feed back coil current, open-circuit and short-circuit conditions so that the interface can detect failed close attempts and record detailed event logs.

Detailed feeder and busbar protection coordination, multi-shot auto-reclose schemes and protection setting philosophy are handled by dedicated protection relay and breaker control topics. This section focuses on the islanding interface view of phase re-match, interlocks and controlled reclosing at the PCC.

Protection coordination and interlocks

At the PCC, the islanding and resynchronization interface shares control authority with protection relays, EMS and local operators. Protection coordination and interlock logic define who can trip the breaker, who can block reclosing and under which combined conditions a close command may actually energise the coil.

Typical interlock paths around the PCC breaker

• Protection relay trip path: line and transformer protections can trip the breaker directly, often through an independent hardwired circuit. The islanding interface must respect this highest-priority path and treat active protection trips as a strong block against reclosing.
• Islanding interface trip and block: based on islanding, sync-condition and fault detection, the interface can issue its own trip or close-block signals. These may be wired in parallel with protection outputs or routed through an interposing relay.
• EMS and remote-control path: EMS, SCADA or a microgrid controller can command “block close”, “enable reclose” or “force open” through communications. The interface uses these commands as high-level interlock inputs.
• Local panel and key-switch path: local selector switches, key switches and mechanical locks can place the bay in local, remote or blocked mode. From the interface perspective, these are discrete inputs that influence whether automatic reclosing is allowed.

Allowing and blocking close: interlock logic concepts

The core idea is that close commands from the reclosing state machine are only honoured when an “allow” logic expression is true and a complementary “block” expression is false.

• Conditions that must be true (AND chain): protection relay close-permit, breaker mechanism ready, PCS ready for sync or grid-connection mode, EMS allowing reclosing, local key switch in automatic position and interface self-check OK are typical members of the allow set.
• Conditions that immediately block (OR chain): active protection trips, interface trips or abnormal sync, open safety circuits, EMS block-close commands and reclose lockout states each block a close attempt even if all allow conditions are otherwise satisfied.
• Final coil command: the driver only energises the close coil if a valid close command is present, the allow logic evaluates to true and the block logic remains false. This separation helps avoid inadvertent energisation due to a single misbehaving input.

IC roles for safe inputs, outputs and supervision

• Safety-rated digital inputs: digital input ICs and isolated receivers capture status from protection relays, key switches, selector switches and safety circuits. Wide input ranges, surge robustness and robust filtering reduce the risk of false transitions.
• Redundant relay and coil drivers: dual-channel relay drivers or solid-state outputs with feedback support separate control paths and cross-monitoring, allowing fail-safe behaviour if a single channel fails.
• Dual-channel MCUs and safety monitors: a primary controller executes the full interlock and reclosing logic, while a secondary safety MCU or monitor checks outputs against simple rules and can cut off the coil drive if unexpected combinations occur.
• Event logging and diagnostics: mapping each interlock input to a dedicated bit in event logs provides visibility into why a close command was blocked and supports post-event analysis and compliance documentation.

Many projects require that such interlock architectures satisfy formal functional safety requirements and SIL targets. This section highlights the signal and IC roles; detailed safety-standard mapping and certification topics are treated in dedicated functional safety and safety PLC content.

Event logging and SCADA/EMS notifications

The islanding and resynchronization interface is not only a real-time decision engine. It also acts as a recorder that documents what happened, when it happened and why it happened. Well-structured event logging with reliable time-stamping and SCADA/EMS reporting is essential for root-cause analysis, compliance and continuous improvement of microgrid and distribution protection schemes.

What needs to be recorded along the islanding timeline

• Potential islanding detections: when voltage, frequency, ROCOF or vector-shift indicators approach trip thresholds, the interface logs “potential island” events with timestamps, measured values and operating mode (grid-tied or islanded).
• Islanding trip actions: for each actual trip, the log captures which device initiated the trip (protection relay, interface, EMS command), the cause code and snapshots of V/f/phase before and after the action.
• Reclosing attempts and outcomes: every phase re-match and close attempt is recorded with attempt index, sync-window conditions (ΔV, Δf, Δφ), interlock status and the final result such as sync-close success, rejected close or failed close due to a driver or coil problem.
• Interlock assertions and releases: changes in block-close and close-permit signals are logged with an indication of which input caused the change, for example a new protection trip, EMS block command or safety circuit opening.
• Setting and configuration changes: updates to sync windows, reclose limits, dead times and communication parameters are recorded with old and new values, the source of the change and a timestamp.

Logging these events makes it possible to reconstruct the sequence of operations across multiple bays and devices and to explain exactly how the interface behaved during disturbances.

Event record structure and time-stamping requirements

Each event record should follow a consistent structure so that SCADA, EMS and analysis tools can interpret it reliably over the life of the system.

• Timestamp: absolute time (for example UTC with seconds and milliseconds) combined with an optional sequence counter provides ordering and correlation with other devices and PMUs.
• Event type and source: each record carries a type code such as potential island, islanding trip, sync-window entry, reclose attempt, reclose success, reclose failure, block-close asserted or setting changed, plus an identifier for the originating module.
• Key measurement snapshots: relevant values such as three-phase voltage, frequency, ROCOF, phase-angle difference and power direction at the time of the event are included so that behaviour can be reanalysed later.
• Status and quality flags: indicators describe time-sync quality (for example PTP locked or free-running), degraded measurement modes and any known channel failures.

The required timestamp accuracy depends on regulatory and coordination needs but generally must support proving trip response within specified windows and aligning events across bays and substations.

Time base, synchronization and holdover

• Local time base: a stable RTC and crystal or oscillator provide the underlying time base for the interface. Supercapacitor or small-battery backup avoids losing time across short power interruptions.
• External time synchronization: time alignment normally comes from station time through PTP, GPS, IRIG-B or similar sources. Ethernet PHYs with hardware timestamping or dedicated PTP clock ICs help achieve sub-millisecond accuracy.
• Holdover performance: when the time reference goes away, the interface operates in holdover mode. Oscillator stability then determines how long timestamps remain within acceptable error until synchronization returns.

Detailed oscillator design, PTP profile selection and PMU alignment techniques belong in dedicated precision timing and synchrophasor material. Here the focus is on why reliable time-stamping is essential for the islanding interface itself.

Event buffers, non-volatile storage and power-down behaviour

• Retention strategy: the design defines how many events or how many days of history must be retained. Ring-buffer structures allow new entries to overwrite the oldest while preserving recent events.
• FRAM and NOR Flash choices: FRAM is well suited to frequent small writes with virtually unlimited endurance, while SPI NOR Flash offers higher capacity for longer histories and bulk uploads at the cost of erase/program cycles and page organisation.
• Power-down management: brownout detection and short-duration holdup on the control supply give the MCU time to flush in-RAM event queues into non-volatile memory before the device turns off.
• Indexing and recovery: simple metadata or index blocks help the interface rebuild event chains quickly after a restart and detect any partially written records.

SCADA/EMS reporting and secure communication

• Station-level interfaces: the interface typically exposes event data to bay controllers or station gateways using protocols such as IEC 61850, DNP3 or Modbus over industrial Ethernet or serial links.
• Control center and cloud links: station gateways forward islanding-related events to control centers or cloud platforms using secure protocols such as TLS-protected TCP, MQTT or HTTPS, often with filtering and aggregation.
• Reporting strategy: critical events such as trips and failed sync-close attempts are pushed immediately, while less urgent statistics and counters can be uploaded in batches to reduce bandwidth and processing load.
• Security and integrity: secure MCUs, crypto accelerators and secure elements protect keys and implement encryption, authentication and integrity checks to align with utility cybersecurity requirements.

Design checklist and IC role mapping

Use this checklist to review a microgrid islanding and resynchronization interface design before hardware freeze. Each group links back to the sections where assumptions, performance targets and trade-offs are discussed in more detail, and the IC mapping table highlights typical device categories and example part numbers for key functions.

System boundary and measurement scope

• Voltage level at the PCC, network topology (radial, ring, meshed) and earthing scheme are clearly defined and reflected in PT/CT selection.
• PT and CT types, ratios, burden and accuracy classes are selected and documented for the islanding interface inputs.
• Measured quantities at the interface are specified: three-phase voltage, three-phase current, zero-sequence quantities, power direction and any additional PMU or synchrophasor inputs.

Detection targets and performance requirements

• Required detection quantities are listed: voltage, frequency, ROCOF, phase-angle difference, vector shift and power direction as applicable.
• Accuracy, response time and detection-window length are defined for each function, consistent with relevant interconnection standards.
• Channel matching and synchronicity requirements are defined for phase and power-direction calculations.

Reclosing strategy and sync window definition

• Sync windows for voltage magnitude, frequency and phase-angle difference are specified, including tolerances and dwell times.
• Reclosing strategy is chosen: fully automatic, single-shot automatic plus manual, or manual-only, with clear requirements for operator confirmation and EMS supervision.
• Maximum number of reclose attempts, dead time between attempts and lockout conditions are documented.

Protection coordination and interlock architecture

• Devices with trip authority at the PCC are identified, including line and transformer relays, the islanding interface, EMS commands and local manual actions.
• Close-permit logic is defined as an AND combination of required inputs such as relay close-permit, breaker ready, PCS ready, EMS allow, local key switch position and interface self-check.
• Block-close logic is defined as an OR combination of blocking inputs such as active trips, abnormal sync, open safety circuits, EMS block-close and lockout states.
• Functional-safety and SIL targets are assigned and cascaded into redundancy, diagnostics and safe-state requirements for the interface outputs.

Time, event logging and reporting

• Time-stamp accuracy requirements are set, along with the primary time source (station PTP, GPS, IRIG-B or other).
• Event types to be logged are enumerated, including potential islanding, trips, reclose attempts and outcomes, interlock changes and setting changes.
• Retention policy is defined in terms of the number of events or days of history and whether ring-buffer overwriting is acceptable.
• Reporting protocols (IEC 61850, DNP3, Modbus, MQTT, HTTP or others) and station gateway interfaces are specified, together with cybersecurity requirements.

IC role mapping for key design decisions

The table below links typical design considerations to IC categories and example devices that are frequently used in microgrid islanding and resynchronization interfaces. Part numbers are illustrative and can be substituted with equivalents that meet project-specific and vendor-preference constraints.

Selecting specific devices within each category depends on utility standards, preferred vendors, temperature and isolation ratings and integration into broader ESS, microgrid and substation designs. The structure above helps map functional requirements from the islanding interface directly to IC roles and candidate families.

Frequently asked questions about microgrid islanding and resynchronization

This FAQ collects common design questions around when a dedicated islanding interface is needed, how detection methods compare, how protection and reclosing are coordinated and what time-synchronization and event-logging requirements matter in real projects.