What this page solves

This page organizes the core design decisions inside a string or micro inverter that connects rooftop or small commercial PV to the AC grid, with or without a battery behind it. The focus is on the power stage itself: high-voltage switches, gate drivers, sensing chains, synchronous rectification and EMI monitoring.

The content helps compare string and micro inverter architectures in terms of safety, efficiency and service: which topology suits per-module shutdown, how many gate drivers and sensing channels are required, and how fault isolation changes when moving from a central string inverter to distributed micro inverters.

It also brings together the high-voltage semiconductor and protection choices: how 700–1500 V DC inputs drive Si vs SiC device selection, which gate-driver and isolation specifications prevent dv/dt related EMI issues, and where leakage current, ground-fault and EMI monitoring should live inside the inverter.

Battery pack design, BMS functions and site-level EMS or SCADA strategies are not covered here. Those topics belong to the battery, PCS and EMS pages. This page stays inside the string or micro inverter enclosure and concentrates on IC-level hooks for safe, grid-compliant power conversion.

Electrical environment & stress map

String and micro inverters operate in very different DC and AC environments. Module-level micro inverters typically work from 30–80 V DC at higher currents and short cable runs, while string inverters handle 600–1500 V DC with longer wiring and much higher insulation and creepage requirements. These levels set the baseline for gate-driver isolation ratings, CMTI targets and the way current and voltage are sensed.

On the AC side, the inverter usually interfaces to 120/230 Vac single-phase circuits or 400/480 Vac three-phase services. Fault and leakage currents must remain within the limits imposed by RCDs and grid protection devices, which drives the ranges and bandwidths for phase-current sensors and residual-current monitoring AFEs used for ground-fault detection and safety shutdown.

Switching frequencies in the 10–50 kHz range for string inverters and up to around 60–100 kHz for micro inverters combine with steep dv/dt and di/dt edges, especially when SiC devices are used. These stresses translate into hard requirements for gate-driver CMTI, isolation devices, sigma-delta modulators and analog front ends that must survive fast common-mode swings while still delivering accurate measurements for control and protection.

The summary below focuses on electrical levels and standards that directly affect power-stage IC selection: gate drivers, sensing amplifiers, isolation components and protection comparators. Detailed surge, ESD and EMC filter design is handled on the dedicated EMI and surge protection pages.

String vs micro: topology roles & use cases

String and micro inverters solve the same problem with very different power-stage topologies. A string inverter concentrates several kilowatts up to tens of kilowatts from a 600–1500 V DC string into a single cabinet, while a micro inverter processes only a few hundred watts from a 30–80 V DC module or small group of modules. This choice directly changes the number of bridge legs, gate drivers and sensing channels that need to be designed and monitored.

In a string inverter, higher DC voltage and centralised power flow favour distributed gate-driver and sensing ICs: isolated high-side and low-side drivers per switch, multiple current and voltage sensing points across the DC link and AC phases, and separate sigma-delta modulators or isolation amplifiers feeding the control processor. Faults tend to be detected and cleared at string or inverter level, which puts more responsibility on residual-current sensing and grid-protection coordination inside the unit.

In a micro inverter, each module-level unit can use a smaller number of bridge legs and a compact set of drivers and sensors, often implemented as a highly integrated power-stage SoC. Lower DC bus voltage eases isolation requirements, but higher per-module currents and dense layouts push integration: combined gate-driver and control ICs, embedded ADCs or AFEs, and built-in protection functions to support fast per-module shutdown and compliance with rapid-disconnect and safety regulations.

Fault isolation granularity is therefore very different. String inverters typically disconnect one or more strings or the entire inverter when a fault is detected, whereas micro inverters can isolate only the affected module and keep the rest of the array online. This shifts how leakage current limits, RCD coordination and EMI limits are allocated across the system. Module-level optimizers and hybrid PV–battery architectures build on these roles and are treated on dedicated optimizer and hybrid inverter pages.

HV gate-driver architectures

The choice of gate-driver architecture follows directly from the inverter bridge topology and DC bus level. Single-phase H-bridges, three-phase two-level bridges and multilevel NPC or ANPC stages all need reliable high-side and low-side drive, but the required insulation strength, common-mode transient immunity and number of isolated channels differ widely between low-voltage micro inverters and high-voltage string inverters.

At lower DC voltages, a micro inverter can often use classical half-bridge drivers with level-shift or bootstrap supplies. These devices combine a high-side and low-side driver in one IC and are adequate where dv/dt is moderate and insulation requirements are limited to basic isolation. At higher string voltages and especially with SiC devices, dv/dt and insulation constraints tend to force a move toward fully isolated gate drivers, with one isolated channel per switch or per leg and dedicated isolated power supplies for each floating gate-driver domain.

Gate-driver selection therefore involves more than peak drive current. Required isolation level, CMTI rating, gate-voltage window and the way gate supplies are generated all matter. Reinforced-isolation drivers and isolators must withstand common-mode swings in the tens of kV per microsecond on a 600–1500 V bus, while still delivering clean edges to Si or SiC switches. Many modern drivers also integrate DESAT detection, UVLO and temperature feedback to help implement fast hardware protection at the bridge-leg level.

Si and SiC devices impose different gate-drive requirements. Si-based MOSFETs and IGBTs usually operate around a single positive gate voltage with modest dv/dt, making them more tolerant of traditional level-shift schemes. SiC MOSFETs often need higher drive voltages and negative gate bias for robust turn-off, together with very high CMTI and carefully controlled slew rate. In high-voltage string inverters, this typically points to isolated gate drivers matched with isolated sigma-delta modulators or isolation amplifiers for current and voltage feedback. Multilevel and multi-inverter systems build on these single-bridge choices and are covered on the PCS and system-level pages.

Current & voltage sensing chain

The power stage in a string or micro inverter depends on accurate sensing of DC-link voltage and current, AC phase currents and residual or leakage current. These signals feed both the control loops and the fast protection paths that disconnect the inverter when limits are exceeded. The sensing chain typically combines shunts, current transformers, Rogowski coils or integrated Hall and AMR sensors with analog front ends, isolation components and ADCs or sigma-delta decoders in the controller.

On the current side, low-power micro inverters often favour shunt-based sensing with current-sense amplifiers, while higher-power string inverters benefit from CTs, Rogowski coils or isolated Hall and AMR sensors that reduce dissipation and provide galvanic isolation. DC-link and phase currents may be brought into the controller as conditioned analog voltages through isolation amplifiers, or as bitstreams from isolated sigma-delta modulators that are decoded by digital filters on the MCU or DSP side.

Voltage sensing typically uses resistor dividers and precision amplifiers for medium-voltage nodes, and isolated sigma-delta or dedicated high-voltage AFEs for direct measurement of DC-link and AC line voltages. Bandwidth, CMTI rating, noise and offset performance of these isolation and AFE devices determine how quickly the controller can react to faults and how much accuracy is available for metering, efficiency optimisation and grid-code compliance.

Error budgeting and protection strategy link the sensing chain directly to overcurrent and short-circuit detection. Fast comparators and desaturation monitors provide sub-microsecond trip paths, while ADC and sigma-delta measurements feed slower control and diagnostic loops. Typical IC roles include current-sense and isolation amplifiers, isolated sigma-delta modulators, differential ADCs and precision references. Cell-level and battery-pack current sensing remains in the scope of Pack BMS and BMU/CMU pages, while this section focuses on the inverter power stage itself.

Synchronous rectification & efficiency features

Synchronous rectification is a key tool for squeezing efficiency from small and medium power stages in string and especially micro inverters. Replacing diode conduction with actively switched MOSFETs reduces losses in DC/DC stages, in AC-side current paths and in auxiliary supplies that support control and communication. Lower conduction loss translates directly into higher efficiency, reduced temperature rise and more margin against thermal derating in compact rooftop and module-level designs.

Implementations range from dedicated synchronous-rectifier controllers that sense current and device voltage to decide when to drive SR MOSFETs, through to firmware-based schemes that use precise timers and PWM units inside the MCU or DSP. In all cases the SR timing must respect dead time, body-diode conduction intervals and current direction so that devices switch on only when they genuinely reduce losses and do not create shoot-through across the power stage.

Gate-driver integration is an important architectural choice. Some designs use multi-channel gate-driver ICs that combine main bridge drive and synchronous-rectifier control in a single package, easing layout and skew control. Others keep the SR controller separate from the main gate drivers to gain flexibility in how many phases are implemented or to reuse the same driver set across different power ratings. In either case, the SR control signals and gate drivers must coordinate closely to meet efficiency targets without compromising stability or protection response.

IC families involved in synchronous rectification include SR controller ICs for DC/DC and AC stages, power management ICs with integrated MOSFET drivers and SR functions, and MCUs or DSPs with advanced timer and PWM peripherals to generate complementary gate signals with adjustable dead time. MPPT algorithms, DC bus energy scheduling and PV power tracking remain on the MPPT charge controller and system-level pages; this section keeps synchronous rectification in the context of inverter efficiency and thermal design.

EMI, protection and monitoring hooks

High dv/dt switching in string and micro inverter bridges creates significant common-mode and differential noise, which directly constrains EMI filters, gate-driver selection and PCB layout. Higher switching speed, especially with SiC devices and 600–1500 V DC buses, demands gate drivers and isolators with robust CMTI, carefully managed return paths and well-damped gate networks so that switching edges do not cause false triggering or excessive EMI emissions through the filter and cabling.

Leakage and residual current sensing sits at the intersection of safety and EMI. Differential current transformers or residual-current monitoring AFEs measure the imbalance between conductors and feed comparators and protection logic inside the inverter. These circuits coordinate with external RCDs and, where required, arc-fault detection devices by providing trip signals, status lines and measured values that can be reported to a controller. Dedicated AFEs can perform band-limited energy detection to support AFDD functions while still presenting clean digital outputs to the protection logic and MCU.

At the input and output terminals, surge and overvoltage protection elements such as MOVs, GDTs and EMI filter stages are complemented by IC-based supervision. Resistor dividers and window comparators implement OVP and UVP thresholds on DC-link and AC lines, while eFuse, hot-swap and active-clamp controllers provide inrush control, current limiting and controlled shutdown during faults. These devices interface to gate drivers, contactors and the digital controller through fault pins, enable lines and status outputs so that protection and restart behaviour can be tuned at the system level.

EMI monitoring completes the picture. Dedicated EMI sensing AFEs can observe common-mode or differential noise at critical nodes and feed envelope or filtered metrics into the controller. Digital power controllers may then adjust switching frequency, spread-spectrum modulation, slew rate or dead time to balance EMI against efficiency and thermal constraints. Detailed EMI filter dimensioning, surge coordination and lightning test strategies are handled on dedicated EMI and surge design pages; this section focuses on the hooks that the inverter power stage exposes to sensing, protection and EMI monitoring ICs.

Digital control, grid sync and communication

The digital controller is the central node that ties together gate drivers, sensing AFEs, EMI monitors and communication interfaces in a string or micro inverter. Smaller micro inverters often rely on a single MCU or DSP that generates PWM, decodes sigma-delta bitstreams, executes control loops and handles communication. Higher-power string inverters frequently partition functions between a real-time digital power controller or FPGA and a supervisory MCU, so that high-speed PWM, protection and signal processing can be implemented alongside protocol stacks, logging and lifecycle management.

Grid synchronisation requires accurate measurement of AC voltage and current to track frequency, phase and amplitude. Digital PLLs using αβ or dq transformations estimate the grid phase and support current control and power-factor adjustment, while zero-crossing detection and over/under-frequency logic provide additional protection thresholds. These algorithms operate on the same voltage and current signals delivered by the sensing chain, linking the design of AFEs, isolation and ADCs directly to compliance with grid codes and ride-through requirements.

Safety hooks inside the controller architecture include watchdogs, brown-out monitors and dedicated fault-handling paths. Fast hardware-level trips from comparators, RCM and AFDD AFEs or desaturation monitors can shut down gate drivers within microseconds, while the MCU or DSP records the event, updates counters and decides whether and how to restart. Interfaces to gate drivers, AFEs and EMI monitors use PWM, complementary outputs with dead time, SPI, LVDS sigma-delta channels and simple GPIO fault lines, so pin multiplexing and timing resources are critical selection criteria for the controller IC.

Toward the system level, the inverter exposes measurement points and control points to EMS and site gateways over communication interfaces. Protocols such as Modbus/TCP, SunSpec mappings or IEC 61850-90-7 profiles carry voltages, currents, power, energy, temperature, insulation status, RCD and AFDD flags, as well as enable, power setpoint, power-factor and ramp-rate commands. Plant-level dispatch algorithms, multi-inverter coordination and microgrid energy management strategies belong to EMS and gateway pages; this section keeps the focus on the digital controller of a single inverter and how it synchronises with the grid and links to higher control layers.

Design checklist & IC mapping

This checklist only covers string and micro inverter power stages and the ICs that sit around the bridge, DC-link and AC filters. Battery management systems, MPPT controllers, energy-management systems and site gateways are covered on dedicated pages elsewhere in the site.

This checklist helps review a string or micro inverter design from the perspective of gate drivers, sensing chains, synchronous rectification and EMI monitoring. It focuses on the IC roles that frame the power stage and the key parameters that should be locked before layout, type testing and certification.

• DC-link voltage range, topology (string or micro) and switching frequency targets are defined, and selected gate drivers and isolators meet or exceed the required insulation class and CMTI for the worst-case dv/dt.
• Slew-rate limits on bridge legs are consistent with EMI, efficiency and thermal constraints, and can be tuned via gate resistance, driver settings or digital slew-control features where available.
• Each bridge arm has a documented short-circuit and overcurrent detection path with a reaction-time budget from fault onset to gate-off that meets the target protection requirement, including desaturation detection, comparator delays and driver shutdown time.
• Gate-driver UVLO thresholds, fault-latch behaviour and reset strategy are aligned with the DC-link architecture and safe restart policy, including coordination with any contactors or eFuse and hot-swap devices.
• DC-link and phase-current sensing technologies (shunt, CT, Rogowski, integrated Hall or AMR sensors) are chosen according to power level, dissipation limits and required isolation class for the target installation.
• Bandwidth, noise and offset performance of current-sense amplifiers, isolation amplifiers and sigma-delta modulators support both control-loop bandwidth and fault-detection requirements over temperature and tolerance.
• Voltage-sense dividers, AFEs and references are dimensioned so that DC-link and AC-line measurements cover all operating, test and surge conditions without saturating ADC or sigma-delta input ranges.
• Leakage and residual current measurement range and bandwidth cover the applicable RCD and standard limits, and the RCM or AFDD front ends provide both a fast trip output and a measurable value for logging and diagnostics.
• Synchronous rectification is applied where conduction losses materially impact efficiency, and SR timing is coordinated with gate-driver dead time and body-diode conduction so that shoot-through is avoided across the full operating envelope.
• Surge and overvoltage protection elements at DC and AC terminals are paired with window comparators or supervision circuits that can command controlled shutdown and record over-stress events for later analysis.
• If EMI sensing AFEs are used, measurement points, bandwidth and metrics are defined so that digital controllers can meaningfully adjust switching frequency, spread-spectrum and slew-rate settings rather than only passively filtering noise.
• The control architecture (single MCU or DSP, or MCU plus FPGA or digital power controller) provides sufficient PWM, complementary-output and high-speed capture resources to implement bridge control, synchronous rectification, PLL and protection without pin or timer conflicts.
• Grid-synchronisation algorithms are matched to available voltage and current measurements and validated against the target grid codes and ride-through requirements for the intended markets.
• The inverter exposes a consistent set of measurements (voltages, currents, P, Q, energy, temperature, insulation status and protection counters) and control points (enable, active and reactive power limits, power factor and ramp rates) over the chosen communication protocols toward the EMS or site gateway.

FAQs about string and micro inverter IC choices

This FAQ collects common design questions for string and micro inverters from the perspective of gate drivers, sensing chains, synchronous rectification and EMI monitoring. Each answer points back to the section where assumptions, trade-offs and IC roles are explained in more detail.