Analog Input (4–20mA/HART/±10V) Front-End Design
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This page provides a comprehensive guide to designing accurate industrial analog input channels for 4–20mA, HART, and ±10V signals using PGA + ΣΔ ADCs, while ensuring precision, protection, and diagnostic capabilities. Learn about key topics such as burden voltage, isolation, calibration, and noise management to optimize performance and reliability in your designs.
H2-1. Center Idea
Industrial analog input channels must stay accurate under long cables, ground offsets, and fast transients. This subpage defines a repeatable, verification-first channel architecture that supports 4–20mA loops, preserves DC accuracy while extracting HART FSK overlay, and measures ±10V signals through a PGA + ΣΔ ADC front end with per-channel isolation, protection, and diagnostics.
Evidence chain focus: each block provides two measurable checkpoints and a first corrective action to shorten bring-up and field debug.
H2-2. Scope & Channel Taxonomy
This page stays strictly at the channel interface level: what the input must survive, what must remain accurate, where isolation belongs, and which measurements prove correctness. The taxonomy below prevents scope creep and keeps all design tradeoffs tied to measurable constraints.
The channel types are organized by the constraint that most often breaks real deployments: headroom (4–20mA burden), coexistence (HART overlay without DC drift), miswire/ground offsets (±10V), and common-mode control (isolation boundary).
- 4–20mA receive (2-wire / 3-wire / 4-wire) — Shunt-based sensing where burden voltage and loop compliance determine whether 20mA can be measured without saturation. Headroom budgeting must include protection elements, series impedance, and worst-case cable drop.
- HART overlay (FSK coexisting with DC loop) — A two-path requirement: the DC measurement path must remain linear and stable, while a separate FSK extraction path preserves modem SNR. Any coupling network that shifts DC gain/offset is treated as a measurable defect.
- ±10V voltage input — High-impedance scaling into PGA/ADC with field realities: ±24V miswire, fast transients, and ground potential differences. Robustness is defined by clamp behavior and post-event accuracy drift, not by survival alone.
- Per-channel isolation — Isolation is a system choice: isolate data, power, or (rarely) analog. The barrier must be evaluated by CMTI-induced code glitches, noise coupling into reference/ground, and predictable fault signaling across domains.
Out of scope: RTD/thermocouple front ends, analog output stages, and full PLC/fieldbus stacks. Those topics have different error models and would dilute this channel-level evidence chain.
H2-3. System Block Diagram
A canonical channel map prevents design tradeoffs from being made in isolation. The two input lanes (4–20mA/HART and ±10V) converge into a shared PGA + ΣΔ ADC conversion core, so accuracy and robustness must be managed end-to-end: survival at the connector, predictable scaling and filtering, verified digitization, and a controlled isolation boundary that preserves diagnostics and code integrity.
Evidence taps are fixed checkpoints used across bring-up, calibration, and field debug: Tap1 shunt/divider node, Tap2 anti-alias node, Tap3 PGA input, Tap4 ADC raw code, Tap5 post-decimation code, Tap6 fault flags & logs.
Survival layer
Protection, miswire tolerance, transient containment.
Accuracy layer
Scaling, AA/EMI filtering, PGA/ΣΔ conversion and digital filtering.
Trust layer
Calibration, diagnostics, and stable reporting across isolation.
HART coexistence
FSK extraction path must not perturb DC measurement path.
H2-4. 4–20mA Receive Fundamentals
4–20mA channels most often fail at the top end because headroom is silently consumed across series elements: protection clamps, series impedance, cable drop, and the shunt itself. Before selecting an ADC or a PGA, the loop must be treated as an energy-and-voltage budget where burden voltage remains positive at 20mA under worst-case wiring and transients.
Shunt selection is a three-way tradeoff
- Noise vs resolution: a higher shunt produces more signal voltage but increases the burden and amplifies self-heating.
- Headroom vs survivability: adding series resistors or heavy clamps can protect the input while making 20mA unreachable.
- Self-heating vs drift: shunt power dissipation creates temperature rise that converts TCR into slow gain drift and apparent nonlinearity.
Burden and compliance must include “hidden drops”
- Protection drop: TVS/leakage paths and clamp steering can disturb low-current accuracy and limit the high-current ceiling.
- Cable and ground offsets: long runs and ground potential differences inject common-mode stress that becomes measurement error without controlled isolation and shielding.
- Shield termination (interface-level): termination strategy must avoid creating a noise return path that raises shunt ripple and ADC code modulation.
Evidence chain (minimum verification):
Measure Vshunt at 4mA and 20mA, plus fault cases (0mA, >20mA) to confirm headroom and diagnostic boundaries.
Measure ΔTshunt at worst-case current to determine whether self-heating is large enough to explain drift.
Symptom
20mA reads low or clips.
Check
Tap1 Vshunt, plus clamp/series drops.
Symptom
Slow drift after warm-up.
Check
ΔTshunt and TCR sensitivity in the error budget.
H2-5. ±10V Path
±10V inputs fail in real installations primarily due to miswire (for example, ±24V or unexpected external drive), ground differences, and fast transients coupled through long cables. A robust path defines a stable input impedance, scales the signal into the PGA range without creating a high-leakage error source, and forces overvoltage energy into a predictable clamp-and-dissipation path that does not disturb rails or references.
Impedance target
Not “as high as possible”—balanced against leakage, bias-induced error, and ESD robustness.
Scaling strategy
Divider/attenuation must preserve headroom for transients and avoid clipping the PGA input.
Overvoltage handling
Define where energy goes: into series dissipation, clamps, and safe return paths.
Common-mode control
If referenced to local ground, isolation + layout must prevent ground-loop induced error.
Divider and input impedance planning
- Attenuation into PGA range: select divider ratio so ±10V maps into the PGA/ADC window with margin for overshoot and tolerance stack-up.
- Impedance target: overly high impedance amplifies leakage, contamination, and bias-current induced offsets; overly low impedance loads the field source and raises power dissipation under miswire.
- Anti-alias node ownership: the AA/EMI network must be treated as a settling element for both accuracy and multiplexed timing.
Miswire and transient survival without “rail collapse”
- ±24V miswire and coupling spikes: ensure clamps activate predictably and the series path limits energy so component stress and drift remain controlled.
- Clamp return paths: clamp current must return locally and avoid injecting into sensitive references, ADC grounds, or isolated supplies.
- Rail disturbance awareness: a clamp-to-rail approach must be verified against supply droop/overshoot that can corrupt codes and diagnostics.
Evidence chain:
(1) Capture step response at the AA filter node to validate bandwidth and settling.
(2) Verify overvoltage clamp behavior by scoping the clamp node and monitoring rail disturbance during an induced event.
H2-6. PGA Selection & Gain Strategy
The PGA is where “spec-sheet accuracy” becomes system reality. A correct gain plan keeps both lanes inside the conversion window with transient margin, while input bias currents and settling behavior remain compatible with the source impedance created by shunts and dividers. For multiplexed channels, settling must be defined on a timeline that includes analog settle, ΣΔ modulator stabilization, and post-decimation validity.
Gain map
Keep headroom across 4–20mA and ±10V after tolerances and transients.
Bias vs source Z
Divider impedance converts bias current into offset and drift.
Settling with MUX
Switching requires a defined discard window before codes are trusted.
Noise verification
Measure input-referred noise at each gain, not only ADC RMS noise.
Gain planning across both lanes
- Unify ranges at the PGA input: map 4–20mA shunt voltage and attenuated ±10V into a shared PGA/ADC window with margin for overshoot and clamp recovery.
- Avoid clipping by construction: transient headroom must be reserved so protection events do not force long recovery or corrupt diagnostic decisions.
- Separate “measurement gain” from “debug gain”: high gain may improve resolution but can be reserved for low-current regions or controlled modes where settling is guaranteed.
Bias currents and settling time are the hidden limiters
- Bias vs impedance: bias currents flowing through high source impedance become an offset that tracks temperature and contamination.
- MUX timing: after channel switch, analog nodes must settle before the ΣΔ chain is considered stable; otherwise post-decimation codes can look “clean” while being wrong.
- Define a validity rule: codes are trusted only after settling to < ½ LSB at the chosen sample rate and filter setting.
Evidence chain:
(1) Measure effective input-referred noise at each gain (raw code and post-decimation).
(2) Apply a step input (or MUX-switch step) and capture settling until the output stays within < ½ LSB at the chosen conversion rate.
H2-7. ΣΔ ADC Architecture & Digital Filtering
ΣΔ ADCs dominate industrial analog input because oversampling and decimation deliver practical benefits that are hard to replicate consistently with other architectures: strong 50/60Hz rejection, stable low-frequency noise behavior, and configurable tradeoffs between resolution, update rate, and latency. The system must treat the output code as a filtered estimate with a defined group delay, not an instantaneous measurement.
What it buys
Noise shaping + decimation enable strong mains notch and low RMS noise.
What it costs
Filter group delay: better rejection typically increases latency.
Update rate tradeoff
Higher data rate reduces latency but can weaken 50/60Hz rejection.
Multi-channel risk
MUX + digital filter memory can create “clean but wrong” codes.
Oversampling and decimation in practical terms
- Noise shaping: quantization noise is pushed out of the measurement band so the in-band RMS noise is reduced after filtering.
- Decimation filtering: the digital filter defines the measurement bandwidth and creates targeted rejection (notches) around mains frequencies.
- Notch expectations: mains rejection is not “free”—changing the data rate or filter setting shifts how deep and how wide the notch is.
Latency vs rejection: a decision that must be explicit
- Group delay matters: the reported code is delayed by the filter and can lag real changes—important for step events, alarms, and channel switching.
- Update rate vs stability: faster updates can increase visible code ripple at 50/60Hz when the notch depth is reduced.
- Define “valid code timing”: for each filter setting, the design must specify when a step change becomes trustworthy at the output.
Multi-channel sampling: simultaneous vs multiplexed ΣΔ
- Simultaneous channels: each channel has its own conversion path, minimizing time-skew and filter-memory interaction.
- MUXed channels: shared conversion paths reduce cost but can expose crosstalk, residual settling, and digital-filter memory effects.
- Operational rule: after a MUX switch, discard a defined window until the decimated output is inside the expected band (ties back to the settling rules in H2-6).
Evidence chain:
(1) Measure RMS noise vs data rate (or FFT/noise density when available) to confirm the intended tradeoff.
(2) Run a mains rejection test: inject 50/60Hz ripple (differential or common-mode) and verify the resulting code ripple is suppressed as expected.
H2-8. HART Coexistence
HART is an overlay problem: a small FSK signal is superimposed on the 4–20mA loop and must be extracted without shifting DC accuracy. The design must define a coupling point for the FSK energy, partition DC and FSK paths with predictable filtering, and place the modem interface so that amplitude, SNR, and diagnostic boundaries remain verifiable under real cable and EMI conditions.
Coupling point
Across shunt vs dedicated coupling network—controls FSK amplitude and DC disturbance risk.
Path partitioning
DC stays on the measurement chain; FSK is extracted via HP/BP filtering into the modem input.
Modem placement
Dedicated modem IC vs MCU DSP demod—interface-level decision driven by input window and SNR.
Verification
A/B test ensures FSK enablement does not shift DC accuracy; measure modem input level and noise.
Where to couple the HART signal
- Across the shunt: directly senses the loop’s AC component but requires careful partitioning so the measurement path gain/offset model stays stable.
- Coupling network: a dedicated coupling path can provide a controlled FSK amplitude while reducing DC path perturbation.
- Energy ownership: the coupling strategy must specify where FSK current flows and how it returns, so it does not masquerade as DC error.
Keep the DC path stable while extracting FSK
- Partition concept: DC/low-frequency components remain in the main conversion chain, while FSK is routed through a high-pass or band-pass partition into the modem.
- Stability rule: enabling the HART path must not shift the DC transfer function (gain/offset/linearity), especially at 4mA and 20mA endpoints.
- Isolation awareness: partitioning should preserve a clean modem input even when the measurement channel crosses an isolation barrier.
Modem placement: IC vs MCU demod (interface-level)
- Dedicated modem IC: predictable analog front-end expectations and faster bring-up for field deployments.
- MCU DSP demod: flexible but typically demands a well-defined modem input window, stable sampling resources, and validated SNR margins.
- Common requirement: modem input amplitude and noise must be measurable at a dedicated tap point.
Evidence chain:
(1) A/B test DC accuracy: compare 4–20mA endpoints with vs without FSK enabled to confirm no gain/offset shift.
(2) Level/eye check at modem input: verify FSK amplitude and SNR at the modem tap point.
H2-9. Per-Channel Isolation Choices
Per-channel isolation is a defining attribute of industrial-grade analog input. The isolation boundary must contain field-side ground shifts, surge common-mode energy, and fast dV/dt events so that the post-barrier interface does not show code glitches, false fault flags, or communication errors. The architecture choice is not only about which isolator to use, but where the ADC, digital interface, and isolated power live relative to the barrier.
Digital isolation (recommended)
ADC on field side + isolated SPI/I²C/UART keeps accuracy modeling simpler and more repeatable.
Analog isolation (rare)
Harder to preserve linearity and drift; calibration models become more sensitive to temperature and aging.
Isolated power
Per-channel rails reduce cross-channel coupling; shared rails require strong proof of ripple containment.
Layout constraints
Creepage/clearance and barrier routing constrain placement; treat the barrier as a hard boundary early.
Decision matrix: where to isolate
- Digital isolation: place the ADC on the field side and isolate the digital interface (isolated SPI/I²C/UART). This contains analog vulnerability and keeps post-barrier signaling robust.
- Analog isolation: isolate the analog signal itself (legacy/rare). This is harder to keep accurate because isolation elements can add gain error, nonlinearity, bandwidth limits, and drift.
- Power isolation: decide between per-channel isolated rails and a shared isolated rail. Shared rails can inject ripple and event energy across channels if not tightly controlled.
- Creepage/clearance constraint: barrier spacing and routing affect component placement and return paths; avoid “snaking” signals that increase coupling around the boundary.
Shared isolated rail vs per-channel isolated power
- Shared isolated rail: simplest distribution, but requires a measured proof that one channel’s transient load or protection event does not modulate ADC reference/ground for other channels.
- Per-channel isolated rail: improves channel independence and reduces correlated noise and fault propagation at the cost of power/channel resources and board area.
- Noise coupling focus: treat the ADC reference and ADC ground as the primary coupling “victims,” especially during fast dV/dt events and burst disturbances.
Evidence chain:
(1) CMTI immunity test (fast dV/dt event): check for output code glitches, false fault flags, and interface errors.
(2) Barrier noise coupling: measure ripple injected into ADC Vref / GND (and the isolated rail) and correlate it with code ripple.
H2-10. Protection, Miswire, and EMC
Protection networks are required for surge, ESD, and EFT, but they can quietly destroy accuracy if their capacitance, leakage, return paths, or rail-clamp energy flow are not controlled. Industrial-grade design treats protection as a set of measurable building blocks: energy containment must be proven while preserving the input transfer function, noise floor, and recovery behavior.
TVS philosophy
Energy rating vs capacitance vs leakage—choose the smallest error source that still survives.
Series impedance
Series R/PTC protects but changes gain and settling; include it in the accuracy and bandwidth model.
Rail clamps
Clamping to rails can inject energy into supplies (“rail kick”); control with local decoupling and current steering.
Weak nodes
AA filter node and PGA input are common EFT/ESD weak points; add test taps where failure actually occurs.
TVS selection: survival vs accuracy
- Energy capability: must survive the intended surge/EFT stress without degradation.
- Capacitance: reshapes the high-frequency response and can alter AA behavior, settling, and HART extraction margins.
- Leakage: creates an offset and temperature-dependent drift term, especially harmful on high-impedance nodes.
- Placement and returns: choose the return path so protection current does not flow through sensitive references or ADC grounds.
Series impedance (R/PTC): model the side effects
- Gain error: series elements interact with shunts/dividers and PGA bias to create measurable transfer function shifts.
- Bandwidth and settling: added impedance increases time constants, which is critical for multiplexed sampling and for step-response validity.
- Recovery behavior: after an event, verify that resistance and leakage return to nominal so calibration does not drift.
Clamps to rails: control “rail kick”
- Energy injection: rail clamps redirect surge energy into local supplies; without control this can disturb ADC Vref and digital state machines.
- Local decoupling: use near-clamp energy storage so the event closes locally instead of modulating shared rails.
- Current steering: define the return routes so clamp current avoids sensitive grounds and reference nodes.
Evidence chain:
(1) After EFT bursts: confirm no latch-up, no stuck fault flags, and no calibration drift versus pre-test baselines.
(2) During surge/EFT: measure code burst noise and define recovery time until codes return to stable within the allowed window.
H2-11. Accuracy Budget, Calibration & Diagnostics
This chapter makes performance provable. Industrial analog input accuracy is not a single spec—it’s the sum of measurable contributors (shunt + PGA + ADC + reference + isolation coupling + self-heating) and a repeatable calibration workflow. The goal is a checklist that links: error budget → calibration model → residual plots → diagnostics.
Budget-first
Quantify each error source before calibrating so fixes target the dominant term.
Model-based calibration
Choose 2-point / multi-point / per-range / temp compensation based on the error shape.
Residual evidence
Golden-source sweep produces residual plots that prove linearity and endpoints.
Diagnostics tie-in
Fault detection must not corrupt calibration and must remain stable after EFT/surge events.
Error sources: what actually contributes to channel error
Use this as a living budget: each item should have a measured baseline, a temperature dependence, and a “can calibration remove it?” label.
| Bucket | Error source (what it looks like) | Why it matters in 4–20mA / ±10V | MPN examples (parts you’ll see in real designs) |
|---|---|---|---|
| Shunt / scaling |
Shunt tolerance (gain), Shunt TCR (gain drift), Self-heating (I²R → local ΔT) |
Dominates endpoint gain and drift. Self-heating can create “mA-dependent” drift at 20mA. | Vishay WSL3637 (power shunt), Vishay WSLP2726 (low-ohm), Isabellenhütte ISA-WELD/SMT series (precision shunt families) |
| PGA / AFE |
PGA offset (zero error), PGA gain drift (temp), Input bias × source R (offset term), Settling (MUXed channels) |
PGA defines low-end accuracy at 4mA and near 0V. Bias-current effects grow with high source impedance (dividers, filters). | TI ADS124S08 (ΣΔ ADC + PGA), TI ADS1220 (ΣΔ + PGA), Analog Devices AD7124-4 (ΣΔ + PGA) |
| ADC linearity |
INL/DNL (nonlinearity), Noise vs data rate (effective resolution), Digital filter group delay |
INL shows up as curved residual plots. Filter settings change noise/rejection/latency and can affect “alarm timing.” | TI ADS131M04 (multi-channel ΣΔ), Analog Devices AD4130-8 (precision ΣΔ families), Microchip MCP3564 (precision ΣΔ) |
| Reference (Vref) |
Vref initial error, Vref drift (ppm/°C), Vref noise (code ripple) |
Vref is the ruler. Rail-kick or isolation coupling into Vref produces correlated code ripple across channels. | TI REF5025 (2.5V ref), Analog Devices ADR4525 (2.5V ref), Maxim/ADI MAX6070 (precision ref) |
| Isolation coupling |
Barrier noise injected into ADC GND/Vref, Shared isolated rail ripple coupling, dV/dt-induced code glitches |
Often the hidden limiter for “industrial-grade.” Causes burst noise during events and slow recovery artifacts. | ADI ADuM141E / ADuM140D (digital isolators), TI ISO7741 (digital isolator), ADI ADuM5020 (isolated power), TI SN6505 (iso power driver) |
| Protection side-effects |
TVS leakage (offset drift), TVS capacitance (bandwidth/settling change), Clamp-to-rail “rail kick” |
Protection can create temperature-dependent offsets and event-correlated errors if return paths and local decoupling are wrong. | Littelfuse SMBJ TVS family, Bourns SMBJ TVS family, Nexperia PESD ESD families, TI TPS2595 (eFuse for rail event containment examples) |
Calibration strategy: pick the smallest model that matches the error shape
2-point (gain + offset)
Best when residuals are near-linear and endpoints dominate. Fast and robust for production.
Multi-point
Use only when residual plots show curvature (INL / leakage-induced nonlinearity) that 2-point can’t remove.
Per-range calibration
Required for PGA gain ranges or multiple input modes (4–20mA vs ±10V) because each path has unique drift.
Temperature compensation
Record drift vs temperature and apply gain/offset TC. Prove improvement with before/after sweeps.
A practical workflow separates what calibration can remove (gain/offset terms, stable drifts) from what it cannot (event-driven rail kick, intermittent coupling, unstable leakage). Calibration must be disabled or frozen when diagnostics indicate an abnormal state (open loop, overvoltage, overcurrent, or post-event recovery).
Diagnostics: channel-level faults that protect data integrity
- Open loop / wire break: impossible current/voltage region for a sustained window; log an event and hold calibration updates.
- Overcurrent / short: shunt drop exceeds the valid range or protection stays active; record peak and enforce a recovery timer.
- Overvoltage / miswire: clamp activity + rail disturbance; treat as an “event state” and require post-event stability before trusting data.
- Stuck fault flags / latched behavior: persistent flags after a reset window indicate a hard fault or latch-up risk; force a safe state and record counters.
Evidence chain:
(1) Golden source sweep (4mA→20mA; -10V→+10V) and generate a residual error plot (before/after calibration).
(2) Temperature sweep: record gain/offset drift vs temperature and show before/after compensation curves to prove improvement.
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H2-12. FAQs
Format per question: 1 conclusion + 2 evidence points + 1 first fix. Each answer links back to H2-4…H2-11 and includes concrete MPN examples.
Use the same evidence taps (AA node, PGA input, Vref ripple, post-decimation code, fault flags) to convert symptoms into measurable checks and a first fix.
Tip: Each answer below includes concrete MPN examples. Treat them as reference parts for design patterns and verification—not a universal BOM.
“4–20mA reads low only at 20mA—burden headroom or shunt self-heating?”
→ H2-4 / H2-11
- Measure shunt drop and the node after protection at 20mA; confirm the loop still has compliance margin under worst-case (TVS/clamps active).
- Log shunt temperature rise at 20mA and compare gain drift vs TCR (e.g., Vishay WSL3637 vs precision shunt families).
“±10V clips near +8V—divider ratio wrong or PGA input common-mode limit?”
→ H2-5 / H2-6
- Probe the AA node and PGA input at +8V and +10V; confirm the PGA input stays inside its allowed common-mode range (e.g., ΣΔ+PGA like AD7124-4 or ADS124S08).
- Verify the divider ratio and clamp behavior under ±24V miswire using an ESD/TVS node check (capacitance/leakage effects).
“Noise is fine in lab, terrible on site—shield/ground loop or EFT coupling?”
→ H2-10 / H2-9
- Correlate post-decimation code bursts with rail/Vref ripple and clamp activity during EFT-like disturbances; watch Vref parts like ADR4525 or REF5025.
- Check isolation barrier behavior under fast dV/dt; compare error rates/flags using digital isolators such as ISO7741 or ADuM141E.
“Muxed channels ‘ghost’ each other—PGA settling or ΣΔ digital filter latency?”
→ H2-6 / H2-7
- Step the input and capture settling at the PGA input to <½ LSB before the conversion window (typical in ΣΔ+PGA devices like ADS124S08).
- Change ΣΔ data rate / notch setting and watch group-delay effects in the output stream; correlated “lag” indicates filter latency (H2-7).
“HART works but DC accuracy shifts—coupling network leakage or ADC front-end loading?”
→ H2-8 / H2-4
- A/B test DC error with HART enabled vs disabled; watch shunt drop at 4mA and 20mA for a systematic offset.
- Measure the coupling node impedance and leakage over temperature; confirm the ADC input bias and source impedance interaction (e.g., AD7124-4 input modes).
“HART decode fails intermittently—FSK amplitude/SNR or modem input filter corner?”
→ H2-8
- Scope modem input amplitude and noise in the HART band while toggling loop current; ensure stable levels at the receiver input (e.g., using a HART modem IC like AD5700-1).
- Check the high-pass/band-pass corner and loading at the coupling node; confirm it does not shift with temperature or protection leakage.
“After surge, channel is ‘alive’ but offset changed—TVS leakage drift or clamp rail kick?”
→ H2-10 / H2-11
- Measure TVS leakage and clamp node behavior before/after stress; compare families (e.g., SMBJ TVS) for leakage sensitivity at temperature.
- Correlate Vref ripple and code offset with clamp-to-rail current events; verify reference stability (e.g., REF5025 or ADR4525).
“50/60Hz ripple shows up in codes—wrong notch setting or grounding/common-mode injection?”
→ H2-7 / H2-9
- Change data rate and notch mode and confirm the code ripple changes accordingly (typical in ΣΔ families like MCP3564 or ADS1220).
- Inject controlled 50/60Hz common-mode and measure Vref/GND ripple across the isolation boundary; spikes suggest coupling rather than filter mis-setting.
“Isolation causes random spikes—CMTI event or isolated supply ripple into ADC reference?”
→ H2-9 / H2-7
- Stress fast dV/dt and count code glitches/CRC errors with isolators such as ADuM141E or ISO7741 (CMTI signature is bursty, event-aligned).
- Measure isolated rail ripple from supplies like ADuM5020 or drivers like SN6505 and correlate with code spikes at the post-decimation output.
“Accuracy is great at room temp, bad at hot—TCR of shunt or PGA/REF drift?”
→ H2-11 / H2-4
- Run a temperature sweep and separate gain drift from offset drift; shunt-related gain drift scales with current (e.g., compare WSL3637-style shunts).
- Log Vref stability across temperature using references like ADR4525 or REF5025, and check PGA gain drift in AD7124-4/ADS124S08.
“Open-circuit detection triggers falsely—threshold/hysteresis or input protection capacitance?”
→ H2-10 / H2-11
- Compare flag timing to ΣΔ group delay and MUX settling; if the flag trips during settling, it is a window/hysteresis mismatch (H2-7).
- Measure AA node step response with the protection network populated (TVS/ESD like Nexperia PESD families can change capacitance).
“Loop current reads OK, but controller trips—diagnostic flag mapping or sampling window?”
→ H2-7 / H2-11
- Align the controller’s sampling window with the ΣΔ output update rate and group delay; confirm stability at the post-decimation stream (e.g., ADS131M04 style timing).
- Audit fault-flag mapping and latched behavior after events; verify flags clear deterministically after recovery (H2-10/H2-11).
