This page is a build-and-verify guide for an EC (conductivity) / resistivity meter front-end. It focuses on the signal chain and evidence needed to reach stable readings while preventing electrode polarization, drift, and noise-induced false changes.

A conductivity meter becomes reliable only when the design is treated as a coherent I/Q measurement problem: the excitation source and the demodulation reference must be phase-related (or phase-calibrated), and both in-phase (I) and quadrature (Q) components must be observable. In practice, I tracks solution-dominant conductivity, while Q is the early-warning channel for interface and parasitic effects (electrode double-layer behavior, cable capacitance, leakage paths).

Minimum Evidence Set (must be declared for reproducibility):

• Excitation: frequency f_exc, amplitude (V_exc or I_exc), waveform (sine / square / synthesized)
• Demod: I/Q outputs, demod low-pass bandwidth (ENBW) and update rate
• Coherence: clocking relationship between DAC and PSD reference (shared clock or phase-calibration method)
• Temperature: measured T, reference temperature T_ref, compensation model
• Calibration: standard values used, residual error after calibration
• Stability: drift slope over a fixed standard (e.g., 10 min / 1 h)

Fundamentals here are limited to what changes design choices: what the meter outputs, how cell constant (K) sets the measurable range, and what must be declared so results are reproducible across probes, frequencies, and temperatures.

Conductivity (σ) expresses how easily ionic current flows through the solution, while resistivity (ρ) is its inverse (ρ = 1/σ). In engineering terms, the meter is estimating a solution-dominant impedance and then mapping it to σ (or ρ) using the probe geometry. The geometry enters as the cell constant K (set by electrode spacing and area), and K effectively becomes the “range knob” for the whole analog front-end.

Why K dominates range planning (the practical view):

• High K probes push the same solution toward a larger effective resistance → smaller signal, more noise sensitivity.
• Low K probes push toward higher current → higher polarization risk, AFE headroom limits, and more self-heating artifacts.
• The right AFE (TIA gain, ADC range, excitation amplitude) is therefore chosen after K and expected σ range are known.

Derived outputs (TDS / salinity): in most meters these are computed from conductivity using application-specific conversion curves. They should be treated as declared transforms (document the curve/standard), not as independent sensor measurements. Keeping this boundary clear prevents scope creep and preserves auditability.

Electrode polarization is not a chemistry footnote—it is an electrical interface that stores charge and distorts low-frequency measurements. Treating the probe as a frequency-dependent impedance is the prerequisite for stable conductivity/resistivity readings.

The conductivity cell can be modeled as a solution resistance in series with an interface network. The interface is commonly represented by a double-layer capacitance (Cdl) and a charge-transfer resistance (Rct). Together with cable capacitance and leakage paths, the interface makes the measured impedance strongly dependent on frequency and time.

DC excitation fails because it continuously biases the interface, driving charge accumulation and slow relaxation. This produces drift that cannot be separated from solution resistance. In contrast, AC excitation with coherent demodulation isolates the component that is strictly synchronous with the excitation. The in-phase channel (I) tracks the solution-dominant contribution, while the quadrature channel (Q) is a sensitive indicator of interface/cable capacitance and leakage-induced phase error.

What to measure (validation evidence):

Excitation settings should be chosen as a verifiable operating point inside an error window, not as a fixed “default frequency.” The goal is to pick a band where I is stable and Q remains bounded under the intended probe, cable, and environment.

Frequency controls which error mechanism dominates. Too low, polarization and drift grow; too high, cable capacitance and phase error inflate Q and reduce interpretability. The recommended workflow is validation-driven: sweep a few candidate frequencies in a standard solution, then repeat with the longest expected cable to confirm that Q does not explode.

Amplitude should be large enough to lift I above the noise floor but not so large that the interface becomes nonlinear (seen as worsening drift and Q growth with amplitude). Amplitude selection is therefore limited by both electrochemical behavior and electronics: driver compliance, AFE headroom, and ADC full-scale must not be violated in high-σ or low-K conditions.

Waveform selection must be done from a PSD perspective. A near-sine concentrates energy at the fundamental, simplifying lock-in extraction. Square or multi-tone waveforms can be used, but harmonics interact with frequency-dependent impedance and nonlinearity, creating mixing that contaminates the baseband I/Q estimate. If a non-sine waveform is used, harmonic management (filtering or declared harmonic ratios) becomes part of the measurement specification.

Evidence fields (must be declared in the build spec):

• Excitation: f_exc, amplitude (Vrms/Irms), waveform type (sine / square / synthesized)
• Spectral purity: THD or harmonic ratio target (especially for sine/synthesized)
• Coherence: reference source (shared clock / NCO) and phase-calibration method
• Acceptance: declared I/Q stability criteria (e.g., Q/I threshold) in a standard and with max cable

The analog front-end must preserve linearity, stability, and phase integrity so that lock-in PSD produces interpretable I/Q. Most “mystery drift” and “Q explosions” are caused by TIA instability, leakage, and phase error—not by the conductivity model.

Two sensing styles (what changes in PSD behavior):

• Voltage-sense across a reference element: simpler signal chain, easier headroom planning, but phase is influenced by more parasitics (routing, reference element, and cable return paths).
• Current-mode TIA: converts probe current to voltage at the earliest point, often producing cleaner PSD inputs for small signals, but it is highly sensitive to cable/electrode capacitance, input bias, and leakage.

TIA stability must be treated as a first-class specification. Cable capacitance and electrode interface capacitance act as a load that reduces phase margin. The Rf/Cf network defines the closed-loop pole/zero placement and therefore the ringing risk. Even mild ringing can be interpreted by PSD as quadrature energy, producing false Q growth and misleading phase signatures.

Anti-aliasing strategy: ΣΔ ADCs provide digital filtering, but they cannot prevent strong out-of-band interference from entering the analog path and mixing back into the demodulated band through nonlinearity or overload recovery. A modest analog anti-alias/EMI filter that preserves phase in the demod band is often required to keep I/Q interpretable.

What to measure (PSD-readiness checks):

Lock-in PSD should be treated as a parameterized signal-processing block that outputs a complex response (I + jQ). Correct results require coherent reference generation, defined bandwidth (ENBW), and a repeatable phase calibration procedure.

The core operation is synchronous detection: multiply the sampled signal by a reference sine and cosine at f_exc, then low-pass filter. The in-phase (I) channel captures the component aligned with excitation; the quadrature (Q) channel captures the 90° component. I/Q enables separation of solution-dominant behavior from interface/parasitic dominance, provided the reference is coherent and phase is calibrated.

The demod low-pass filter defines a tradeoff between noise and responsiveness. The effective noise in I is the analog front-end noise integrated over the PSD equivalent noise bandwidth (ENBW). A narrow ENBW reduces noise and improves resolution but slows update rate and transient response. For stable readings, ENBW must be chosen alongside the TIA noise and settling behavior rather than as a fixed digital default.

Evidence fields (must be recorded in validation and specs):

• Demod filter: LPF cutoff, ENBW, update rate, and group delay
• Phase calibration: procedure to minimize Q in a known resistive standard; stored phase offset and residual Q range

ΣΔ ADC configuration must be selected as part of the lock-in measurement system: coherence between f_exc and sampling, predictable group delay, and “quiet” clocking determine whether I/Q is stable and reproducible. High resolution alone does not guarantee phase-correct demodulation.

Coherence planning: ensure the demod reference and the sampled data stay phase-consistent across the observation window. This can be achieved by deriving excitation and demod reference from a shared clock/NCO and selecting an output data rate (ODR) that keeps the observation window aligned to an integer number of excitation cycles. If coherence is broken, energy leaks between I and Q, the effective demod bandwidth broadens, and apparent conductivity “noise” rises even in a stable standard.

Digital filter group delay: ΣΔ ADCs introduce deterministic group delay that depends on decimation and digital filter configuration. The delay itself is not harmful if it is constant and accounted for, but it becomes a phase error when configuration changes occur without re-calibration. Any change to ODR/decimation/filter should be treated as a phase-affecting change that requires I/Q validation or a refreshed phase calibration.

“Quiet” clocking and grounding: clock jitter and ground/clock coupling can masquerade as conductivity change by modulating phase and amplitude. This is most visible when excitation is derived from MCU timers while the ADC clock is sourced differently. A stable clock plan (shared reference, controlled jitter) and clean return paths reduce I/Q wandering and reduce false Q growth under mains interference.

What to measure (integration evidence):

Anti-polarization is a closed-loop control problem: keep the electrode interface within a regime where measurements remain linear and reproducible. Beyond “use AC,” algorithmic actions such as duty cycling and frequency hopping reduce net charge accumulation and expose interface dominance early.

Duty cycling reduces the effective DC bias at the interface by alternating measurement windows with recovery windows. During the pause, interface charge relaxes and drift slope decreases. The tradeoff is update rate: recovery time and ENBW must be planned so that the reported value remains stable while the system avoids sustained polarization.

Frequency hopping (or lightweight multi-frequency probing) improves robustness because interface/parasitic contributions are more frequency-sensitive than solution resistance in the intended operating window. Comparing I/Q across two or three frequencies allows detection of curvature that indicates interface dominance, enabling compensation strategies or a controlled shift to a more stable band.

Electrode health hooks (device-side only): when polarization indicators exceed thresholds, firmware can apply a short recovery action set: hop frequency, pause excitation, or reduce amplitude. If recovery time exceeds a declared maximum, the system flags an electrode health condition instead of silently reporting drifting conductivity.

Evidence fields (algorithm validation and logging):

• Polarization index (PI): declared metric definition (e.g., PI = |Q|/|I|) and thresholds (warn/action/fault)
• Recovery time: time for PI to fall below threshold after excitation pause
• Action log: trigger reason → action taken (hop/pause/reduce) → measured improvement in I/Q

Calibration is the credibility layer: it converts stable, phase-correct I/Q into conductivity (σ) or resistivity (ρ) with traceable configuration, residual-error evidence, and an explicit confidence flag. A meter is only as reliable as its auditable calibration pipeline and its out-of-cal detection.

Two-point vs multi-point calibration: two-point calibration can be adequate for a narrow operating range, but it provides limited visibility into curvature and does not produce a full residual map. Multi-point calibration across standards creates an error profile that can be stored and audited. This residual profile becomes the reference for detecting drift, contamination, or configuration changes that invalidate prior calibration.

Cell constant K estimation and storage: K is a system parameter influenced by cell geometry, electrode condition, and assembly variation. K should be stored with a versioned record (timestamp, excitation conditions, temperature reference) and tracked over time. When K drifts or when the cell signature changes (e.g., cable replacement or contamination), the system should downgrade confidence or declare out-of-cal rather than silently reporting shifted conductivity.

Out-of-cal detection: calibration should include explicit invalidation triggers. Common triggers include residual error exceeding thresholds across standards, day-scale drift slope rising beyond limits, PI/Q behavior indicating interface dominance, and leakage/cable signature shifts that indicate parallel conduction paths. These triggers feed a confidence flag that is output alongside σ/ρ.

What to measure (audit-grade calibration evidence):

An engineering-grade error budget is not a list of causes—it is a mapping from contributor → expected signature → validating test → pass/fail evidence. This section provides a vertical checklist that enables fast root-cause isolation when σ/ρ becomes unstable or biased.

Polarization / interface error: typically worsens at lower excitation frequency and appears as rising Q contribution and phase curvature during sweeps. When interface terms dominate, the system may show stable-looking readings at one frequency but fail across frequency or over time.

Cable capacitance / leakage / contamination: cable length changes primarily affect the frequency-dependent quadrature behavior, while leakage and contamination introduce parallel conduction paths that shift I and drift with humidity. These effects can masquerade as true conductivity change unless signature tests are performed.

ADC noise and reference drift: set the amplitude accuracy and noise floor. Reference drift creates slow bias, while ADC noise integrated over demod ENBW sets the minimum resolvable change. These contributors often look like “random jitter” unless correlated with ENBW and reference telemetry.

Validation plan (explicit, signature-driven):

Field robustness must not corrupt high-impedance measurement integrity. Protection and EMC components are only “correct” when they meet two proofs: (1) low-leakage behavior across humidity/contamination, and (2) minimal phase distortion near the excitation band so I/Q remains valid.

1) Connector-side ESD strategy (placement & return path): place ESD parts at the probe connector so discharge current closes locally to chassis/shield ground. Keep the ESD loop short and wide. Avoid placing clamp devices on the high-Z node side of the front-end; that creates humidity-sensitive leakage paths that look like real conductivity.

• Rule: ESD parts belong on the “connector side” of any series impedance, not inside the guarded high-Z region.
• Rule: add a small series resistor (or RC) only if the phase impact at f_exc is verified (see section 4).
• Rule: dedicate a chassis/shield return for ESD; do not force ESD current through analog ground traces near the TIA/high-Z input.

2) Leakage control (the root cause of “ghost EC”): the meter reads “ghost EC” when an unintended parallel conduction path forms at the connector surface, ESD device leakage, PCB contamination, or cable insulation moisture. These paths are often humidity- and cleanliness-dependent, and they can dominate the measurement even when noise looks low.

3) Shielding vs driven guard (different goals): shielding reduces external electric-field pickup; driven guard reduces parasitic current (cable/PCB capacitance and surface leakage) by keeping the guard conductor near the same potential as the high-Z node. Mis-terminating shield can inject mains/common-mode currents and increase I/Q ripple.

• Shield termination: start with single-end termination to chassis/shield ground at the meter, then validate with the A/B noise test.
• Driven guard: use when cable length/high humidity makes parasitics dominant; verify guard stability and phase impact.

4) Input RC / EMI filtering without phase damage: any RC pole near the excitation band introduces phase rotation that changes I/Q projection. Filters must be designed and verified so the transfer function is “flat enough” (both amplitude and phase) across the excitation band and demod bandwidth. Over-filtering can reduce EMI but silently break calibration.

5) Isolation (only when required): isolation is justified when safety regulations demand it, when large common-mode differences exist between probe and meter, or when ground loops cannot be controlled by shield/return design. Keep scope meter-side: isolation is a boundary to cut common-mode currents, not a full power-supply design topic here.

What to measure (field survivability without ghost EC):

Concrete MPN examples (meter-side, low-leakage oriented):

Each FAQ is a fast triage route: a one-sentence diagnosis, two concrete measurements, one minimal first fix, and a link back to the relevant chapter. The goal is to capture long-tail queries while keeping every answer meter-side and evidence-based.