Emergency Shutdown & Interlock (Fast Latch + Isolation)
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Emergency Shutdown & Interlock ensures a deterministic, fail-safe stop: when a hazard occurs, the system must cut or derate energy within a defined time budget and latch into a known safe state. It also must leave recoverable, auditable evidence (reason codes, timing proof, and black-box records) so the event can be verified and fixed without guesswork.
Emergency Shutdown & Interlock ensures a deterministic, fail-safe stop: when a hazard occurs, the system must cut or derate energy within a defined time budget and latch into a known safe state. It also must leave recoverable, auditable evidence (reason codes, timing proof, and black-box records) so the event can be verified and fixed without guesswork.
Core idea: what an “Emergency Shutdown & Interlock” must guarantee
Emergency shutdown is not “turning the light off”. It is a deterministic safety mechanism that forces energy and actuation into a predictable outcome under worst-case conditions, and leaves an auditable record for recovery and root-cause analysis.
Acceptable by design means the shutdown system must be verifiable against three guarantees (each with measurable evidence):
- Deterministic time — there is a bounded, testable upper limit from trigger to a safe-energy condition (not just “fast”).
- Fail-safe state — the default state under loss of power, broken wires, or controller faults is defined and safe by intent.
- Recoverable evidence — every trip leaves a minimal “black-box” record that supports reconstruction and accountability.
Typical triggers can be grouped so the design and validation plan stays complete:
- Human safety: E-stop, door open, service cover removed.
- Thermal / smoke proxies: over-temperature, smoke/overheat indicators, enclosure sensor alarms.
- Electrical: over-current, over-voltage, driver fault signals, short/open string events (as a trigger, not topology details).
- Control integrity: watchdog, heartbeat loss, brownout, timing supervisor faults.
Allowed shutdown outputs should be defined as behavior levels (to prevent “silent unsafe recovery”):
- Hard trip (latched): immediate lockout until explicit reset conditions are met.
- Soft trip (derate): power/current reduced to a verified safe envelope while still enforcing confirmation.
- Controlled bypass: temporary maintenance override with strict constraints, expiry, and explicit logging.
- Manual reset policy: human-in-the-loop recovery to prevent auto-retries that re-enter hazard conditions.
Minimum evidence fields (the page-wide “evidence contract” used by all chapters):
Figure: A single mental model that anchors the whole page: measurable timing budget, explicit fail-safe states, and a minimal black-box record.
Threat model: what can go wrong if “shutdown” is firmware-only
Firmware can coordinate shutdown, but it should not be the single point that decides safety. In real fixtures, the shutdown path must remain reachable under controller overload, communications failures, and electrical noise—otherwise “commanded off” can diverge from “energy removed”.
Key claim (engineering form): A shutdown design is only as strong as the weakest link in three simultaneous paths:
- Control path (decision): can the trip decision still happen under worst-case compute and timing?
- Signal path (delivery): can the trip signal reach the actuation point under bus faults, wiring faults, or EMI?
- Energy path (reality): does the actuation actually remove energy, and is that removal confirmable?
Failure class A — MCU overload / lockup (control path breaks)
- Why it happens: ISR storms, priority inversion, clock anomalies, memory pressure, watchdog policy delays.
- Typical symptom: shutdown sometimes works in the lab but misses or delays trips under real load.
- Evidence fields to collect: WCET budget vs measured worst-case trip delay; heartbeat-loss-to-latch timing; watchdog reset reason codes.
- Design conclusion: emergency trip must have a hardware fast path (compare + latch) that does not depend on firmware scheduling.
Failure class B — communication loss / bus stuck (signal path breaks)
- Why it happens: packet loss, bus arbitration lock, cable intermittency, address collisions, frozen gateways.
- Typical symptom: an interlock event is detected somewhere, but the command cannot reach the actuator in time.
- Evidence fields to collect: timeout counters, bus error counters, interlock-state bitmap snapshots, last-good message timestamps.
- Design conclusion: interlock must have a local default-safe behavior (wire-level or local hardware gate), not “remote-only” logic.
Failure class C — EMI/ESD & common-mode noise (false trips or missed trips)
- Two risks to balance: nuisance trips (operators bypass safety) vs dangerous failures (trips do not occur).
- Evidence fields to collect: false-trip rate (events per hour / per 10k operations), ESD-trigger statistics, EMI sweep correlation (frequency bands that correlate with trips), line-fault detection counters.
- Design conclusion: interlock inputs require a defined default state, hysteresis, and fault-detect (open/short) so noise cannot silently flip meaning.
Failure class D — single-point faults (a “one-wire” safety story is fragile)
- Examples: comparator input open, trip line shorted, actuator output short, isolation device unpowered, connector oxidation.
- Evidence fields to collect: fault-injection results, state-machine transition logs, mismatch counters (commanded-off vs measured-off), recovery reason codes.
- Design conclusion: define behavior under open/short/loss-of-power and prove it with fault injection, not assumptions.
Practical “pass/fail” framing: The goal is not “zero false trips”. The goal is to minimize dangerous failure probability while ensuring nuisance trips are diagnosable, localizable, and repairable with a clear evidence trail.
Figure: A firmware-only chain breaks at predictable places. The fix is architectural: preserve a hardware-fast, default-safe trip path and confirm energy removal.
Timing budget: how fast is “fast enough”
“Fast” is not a slogan. A shutdown design needs explicit time bounds that remain valid across temperature, supply, load, and noise conditions. The practical target is a measurable timing budget from trigger to a verified safe-energy state.
Step 1 — derive the maximum allowed shutdown time from hazard constraints. Time limits come from physics and exposure windows, not preference:
- Energy constraint: stored energy and backfeed paths can keep current flowing after a control signal changes; the budget must cover the decay tail.
- Thermal constraint: if heating continues after a fault, the budget must limit additional energy injection before temperatures cross a safe envelope.
- Optical exposure constraint: for intense light sources, the budget must limit hazardous exposure duration; the safe state must be provable, not assumed.
- Touch/access constraint: door-open interlocks must reach a safe-energy state before the system becomes physically accessible.
Step 2 — decompose latency into a worst-case, additive chain. The timing budget is the sum of bounded delays across the full shutdown path:
- Sensor response and conditioning delay
- Compare propagation and decision delay
- Latch set/hold establishment
- Isolated actuation delivery to the shutdown point
- Power-stage response and energy decay to a measurable safe threshold
Step 3 — define three time bounds with different meanings. A single “shutdown time” metric hides failure modes:
- Trip time: trigger → latch set (decision is locked in).
- De-energize time: latch set → energy is actually removed (e.g., current drops below a safe threshold).
- Safe-confirm time: trigger → system can reliably assert “safe” and move to a controlled recovery state.
Evidence fields (measurement-ready): define measurement points and compute bounds from real waveforms, not estimates.
Validation rule: budgets must hold under corners (hot/cold, high/low supply, load extremes) and under injected disturbances (ESD/EMI) without turning into nuisance trips. A design that meets timing only in nominal conditions is not deterministic.
Figure: A measurement-first timing budget. Define waveform points (T0–T4), compute trip/de-energize/safe-confirm, then prove bounds under corners.
Fast compare & latch: the hardware “decision core”
A shutdown path becomes deterministic when a hardware decision core converts analog conditions into a clean trip event, remembers it as a latched state, and only allows recovery through an explicit reset policy. This avoids reliance on firmware timing and bus availability.
1) Compare: convert “analog reality” into a stable event. Different front ends exist to address different field failure modes:
- Comparator (single threshold): best for clear hard limits (over-current/over-temp). Needs hysteresis or filtering to avoid chatter.
- Window comparator: detects “out of allowed range” and helps catch sensor/wiring faults (floating inputs, bias drift, missing reference).
- Schmitt input (hysteretic threshold): stabilizes slow/noisy edges (long interlock cables, mechanical contacts, post-ESD recovery).
2) Latch: make short events impossible to ignore. Latching choices differ mainly by behavior under clock/power anomalies:
- SR latch (asynchronous): locks immediately without a clock; fits emergency trip paths where timing must be bounded even during clock faults.
- D flip-flop (synchronous): aligns to a clock domain; requires the clock’s health to be part of the safety argument.
- Supervisor-integrated latch: compact and consistent; must be verified for default state, propagation delay, and reset semantics.
3) Reset policy: recovery is part of safety, not convenience. A robust design prevents oscillation and unsafe auto-retry:
- Manual reset: preferred where human safety is involved; requires explicit operator action after inspection.
- Timed reset: acceptable for transient conditions only when bounded attempts, backoff, and evidence capture are enforced.
- Two-step reset: separates “clear request” from “safe-confirm true” to prevent re-energizing before the energy path is proven safe.
4) Debounce & filtering: keep the hardware trip path reachable. Filtering can exist, but must not make firmware scheduling the only gate:
- Analog conditioning (RC + hysteresis) cleans inputs without depending on CPU timing.
- Digital debounce can reduce nuisance trips, but the “hard trip” path must remain available under overload and bus faults.
- Over-filtering risk: a large debounce window silently expands trip time and breaks the timing budget defined in H2-3.
Evidence fields (audit-ready):
Figure: A decision core that stays reachable under firmware overload: conditioned inputs → comparator family → latch semantics → reset policy loop.
Interlock chain architecture: series, voting, and bypass (without breaking safety)
An interlock is not a single wire. It is a chain system whose topology determines three outcomes: deterministic trips, fault localization, and controlled bypass without turning safety into a permanent loophole.
1) Series loop (simple, but hard to localize). The classic series loop is clear in behavior—any open triggers a trip—but it is weak in maintainability.
- Strength: minimal wiring, minimal logic, unambiguous “loop open → trip”.
- Limit: poor localization—only “somewhere is open” is known; field troubleshooting becomes slow and expensive.
- Hidden risk: repeated nuisance trips increase the chance of an operator bypassing safety to keep the fixture running.
2) Zoned interlock (structure for serviceability). Zoned designs split the chain into maintainable segments (doors/modules/compartments) so faults are localized by design.
- Benefit: a trip can be mapped to a specific zone/segment rather than an unknown location.
- Operational advantage: fewer “blind resets”; faster repairs reduce the temptation to bypass.
- Design rule: every zone must define default behavior under open wire, short, and loss of local power (fail-safe semantics).
3) Voting / redundancy (when fault tolerance or robustness is needed). Voting is not a checkbox; it is an explicit tradeoff between nuisance trips and dangerous misses.
- 1oo2: either channel can trip. Useful when “do not miss” dominates; requires strong evidence and localization to keep nuisance trips manageable.
- 2oo2: both channels must agree. Useful when nuisance trips are extremely costly; requires self-check and fault detection to avoid silent misses.
- Practical framing: voting choice must align with hazard class and field maintainability, not only lab behavior.
4) Bypass philosophy (only in controlled states). Bypass should exist only as a constrained, auditable maintenance action—never as an invisible permanent setting.
- Mode-gated: only allowed in Maintenance / Service modes.
- Time-bounded: auto-expire (TTL) to prevent “forever bypass”.
- Derated: reduced power envelope while bypass is active.
- Logged: who enabled it, for how long, why, and whether it auto-expired.
Evidence fields (audit + service ready):
Figure: Series loops trip reliably but localize poorly; zoned designs turn localization into a system feature; voting adds robustness, while bypass must remain mode-gated, time-bounded, and logged.
Isolated actuation: moving the shutdown action across an isolation barrier
Isolated actuation transfers a shutdown decision across an electrical boundary while preserving fail-safe behavior under wiring faults, ground potential differences, and loss-of-power scenarios. The goal is consistent shutdown semantics across control and power domains.
Why isolation is used (practical drivers):
- High-voltage boundaries: separation between low-voltage control logic and high-energy power domains.
- Long cables: cable coupling and induced noise can corrupt a non-isolated trip signal.
- Common-mode noise: high dv/dt environments shift references and can cause false or missed triggers.
- Ground potential differences: different earth points and chassis grounds can distort logic thresholds.
Actuation targets (where shutdown is enforced): choosing an actuation point is a semantic decision; each target must support confirmation that energy is truly removed.
- Gate inhibit / driver disable: fast and controllable; must avoid “logic-off but energy-on” scenarios via energy-off confirmation.
- EN pin pull-down: simple inhibition path; must define default behavior when the output side loses power.
- Relay / SSR: clear physical disconnection; requires attention to release time and contact/drive failure modes.
- Primary-side shutdown: removes energy at the source; recovery behavior must remain controlled and logged.
Reliability principles across the barrier: isolated shutdown is only “safe” when default, loss-of-power, and fault states are defined and provable.
- Default state: the expected output state under normal operation and under asserted trip.
- Loss-of-power state: what happens when the isolator or output-side supply disappears.
- Fault state: open/short on the input, stuck-high/low output, or degraded isolation must map to a safe outcome.
Evidence fields (fail-safe semantics):
Figure: Isolated actuation is a structured boundary. Control-domain trip semantics must survive noise, ground shifts, and loss-of-power, and the output must be defined by a fail-safe truth table.
“Fault bypass” done right: serviceability without creating a backdoor
Fault bypass is a controlled risk operation. It exists to restore serviceability under a defined envelope, not to silently remove protection. A correct design binds bypass to strong gating, automatic expiry, derating, and an audit trail that survives power cycles.
1) Three bypass levels (increasing strictness). Each level must have a distinct semantic boundary and evidence requirements.
- Diagnostic bypass: short, guided isolation for troubleshooting; the hard trip path remains reachable.
- Limited operation: restricted service continuity with an enforced derating profile and tighter monitoring.
- Hard override: last-resort operation under strong physical gating and shortest TTL; typically requires manual reset and explicit confirmation.
2) Non-negotiable bindings: token + timeout + derating. Removing any one of them turns bypass into a backdoor.
- Bypass token: physical key / jumper / authorization code, bound to role and purpose.
- Timeout (TTL): auto-expiry with a defined post-expiry behavior (exit bypass or enter safe stop awaiting confirmation).
- Derating profile: a profile ID that caps current/power/temperature and optionally limits duration while bypass is active.
3) Monitoring must be stronger during bypass. Bypass should increase observability and tighten thresholds, not relax them.
- Thermal: tighter temperature limits and higher sampling rate.
- Current / power: caps enforced by profile; excursions trigger immediate trip.
- Enclosure / interlock state: zone/door status must remain visible; bypass scope must be explicit.
- Time window: renewals, expiry, and cancellations must be recorded as events.
Evidence fields (audit-ready):
Figure: A safe bypass is gated (token + mode), bounded (TTL), constrained (derating), and compensated (enhanced monitoring), with every transition recorded as an auditable event.
Black-box records: what to log so you can prove what happened
A black-box is an auditable evidence chain, not “more logs”. It must answer: what happened, why it happened, and what the system did under the active policy (including bypass).
1) Event model: evidence is a time-structured chain. Use three record classes so analysis does not rely on assumptions:
- Pre-trip snapshots: short-window samples immediately before a trip (2–4 key signals, repeated samples).
- Trip event: the definitive record (reason code + interlock bitmap + sequence number + policy context).
- Recovery event: how the system returned (manual reset / expiry exit / reboot), including confirmation status.
2) Minimal field set (schema-oriented). Keep records small but complete enough for causality and compliance:
| Field group | Required fields | Purpose |
|---|---|---|
| Header | sequence_number, record_type, timestamp_local, timestamp_relative | Ordering that survives reboots and power loss |
| Cause | reason_code (enum) | Explains why the trip occurred |
| State | sensor_snapshot (2–4), interlock_bitmap, bypass_status | Captures the system context at decision time |
| Policy | firmware_version, config_hash, derating_profile_id | Proves the active policy and envelope |
| Integrity | crc, integrity_check_result | Detects corruption and supports auditability |
3) Storage strategy (principles). Preserve evidence under continuous operation and brownouts.
- Ring buffer: bounded storage with predictable retention.
- Power-fail safe commit: two-stage write (write → verify → mark valid) to avoid half-records.
- Priority retention: trip/recovery records should not be overwritten by low-priority telemetry.
- Export/readout path: records must be retrievable with sequence ranges and integrity status.
Evidence fields (audit anchors):
Figure: Evidence is a chain: pre-trip snapshots → trip event → recovery event. Records follow a schema with monotonic sequence numbers, and storage uses ring retention plus power-fail safe commit and integrity checks.
Confirming the shutdown: how to avoid “it says off, but it’s still on”
Many incidents come from confusing a commanded-off state with a measured-off state. A shutdown is complete only when an off-command is followed by verified energy-off measurements within a bounded time window.
1) Dual confirmation model: commanded-off + measured-off. The off-command proves intent; measurement proves energy removal.
- Commanded-off: the system issues a shutdown command to an actuation target (gate inhibit / EN pull-down / relay open / primary-side off).
- Measured-off: independent probes confirm that energy has actually disappeared, not merely that a control pin changed state.
- Mismatch handling: when command and measurement disagree, the system must escalate (latch fault, trigger a secondary kill path, and record evidence).
2) Key confirmation points (choose at least two independent probes). Avoid single-point “off” proof.
- LED current → 0: strongest direct evidence that emission-driving energy is gone (ensure bandwidth and threshold are defined).
- Output voltage decay: track the decay curve after shutdown; unexpected plateaus imply stored energy or backfeed.
- Gate/driver disable state: confirms the switching path is inhibited and not re-enabled by glitches or resets.
- Relay feedback: contact/driver feedback helps distinguish “commanded open” from “physically open”.
3) Counterintuitive “false off” causes. These are common reasons energy persists after an off-command.
- Stored energy: reservoir capacitors and output filters keep voltage alive longer than expected.
- Parasitic powering: protection structures and signal paths can unintentionally feed a domain that “should be off”.
- Backfeed paths: other rails, interfaces, or parallel modules can re-energize nodes through unintended routes.
Evidence fields (verification-grade):
Figure: Dual confirmation uses an off-command plus independent measured-off probes. Timeout and mismatch counters ensure that “logic says off” cannot silently become “energy still present”.
Noise immunity & false trips: designing interlock signals to survive EMC/ESD
This section focuses only on the interlock signal path. The goal is deterministic behavior under EMC/ESD without expanding into full compliance design. Robustness comes from default-state definition, input conditioning, and line-fault detection—plus measurable nuisance-trip metrics.
1) Wiring layer: default states that fail safe. Long cables and shared grounds turn interlock wires into antennas unless their semantics are defined.
- Default state: pull-up/pull-down defines what happens on open wires and during brownouts.
- Reference strategy: define return/reference paths so thresholds remain meaningful under ground shifts.
- Long-line reality: treat coupling and induced transients as expected, not exceptional.
2) Input layer: RC + hysteresis + clamp + debounce as a combined stack. Each layer addresses a distinct failure mode.
- RC: attenuates fast spikes but adds delay; its cutoff must respect the shutdown timing budget.
- Hysteresis: prevents threshold chatter and converts noise into bounded behavior.
- Clamp: limits ESD/overshoot so the receiver does not misbehave or get damaged.
- Debounce: for slow/mechanical inputs; avoid masking genuine fast hazards by preserving the hardware trip path.
3) Line fault detection: distinguish noise from wiring failures. Robust chains detect opens and shorts explicitly rather than misclassifying them as normal states.
- Open wire: treated as a defined fail-safe state (usually trip), with a distinct fault code.
- Short-to-GND: detected and recorded as a wiring fault, not a valid asserted state.
- Short-to-VCC: detected similarly; prevents a stuck-high line from hiding a dangerous condition.
4) Tradeoff: nuisance trips vs dangerous misses. The design must choose an explicit operating philosophy and prove it with data.
- Fail-safe bias: more nuisance trips may be acceptable when hazards are severe.
- Continuity bias: fewer nuisance trips may be required for availability, but only if stronger diagnostics and evidence exist.
- Measure it: express nuisance trips as a rate and record EMI/ESD triggers by condition.
Evidence fields (test + field metrics):
Figure: Interlock robustness is a stack: define wiring default states, condition inputs (RC/hysteresis/clamp/debounce), detect line faults, and quantify nuisance trips with ESD/EMI metrics and false-trip rate.
Validation playbook: what to test and how to capture proof
Validation is complete only when every shutdown/interlock trigger has a repeatable Test ID, a waveform/log proof bundle, and a clear pass/fail criterion. This playbook focuses on engineering execution: test matrix, corner coverage, fault injection, noise sanity checks (interlock path only), and forensic integrity under power loss.
0) Recommended lab setup (example MPNs). Use equivalent parts if the voltage/current class differs. MPNs below are common and widely available references.
| Category | Purpose | Example MPNs | Notes |
|---|---|---|---|
| Oscilloscope | 3-point timing proof (TRIG / LATCH / ENERGY) | Tektronix MDO34, Keysight MSOX3054T, R&S RTO series | 4+ channels; save screenshots + waveform data |
| Current probe | Confirm I_LED → 0 and decay shape | Tektronix TCP0030A, Keysight N2820A | Pick bandwidth/peak current to match the driver |
| High-voltage diff probe | Measure Vout decay safely | Tektronix TDP0500, Keysight N2791A | Use rated probes for HV LED strings/PSU nodes |
| Logic analyzer | Capture GPIO/interlock bitmaps + bus lockups | Saleae Logic Pro 16 | Helpful for “comm stuck vs MCU alive” proofs |
| Load / LED emulator | Repeatable load corners without optical uncertainty | Chroma 6314A (DC load), BK Precision 8600 series | Use an LED string emulator if available; otherwise controlled DC load |
| Power supply | VIN min/nom/max corners + brownout injection | Keysight E36313A, R&S NGU series | Add series MOSFET or relay for fast drop tests if needed |
| Power-fail injector | Drop VIN at defined edge to test log commit | Pickering 40-142 (relay modules), Omron G5LE (basic relay) in fixtures | Module choice depends on voltage/current; fixture design must be safe |
| ESD gun | Interlock sanity under ESD (stats) | EM Test ESD NX30, Teseq/Schaffner NSG 435 | Only track “interlock correctness”, not full EMC certification |
| EFT/Burst | EFT sanity (interlock path stability) | EM Test UCS 500N, Haefely ONYX series | Use coupling clamps appropriate for harness |
| Surge | Surge sanity (no spurious latch / no missed latch) | EM Test UCS 200N, Haefely PSURGE series | Focus on interlock correctness + evidence capture |
| Environmental chamber | Cold/room/hot corners for timing | ESPEC SU series, Thermotron SE series | If no chamber: controlled hot plate + cold spray is inferior but workable |
1) Test ID system (traceability backbone). Use a stable ID so waveforms, logs, and conclusions always line up.
- Functional:
ESI-FUNC-xx(each trigger source → correct latch/action/reset) - Timing corners:
ESI-TIME-xx(trip/de-energize/safe-confirm across T/VIN/load) - Fault injection:
ESI-FAULT-xx(open/short/isolation loss/MCU hang/comm stuck) - Immunity sanity:
ESI-IMMU-xx(ESD/EFT/surge → interlock correctness only) - Forensics:
ESI-FORE-xx(power-fail log integrity, sequence continuity, CRC)
2) Proof package layout (repeatable archiving). Keep a predictable folder structure so evidence can be audited later.
| Path | Contents | Required items |
|---|---|---|
/proof/ESI-TIME-03/ |
One test ID = one folder | README (setup), result.txt (pass/fail) |
/proof/ESI-TIME-03/scope/ |
Waveform screenshots + optional CSV | 3-point timing screenshot |
/proof/ESI-TIME-03/logs/ |
Log dump (binary + decoded) | seq range + CRC/verify status |
/proof/ESI-TIME-03/notes/ |
Corner conditions and anomalies | VIN/T/load + fixture notes |
3) Screenshot naming rule (machine-sortable). Encode test + corner + channels in the file name.
- Example:
ESI-TIME-03__VINmax_THOT_LoadHi__CH1_TRIG_CH2_LATCH_CH3_ILED.png - Minimum: include Test ID, corner tag (VIN/T/load), and channel mapping (TRIG/LATCH/ENERGY).
4) Test matrix (execution-oriented). Each row points to a proof bundle and a numerical pass/fail criterion.
| Test group | Test ID examples | What to test | Pass/Fail criterion | Proof required |
|---|---|---|---|---|
| Functional | ESI-FUNC-01..08 |
Each trigger source must enter the correct latch state and output action (cut/derate/bypass/hold reset) | Correct reason code + correct output state + correct reset policy | Trip log + interlock bitmap + action confirmation |
| Timing (corners) | ESI-TIME-01..06 |
Trip time, de-energize time, and safe-confirm time across temp/VIN/load corners | All times ≤ budget at cold/room/hot and VIN min/nom/max | 3-point scope screenshot + summary table |
| Fault injection | ESI-FAULT-01..10 |
Sensor open/short, isolation loss, MCU hang, comm stuck → safe outcome with distinct codes | Fail-safe action + distinct fault classification + no silent recovery | Fault method note + log + waveform/state |
| Immunity sanity | ESI-IMMU-01..05 |
ESD/EFT/surge: interlock correctness (no random latch, no missed latch) | False-trip rate within limit; no dangerous miss in defined scenarios | Stats log + breakpoint notes + counters |
| Forensics | ESI-FORE-01..06 |
Power-fail during events: log completeness, monotonic seq, CRC correctness | No half-records; seq never rolls back; CRC/verify passes | Log dump + verify report + seq range |
5) Corner plan (minimum set). The goal is to expose worst-case delay and “energy still present” scenarios.
- Temperature: cold / room / hot
- Input voltage: VIN min / nominal / max
- Load: low / nominal / high (include long harness or capacitive load if relevant)
- Repetition: run each timing test ≥ 5 times; record min/typ/max
Evidence fields (must appear in every proof bundle).
Figure: A validation proof pipeline ties each Test ID to instrumentation outputs, numeric criteria, and an archived proof bundle (scope + logs + integrity evidence) for auditability.
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FAQs (Troubleshooting-ready, evidence-linked)
Each answer follows a fixed field-proven format: 1-sentence conclusion + 2 evidence checks + 1 first fix. Each FAQ links back to the relevant chapters so readers can validate with the same evidence fields (timing, mismatch counters, interlock bitmaps, and log integrity).
Figure: A repeatable FAQ workflow that forces every answer to cite two evidence checks and a smallest-possible first fix, then re-test using the same timing and logging fields.
1
Emergency stop sometimes works, sometimes doesn’t—firmware latency or hardware path?
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Conclusion: Intermittent E-stop behavior is usually a timing-budget violation in the software path, or a noisy/undefined hardware trip input.
Evidence 1: Capture a 3-point scope shot: trigger edge → latch/kill output → energy-path change; compare worst-case delay against the H2-3 budget.
Evidence 2: Check MCU load/WCET vs the measured trip time and confirm the comparator/latch propagation delay is stable.
First fix: Route E-stop through a dedicated fast comparator + latch path (e.g., TLV3201 or LTC6752) and keep firmware as a secondary reporter.
2
False trips during ESD—hysteresis issue or wiring reference problem?
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Conclusion: ESD-driven nuisance trips are most often caused by a floating reference/return path or insufficient input hysteresis/clamping.
Evidence 1: Record ESD trigger statistics and correlate with line length/grounding; a strong correlation points to wiring/reference issues.
Evidence 2: Measure the interlock input waveform during ESD; if it crosses threshold briefly, hysteresis/RC/clamp is under-designed.
First fix: Define a deterministic default pull state and add clamp + hysteresis at the receiver (e.g., SN74LVC1G17 Schmitt buffer or a comparator with hysteresis).
3
It latches off but won’t recover—reset policy too strict or interlock still open?
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Conclusion: Non-recovery is usually a still-open interlock segment or a reset policy that requires a condition never met in the field.
Evidence 1: Inspect the interlock state bitmap and chain map; a persistent open segment should be visible and repeatable.
Evidence 2: Verify the latch set/reset truth table and the manual/timed/two-step reset conditions against real sensor states.
First fix: Add a “reset-ready” gate that requires all interlock segments closed for N ms before reset, and log a “reset blocked” reason code.
4
Bypass fixed maintenance, but safety team rejects it—what’s missing?
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Conclusion: A bypass is rejected when it lacks bounded authorization, automatic expiry, and a provable derating/monitoring policy.
Evidence 1: Check whether a bypass token includes source, scope, and TTL, and whether logs record who enabled it and for how long.
Evidence 2: Confirm derating profile enforcement during bypass and verify enhanced monitoring alarms (temp/current/enclosure).
First fix: Bind bypass to a physical key/jumper + TTL + derating curve, and store the bypass record in a tamper-evident log (e.g., FRAM MB85RC256V).
5
Log shows “over-temp” but temperature is normal—sensor fault or threshold mapping?
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Conclusion: “Over-temp” with normal readings is commonly a sensor-open/short or a configuration/lookup mapping mismatch.
Evidence 1: Compare pre-trip sensor snapshots (raw ADC, converted °C, and threshold ID) against the reason code; mismatches indicate mapping issues.
Evidence 2: Run fault injection (open/short) and confirm the system distinguishes “sensor fault” from true over-temp with separate codes.
First fix: Add line-fault detect for the sensor input and log raw ADC + config hash at trip; use a robust temp sensor interface (e.g., TMP117 for digital sensing).
6
System says OFF, but LED still glows—residual energy or backfeed path?
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Conclusion: A dim “still on” glow after OFF is usually residual energy in output capacitance or a backfeed/parasitic power path.
Evidence 1: Check the residual energy decay curve (Vout and/or I_LED) against the expected time constant; plateaus suggest backfeed.
Evidence 2: Inspect the mismatch counter: commanded-off is true but measured-off never reaches threshold before the off-confirm timeout.
First fix: Add a defined discharge path and enforce measured-off confirmation; if backfeed is suspected, isolate suspect interfaces and retest with the same decay capture.
7
Isolation barrier resets during surge—actuation path or default state wrong?
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Conclusion: Surge-induced resets typically reveal a fail-unsafe default state or an isolation/control path that does not hold the safe output on loss of power.
Evidence 1: Validate the fail-safe truth table: what output state occurs when the isolator side loses power or the input is disconnected?
Evidence 2: During surge tests, log barrier-side brownout/reset flags and correlate with any “missed trip” or unexpected re-enable events.
First fix: Choose an isolator with defined output behavior and add a hardware pull-to-safe on the output side (e.g., isolator ISO7721 + pull-down on EN).
8
Interlock chain is hard to debug—how to localize which segment opened?
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Conclusion: If the chain cannot be localized, the interlock architecture likely lacks zoning and per-segment state visibility in logs.
Evidence 1: Review the chain map and confirm whether segments are separately observable (zoned loop vs single series loop).
Evidence 2: Check whether the black-box record includes an interlock state bitmap at trip and during recovery attempts.
First fix: Add zoned interlocks with per-zone inputs (or encoded resistive states) and log a per-zone bitmap; consider a protected input expander (e.g., TCA9535) on the logic side.
9
Trip time meets spec at room temp, fails hot—prop delay drift or power stage response?
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Conclusion: Hot failures usually come from temperature-dependent propagation delay in the decision path or a slowed power-stage de-energize response.
Evidence 1: Split the timing: measure trigger→latch edge (decision path) and latch→energy-off (power stage response) across temperature corners.
Evidence 2: Compare hot vs room mismatch counters and confirm whether de-energize time grows while trip time remains stable.
First fix: Reduce decision-path uncertainty (use faster comparator/latch) and retune the shutdown actuation to cut energy faster; validate with H2-11 corner repetition.
10
After power loss, black-box record is corrupted—commit strategy or CRC handling?
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Conclusion: Corrupted records after power loss typically indicate non-atomic commits or missing integrity checks rather than “random memory failure”.
Evidence 1: Verify sequence continuity and CRC/verify status across the power-fail window; half-records or rollbacks indicate commit weakness.
Evidence 2: Re-run a controlled power-drop test and check whether a “commit complete” marker is present before the record is accepted.
First fix: Implement two-phase commit (write → CRC → commit flag) and store logs in non-volatile memory designed for frequent writes (e.g., FRAM MB85RS64V).
11
Multiple faults occur together—how to prioritize reason codes?
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Conclusion: Reason code priority should favor the earliest hazard-defining event, while still capturing secondary faults in snapshots for debugging.
Evidence 1: Compare pre-trip snapshots against the recorded primary reason; the primary code should match the first threshold crossing in time.
Evidence 2: Confirm sequence number ordering: multiple sub-events should appear as a chain, not overwritten by later noise.
First fix: Define a priority table (hazard-first), log secondary flags in the same record, and freeze snapshots at latch time to prevent post-trip noise from rewriting history.
12
How to prove to auditors what happened without full telemetry?
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Conclusion: Auditable proof does not require full telemetry; it requires a minimal, consistent event schema with integrity and traceable test evidence.
Evidence 1: Ensure each trip record contains timestamp (or relative time), reason code, key sensor snapshot, interlock bitmap, bypass status, and firmware/config hash.
Evidence 2: Provide a validation bundle: Test ID, waveform screenshot naming, log dump location, and CRC/verify report proving record integrity.
First fix: Standardize the log schema and add monotonic sequence numbers plus integrity checks; store in robust NVM (e.g., AT25SF641 SPI NOR or FRAM).
