RTD / Thermocouple Transmitter Design Guide
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RTD / thermocouple transmitters turn microvolt- and milliohm-level sensor signals into a stable, loop-powered 4–20 mA temperature output by controlling the entire error chain—excitation/CJC, low-noise gain, 24-bit conversion, linearization, and field-hardened diagnostics.
This page focuses on measurable proof (error budget, noise/settling, ΔTemp under EMI, and fault-response behavior) so accuracy claims can be validated, not guessed.
H2-1. Page purpose and “who this is for”
Extractable answer block: An RTD / thermocouple transmitter converts milli-ohm or micro-volt sensor signals into a stable, long-cable output (typically 4–20 mA). Accuracy is defined by excitation/reference stability (RTD), low-noise gain and drift (RTD/TC), and cold-junction compensation placement (TC). A “good” transmitter proves performance with an error budget, noise/settling evidence, and a deterministic fault behavior map.
What this page teaches
- How the full measurement chain is partitioned (sensor wiring → protection/bias/excitation → low-noise gain → 24-bit ADC → digital linearization → loop DAC/current output).
- Why thermocouple CJC is a system problem (connector temperature tracking, thermal gradients, placement evidence), not just an algorithm checkbox.
- How 4–20 mA loop power back-constrains the design (power budget, compliance headroom, and fail-safe current behavior that must remain deterministic under stress).
What can be proven at the bench & in the field
- Error budget closure at defined temperature points (RTD/TC + CJC + drift + output stage), with traceable assumptions.
- Noise and settling evidence (input-referred RMS/p-p and step response to a temperature-equivalent window).
- Fault detection matrix (open/short/out-of-range/reference/ADC saturation) mapped to loop current behavior + diagnostic codes/log fields.
Every later chapter must tie back to at least one measurable evidence field (error, noise, settling, compliance, fault determinism). This prevents scope creep and turns the page into a build-and-verify checklist rather than a narrative.
H2-2. Requirements first: define the measurement contract
A transmitter design becomes “deterministic” only after the measurement contract is pinned down. This contract prevents hidden assumptions (wire resistance, ambient gradients, loop headroom, EMI) from turning into unexplained drift in the field. Each downstream block (excitation, gain, ADC, firmware, output) must map back to one or more contract fields below.
| Contract field | What must be specified (no ambiguity) | What must be proven (evidence) |
|---|---|---|
| Sensor + wiring model |
RTD: 2/3/4-wire, nominal R (e.g., PT100/PT1000), cable length and lead symmetry expectations. Thermocouple: type family (K/J/T/N/R/S/B), connector style, expected gradients near terminals. |
Wiring sensitivity test (lead mismatch or connector gradient) converted into temperature-equivalent error. |
| Accuracy targets |
Separate static (total error at defined points) from dynamic (time to settle into an error window after a step). State “noise-free” temperature resolution, not “24-bit” marketing. |
Error table at points (e.g., −40/0/100/200°C), plus step response to within a target band (e.g., 0.1°C). |
| Update rate & latency | Required update rate (Hz) and maximum allowed latency, including line-frequency rejection expectations (50/60 Hz). | Plot or table: update rate vs filter/OSR setting; line-frequency interference rejection vs latency. |
| EMI/ESD/surge reality | Cable class (shielded/unshielded), installation environment, expected common-mode shifts, and stress events (EFT/surge/ESD). Define whether “no reset” is enough, or whether no offset shift is required after events. | Temperature reading delta during/after stress (ΔT), recovery time, and any permanent offset shift record. |
| 4–20 mA loop constraints | 2-wire loop-powered vs 3/4-wire, supply range, loop resistance range, and compliance voltage at 20 mA. Define fail-safe current behavior (fault currents and saturation behavior). | Compliance margin report across loop resistance; power budget margin; deterministic fault-to-current mapping + logs. |
(1) Total error at defined points, (2) input-referred noise (RMS/p-p), (3) update rate vs filter setting (latency), (4) loop compliance margin. Every later section must contribute at least one of these fields to remain vertically scoped and testable.
H2-3. System architecture: two canonical chains (RTD vs Thermocouple)
This page treats a transmitter as a deterministic signal chain whose blocks each own a specific error type. The architecture below is the “map” used by later chapters: every claim about accuracy, noise, settling, or diagnostics must tie back to a block and to a measurable evidence field.
Two chains, one shared backbone
- RTD chain: precision current source → RTD wiring & sense → instrumentation gain → 24-bit ADC → digital linearization → loop DAC / current output.
- Thermocouple chain: TC input → low-noise differential gain → 24-bit ADC → CJC sensor + gradient handling → linearization → loop DAC / current output.
The bottom “error tags” indicate where specific failures originate (drift, leakage, gradients, headroom). Later chapters pick one block, reduce one class of error, and output a corresponding proof (error@points, input-noise, settling, compliance, fault determinism).
H2-4. Input front-end & protection: don’t let the field ruin your ppm
Input protection for RTD/TC transmitters must be evaluated by the post-stress offset and drift, not only by survival. Real installations introduce long cables, ground shifts, and RF energy; the front-end must provide a controlled bias return path while keeping leakage and capacitance from turning into temperature-equivalent error.
Design questions that keep the chain deterministic
- Where is the protection boundary? Terminal-side protection reduces trace stress; AFE-near protection shields IC pins but may leave the trace exposed. Placement is a trade between survivability and offset risk.
- What leakage is acceptable across temperature? Micro-volt measurement turns leakage into offset drift. Any clamp element must be judged by leakage(T), not only by voltage rating.
- What is the bias return strategy? Input bias currents require a defined return path; uncontrolled paths (humidity/contamination dependent) appear as temperature-dependent offsets.
- What common-mode and ground shift is expected? “Acceptable CM range” means the AFE remains linear and unsaturated across the expected field CM swing and still meets error@points.
- How do filtering and settling coexist? Cable-induced 50/60 Hz and RF ingress demand RC/filters, but the contract also sets a latency limit. Filtering must be coordinated with settling targets.
| Risk mechanism | What it looks like in the field | Proof to collect |
|---|---|---|
| Leakage(T) | Readings drift with ambient; “bench OK, enclosure wrong.” Often appears as a slowly moving zero. | Offset vs temperature sweep with input shorted/known source; translate to °C-equivalent error. |
| Post-stress shift | After surge/ESD/EFT, device runs but zero moved; intermittent complaints are hard to reproduce. | Pre/post stress comparison: Δoffset and recovery time; declare pass/fail by ΔT-equivalent threshold. |
| RC vs settling | Noise improves but response becomes sluggish; loop output lags real temperature changes. | Step response after input RC: time to settle within a defined band (e.g., 0.1°C equivalent). |
| CM pickup | Readings jump when nearby loads switch; ground shift causes saturation or rectified offsets. | CM sweep or injected interference test: verify linearity and no saturation across expected CM range. |
Pass criteria should be stated in measurement units (°C-equivalent error, settling time, compliance margin), not only in “did not reset.” This keeps protection design aligned with the transmitter’s accuracy contract.
H2-5. RTD excitation: precision current sources that don’t self-heat or drift
RTD accuracy is dominated by how excitation is generated, routed, and budgeted. Excitation must stay stable across temperature, provide enough compliance headroom at the highest RTD resistance, and avoid turning sensor power into a hidden thermal error. This section defines a practical decision framework and the minimum evidence needed to prove an excitation design is deterministic.
5.1 Excitation modes: when constant current wins vs ratiometric
- Constant current simplifies the analog path and calibration flow, but total error becomes sensitive to excitation initial accuracy and tempco. It is strongest when excitation stability is provable and power headroom exists.
- Ratiometric measurement attempts to cancel excitation and reference drift by measuring ratios (e.g., RTD vs reference element). It is strongest when the system can keep the ratio path matched and when drift must be suppressed across wide ambient changes.
- Decision rule: choose the mode that converts the largest uncertainty in the contract into a measured ratio or a calibrated constant, rather than leaving it as an uncontrolled drift term.
5.2 Self-heating budgeting: keep it practical and testable
Self-heating is the simplest “accuracy trap” because it looks like the sensor is correct but the measured temperature is not the environment. A minimal budget uses three linked quantities: RTD power (P ≈ IEX2·R(T)), temperature rise (ΔT ≈ P·θ), and allowed thermal error from the measurement contract. The excitation current must be set so ΔT stays inside the allowable error window for the worst-case mounting and airflow condition.
5.3 Lead resistance & wiring: what must be measured (not assumed)
- 2-wire: lead resistance adds directly to the RTD reading; the chain cannot distinguish lead change from temperature change without extra measurement steps.
- 3-wire: compensation relies on lead symmetry; mismatch becomes a residual error that must be bounded by test (inject mismatch and observe °C-equivalent shift).
- 4-wire: separates force and sense to cancel lead resistance, but increases sensitivity to input bias paths and leakage that can convert to offset drift (tie back to H2-4 evidence).
5.4 Current source error components: turn them into a budget table
| Error component | Why it matters in an RTD transmitter | Proof to collect |
|---|---|---|
| Initial accuracy | Sets baseline gain error in the RTD-to-temperature conversion; must be calibratable or inherently stable. | Measure IEX vs known loads; report initial error and post-calibration residual. |
| Tempco / drift | Shows up as ambient-dependent temperature shift even when the sensor is stable. | IEX(T) sweep in a chamber; translate to °C-equivalent contribution in error@points. |
| Noise | Converts into temperature jitter and limits noise-free resolution; affects deep filtering and latency tradeoffs. | Input-referred noise measurement with excitation enabled vs disabled; compare RMS and 1/f region. |
| Compliance headroom | If headroom is insufficient at high R(T)+Rlead, excitation clips and the chain becomes nonlinear (curve shape changes). | Worst-case resistance sweep (including lead resistance); report the onset point of current clipping and margin. |
(1) IEX(T) stability curve, (2) self-heating sensitivity vs IEX, and (3) compliance margin test across worst-case resistance. These three items prevent “calibration hides drift” and “works on bench, saturates in the loop.”
H2-6. Thermocouple specifics: CJC done correctly (and provably)
Thermocouple accuracy is limited by microvolt-level noise and by temperature gradients near the connector. Cold-junction compensation (CJC) is not “an algorithm step”; it is a measurable sub-system whose placement and thermal coupling decide whether the bench result survives enclosure airflow, heat sources, and terminal geometry.
6.1 What CJC must measure (and what must be assumed)
- Must measure: the cold-junction temperature at the thermocouple connector/terminal, not “a convenient PCB temperature.”
- Must assume (and therefore verify): whether the connector and the chosen sensor location are close to isothermal under airflow, enclosure contact, and nearby heat sources.
6.2 Placement and thermal coupling: how to keep the sensor honest
- Track the connector, not the board average: place the CJC sensor on a thermal path that is dominated by the terminal temperature, not by adjacent high-power components.
- Control thermal gradients: use copper coupling where helpful, isolation slots where necessary, and shielding from direct airflow that cools only one spot.
- Prevent self-heating artifacts: choose a sensor and biasing method that does not create its own local hot spot.
6.3 CJC sensor choice: prioritize drift and response
| Factor | Why it matters | How to verify |
|---|---|---|
| Accuracy | Sets baseline cold-junction error; must be compatible with the overall error budget. | Compare against a reference probe at the terminal under stable conditions. |
| Drift / tempco | Turns ambient changes into offset; often the hidden cause of “seasonal” mismatch. | Chamber sweep; record ΔT_CJC vs ambient and convert to µV-equivalent error. |
| Self-heating | Creates local gradients that look like terminal temperature; can dominate at low airflow. | Power-step or bias-change test; observe local temperature rise and recovery. |
| Response time | Determines dynamic error under airflow transients and enclosure events. | Forced airflow / step heat test; measure time constant to within a target band. |
6.4 Validate CJC independently from the TC chain
CJC must be tested as its own subsystem. The goal is to quantify gradient sensitivity without confounding it with the thermocouple front-end gain or ADC noise. A minimal validation set includes:
- CJC gradient sensitivity test: apply controlled airflow or localized heating near the terminal and record ΔT_CJC vs a reference at the connector.
- µV-equivalent CJC error table: convert ΔT_CJC into equivalent input error voltage and carry it into the overall error@points budget.
(1) ΔT_CJC under forced airflow/heater near terminal, and (2) a table translating ΔT_CJC into µV-equivalent input error. These two outputs prevent “bench is good, enclosure is wrong.”
H2-7. Low-noise gain stage: microvolt work without flicker surprises
The gain stage defines the input-referred noise floor, low-frequency drift behavior, and how the system reacts to real-world interference. A “quiet on the bench” design can still fail in the field if analog gain saturates during EMI bursts, if bias paths are uncontrolled, or if chopper/auto-zero artifacts are filtered incorrectly. This chapter turns gain design into a deterministic, test-backed contract.
7.1 Gain partitioning: analog gain vs digital gain
- Too much analog gain increases sensitivity to common-mode injection and EMI bursts. Saturation creates slow recovery and “false drift” that looks like temperature movement.
- Too little analog gain pushes the chain into ADC noise limits, forcing aggressive digital filtering that can violate update-rate and latency requirements.
- Practical target: keep worst-case interference below the analog linear range while keeping smallest sensor steps above the ADC noise floor at the chosen update rate.
7.2 1/f noise and offset drift: what dominates at slow updates
Temperature is often sampled slowly, but slow updates shift attention to low-frequency behavior. In this region, 1/f noise and offset drift can dominate even when the integrated wideband noise looks excellent. The gain stage must be evaluated by input-referred noise density (including the 1/f rise) and by drift vs temperature, not only by midband noise.
7.3 Input impedance, bias currents, and source resistance (thermocouple trap)
- Bias current × source resistance becomes an input offset. For thermocouples, even small bias currents can translate into µV-level errors that appear as temperature shifts.
- Bias return paths must be controlled. Uncontrolled leakage paths (humidity/contamination dependent) cause ambient-sensitive offsets that mimic sensor drift.
- Verification approach: test offset with defined source resistances (emulated networks) and compare against shorted-input behavior.
7.4 Chopper / auto-zero: benefits vs ripple artifacts
- Benefit: reduces low-frequency offset and suppresses 1/f drift terms.
- Cost: introduces ripple and switching artifacts that can be rectified, aliased, or transformed by the input RC and ADC sampling behavior.
- Filtering rule: filter must attenuate ripple without pushing step response and settling beyond the measurement contract (latency/settle time).
| Evidence field | What it proves | How to collect |
|---|---|---|
| Noise density (input-referred) | Shows midband floor and 1/f rise; reveals whether “slow-update jitter” is dominated by low-frequency noise. | Measure spectral density at the input-referred level; mark the 1/f region and expected bandwidth. |
| Integrated noise | Converts noise into an RMS error over the chosen bandwidth/update settings; supports noise-free resolution claims. | Integrate noise over bandwidth or filter-equivalent; translate into µV and °C-equivalent jitter. |
| Offset drift vs temperature | Separates true sensor change from electronics drift; prevents “seasonal mismatch.” | Chamber sweep with input shorted or known source; report °C-equivalent drift across range. |
Declare limits in input-referred µV and °C-equivalent units at the target update rate. “No saturation under EMI burst” and “no ripple-induced settling violation” should be explicit acceptance criteria.
H2-8. 24-bit ADC selection & configuration: make “24-bit” real
“24-bit” is a marketing width, not a guaranteed resolution. Real performance is determined by noise-free bits at the target update rate, reference stability, input mux leakage, and digital filter choices that trade 50/60 Hz rejection against latency. This chapter converts ADC specs into end-to-end transmitter behavior that can be validated and budgeted.
8.1 Translate “ADC bits” into transmitter outcomes
- Noise-free bits sets the minimum stable temperature step (jitter floor) at the chosen update rate.
- ENOB is not a substitute for low-frequency stability; low-rate systems must prioritize 1/f and drift behavior in the chain.
- Input mux leakage can become a bias term for high-impedance inputs (thermocouples), turning into an ambient-sensitive offset.
- PGA options influence gain partitioning and saturation margin (ties back to H2-7).
8.2 Reference strategy: drift control is a system property
- Vref drift makes the measurement “ruler” move with ambient; it must be included in error@points and long-term stability claims.
- Buffering/drive prevents sampling dynamics from modulating the reference and creating repeatable patterns that look like noise.
- Ratiometric opportunities (especially for RTD) can suppress certain drift terms when the system measures ratios rather than absolutes.
8.3 Sampling & digital filter: line rejection vs latency
Line-frequency rejection is purchased with time. Higher OSR and stronger sinc-style filtering can reduce noise and reject 50/60 Hz, but they increase latency and slow step response. ADC configuration should be treated as a contract: select the update rate and rejection target first, then choose the filter family/OSR that meets both without violating settling requirements.
8.4 Input current / charge kickback: where RC and ADC collide
- Sampling dynamics can draw transient charge and disturb the front-end through source resistance and RC networks.
- Symptoms: periodic spikes, slow recovery after channel switching, or apparent noise rise at certain update rates.
- Verification: measure step response and disturbance amplitude after sampling events; confirm recovery within the allowed settling window.
| Evidence field | What it proves | How to collect |
|---|---|---|
| Noise-free resolution vs rate | Shows whether “24-bit” translates into stable codes at the target update rate. | Record code histogram at multiple update rates; compute noise-free bits or RMS-to-step. |
| 50/60 Hz rejection vs latency | Confirms line rejection does not violate response-time and settling requirements. | Inject 50/60 Hz interference; sweep OSR/filter; measure rejection and latency. |
| Kickback interaction | Validates ADC input behavior is compatible with the selected RC/bias network. | Observe switching transients and recovery time; verify no residual offset after settling. |
H2-9. Digital processing: linearization, filtering, and diagnostics hooks
Digital processing converts raw ADC codes into two outputs that must be trustworthy in the field: a temperature value with bounded residual error, and a fault state that can drive deterministic fail-safe behavior. This section defines where linearization lives, how coefficients are managed, how filtering stays stable without becoming sluggish, and which diagnostics signals should exist as first-class hooks.
9.1 RTD linearization: Callendar–Van Dusen concept and coefficient ownership
- Conceptual model: RTD resistance is mapped to temperature using a piecewise/parametric curve (CVD-style). The goal is not “math purity,” but predictable residual error after calibration.
- Where coefficients live: treat coefficients as device-specific assets. Default coefficients enable operation; factory coefficients enable guaranteed accuracy.
- Integrity hook: store coefficient version + CRC and expose a “calibration valid” flag. Missing/invalid coefficients should trigger a deterministic degraded/fault mode.
9.2 Thermocouple linearization: polynomial/LUT plus the CJC integration path
- Two-stage logic: convert TC µV to hot-junction temperature using polynomial/LUT, while CJC supplies the cold-junction temperature to close the absolute measurement.
- CJC validation hook: if the CJC sensor is out-of-range, unstable, or flagged invalid, temperature should be marked invalid (or switched to a defined fallback behavior).
- Residual awareness: keep an internal “linearization residual” metric at calibration points to detect coefficient mismatch or unexpected drift.
9.3 Filtering policy: stable but not sluggish
Filtering must satisfy three constraints simultaneously: (1) reduce jitter to meet noise-free resolution targets, (2) preserve step response so process changes are not hidden, and (3) keep fault detection latency within limits. Moving average and IIR filters are valid tools, but acceptance must be defined by measurable outcomes: RMS jitter, step settling time, and fault-to-action latency.
- Rule of thumb: filtering strength should be set by the required stability at the target update rate, then checked against the allowed settling window.
- Do not hide faults: filter and debounce must not delay open/short detection beyond the system’s response requirement.
9.4 Diagnostics hooks: compute raw flags, then map to fault states
| Hook (computed signal) | What it detects | Typical fault state mapping |
|---|---|---|
| Open/short detectors | Sensor wiring discontinuity or hard short; should survive noise and transients. | Sensor Open / Sensor Short |
| Out-of-range / plausibility | Codes exceed physical range; protects against invalid extrapolation. | Measurement Invalid |
| CJC sensor fault | CJC out-of-range, unstable, or self-test fail; prevents false absolute temperature. | CJC Invalid |
| ADC saturation flag | Front-end/ADC overrange or recovery issues (ties to EMI events). | Measurement Invalid |
| Reference / brownout monitor | Vref instability or rail drop that invalidates conversion integrity. | Reference Fault / Brownout |
(1) Residual error after linearization at calibration points and midpoints, and (2) fault detection latency table (fault occurrence → state decision → output action).
H2-10. Loop-powered 4–20 mA output stage: DAC + compliance + fail-safe
The 4–20 mA loop stage is the defining “transmitter” element: it must produce accurate current under wide loop resistance, long cables, and transients, while staying within the loop power budget. It must also express fault states as deterministic current behavior so field systems can distinguish sensor faults from measurement invalidity and power problems.
10.1 Loop power budget: build a current ledger first
A 2-wire loop-powered transmitter is current-budget limited. The design must enumerate dominant consumers (AFE, ADC/Vref, MCU/processing, and the output regulator) and verify margin under worst-case voltage, temperature, and startup/transient conditions. If budget margin collapses, measurement integrity and output stability can degrade simultaneously.
10.2 Compliance voltage: the boundary condition for current accuracy
- Compliance limit is reached when loop voltage headroom is insufficient at high loop resistance (long cable / high burden).
- Behavior beyond the limit is not “a little worse”; current regulation enters saturation and becomes non-deterministic unless explicitly handled.
- Acceptance: define and measure compliance margin (minimum headroom) across the expected loop resistance range.
10.3 DAC + current regulator (high-level): keep output stable under transients
- Architecture intent: DAC sets a current command, while the regulator enforces loop current across changing loop voltage.
- Transient resilience: cable-induced spikes and EMI must not cause long recovery, oscillation, or state ambiguity.
- Verification: sweep loop resistance and inject transients; confirm output returns within a defined settling window.
10.4 Fault current behavior: functional mapping (avoid standards deep dive)
Fault behavior should be functional and unambiguous: each fault state from H2-9 maps to a clearly distinguishable current behavior (e.g., fixed current levels or out-of-normal-range patterns). The mapping must avoid overlap with valid measurement range and must be reachable within a bounded latency.
| Fault state (from H2-9) | Functional current behavior | Validation check |
|---|---|---|
| Sensor Open / Sensor Short | Enter a distinct fault-current region that cannot be confused with valid temperatures. | Trigger each fault and measure time-to-fault-current and stability under loop resistance sweep. |
| CJC Invalid | Either declare measurement invalid via fault current or switch to a defined degraded mode with explicit flag. | Force CJC fault; confirm deterministic mapping and recovery behavior. |
| ADC Saturation / Reference Fault | Mark conversion integrity invalid and map to a non-overlapping fault current behavior. | Induce saturation or Vref drop; confirm mapping and no oscillation between states. |
(1) Power budget margin under worst-case loop voltage, (2) compliance sweep (loop resistance vs current accuracy), and (3) fault mapping latency (fault → action current) aligned to H2-9.
H2-11. Error budget & calibration strategy: the only way to claim accuracy
Accuracy claims are only defensible when every error source is counted in a single budget, expressed in a consistent unit (input-referred or °C-equivalent), and tied to a calibration and production-test flow that is repeatable at scale. This chapter provides a copy-ready error budget template, a calibration flow for RTD and thermocouple systems, and a minimal production test set that separates quick checks from soak-only characterization.
11.1 Error budget table template (copy-ready)
The budget must unify units. Each row should state: how the error is expressed, whether calibration can remove it, and what evidence proves the value. Use °C-equivalent for final claims, and keep input-referred as the diagnostic “root cause” view.
| Error source | Express as | Calibratable? | Evidence / test method | °C-equivalent note |
|---|---|---|---|---|
| Sensor & wiring | Ω / µV / lead ΔR | Partly | Known simulator networks; open/short injection; wiring config coverage. | RTD: ΔR → °C via slope; TC: µV → °C via LUT. |
| Excitation / Vref | ppm / drift | Limited | Vref stability test; excitation accuracy vs temperature; monitor flags. | Contributes as gain-like error across temperature span. |
| AFE gain/offset/drift | µV, ppm, µV/°C | Yes (offset/gain) | Shorted-input drift sweep; gain check with precision stimulus. | Dominates at low frequency; must be tied to update rate. |
| ADC noise / INL | RMS codes, INL | No (noise), partly (INL) | Histogram at target rate; linearity check; filter setting documented. | Noise sets jitter floor; INL sets curvature-like residuals. |
| CJC error (TC only) | °C, drift, gradient | Verify (not “hide”) | Gradient sensitivity test; forced airflow/heater near terminal; CJC plausibility flags. | Directly adds to TC absolute temperature error. |
| Linearization residual | °C residual | Yes (via coeffs) | Residual plot at calibration points + midpoints; coefficient version/CRC checks. | Should be bounded over the intended temperature range. |
| Output DAC / current accuracy | mA, %FS, drift | Yes (trim), verify | 4 mA / 20 mA (or midpoint) verification; compliance sweep across Rloop. | Maps to temperature via scaling; must not mask faults. |
For each row: define the worst-case condition (temperature, update rate, loop voltage), record the measurement method, then convert to °C-equivalent. Final accuracy should state both the method (RSS or worst-case) and the test conditions.
11.2 Calibration flow: RTD 1-point/2-point, TC + CJC verification
- RTD 1-point: removes offset-like terms (front-end offset, wiring residuals). Best when production time is constrained and span accuracy is acceptable.
- RTD 2-point: constrains both offset and gain-like terms. Recommended when accuracy must hold across a wide temperature span.
- Thermocouple: verify CJC as an independent contributor. A “perfect” end-to-end TC result can hide a CJC error if they accidentally cancel.
- Quality gates: coefficient CRC/version must pass; otherwise force degraded/fault behavior (aligned with the loop fault mapping in H2-10).
11.3 Where to store calibration constants: NVM + CRC + versioning
- Data structure: include version, calibration status flag, and CRC for atomic validation at boot.
- Boot policy: if CRC fails or version mismatches, set a “calibration invalid” state and drive deterministic output behavior.
- Write robustness: protect against partial writes (e.g., dual-slot/commit marker concept) so power interruptions do not create silent drift.
11.4 Production test minimal set: fast checks vs temperature soak
| Category | What can be tested quickly | What typically needs soak / characterization |
|---|---|---|
| Measurement integrity | Open/short detection, ADC saturation flag behavior, coefficient CRC/version check. | Offset drift vs temperature, low-frequency noise stability across temperature. |
| CJC (TC only) | CJC sensor plausibility, out-of-range detection, basic stability screen. | Gradient sensitivity, airflow/terminal heating sensitivity, long-term drift. |
| 4–20 mA output | 4 mA & 20 mA (or midpoint) accuracy, fault mapping trigger and action latency. | Compliance sweep over full Rloop under temperature extremes and transient stress. |
11.5 Long-term drift plan: “as-shipped” vs after 1000 hours
Even without current data, define the plan now so accuracy claims remain provable as the product matures. The drift plan should specify stress conditions, checkpoints, and pass/fail criteria in °C-equivalent and output current terms.
- Conditions: operating temperature, humidity, loop voltage range, and duty cycle (continuous vs intermittent).
- Checkpoints: baseline (as-shipped), intermediate (e.g., 168 h), and 1000 h endpoints with repeated calibration-point measurements.
- Criteria: drift limit (°C-equivalent) + output current drift limit + false-fault rate under stress.
H2-12. EMC, isolation, and layout validation checklist
This checklist focuses on silent accuracy loss: the device may not reset, but temperature reading drifts during/after EMI. The validation target is therefore measurable: ΔTemp shift under stress and recovery time back within spec, aligned to the error budget (H2-11) and diagnostics/fault mapping (H2-9/H2-10).
12.1 Layout priorities (RTD/TC transmitter specific)
| Priority | What to do (checklist) | Field symptom if wrong | How to validate |
|---|---|---|---|
| Guarding & leakage control | Guard high-impedance nodes; keep input pins clean/short; avoid flux residue around TC/RTD input networks; keep ESD parts away from microvolt nodes unless leakage is proven acceptable. | Slow drift, humidity-sensitive offset, “fine on bench” but off in enclosure. | Humidity/condensation screening; measure offset drift vs time; log ΔTemp_residual after EMI. |
| Kelvin routing (RTD 3/4-wire) | Route force/sense as controlled pairs; sense lines must return to the same Kelvin point; avoid shared copper that adds unknown lead resistance. | Span error grows with cable length; inconsistent readings across harness variants. | Swap cable lengths; verify error@points stays within budget; look for gain-like shift. |
| Split returns (analog/digital) | Control return paths: keep AFE/Vref return quiet; prevent digital/isolator switching currents from flowing under the input/ADC reference network. | Noise floor rises; readings “breathe” with MCU activity or comms. | Toggle digital load/comms; measure input-referred RMS noise and ΔTemp_peak. |
| CJC thermal symmetry (TC only) | Place CJC sensor thermally coupled to terminal/connector; use copper for coupling but isolate from hot components; consider thermal slots to reduce gradients. | Airflow or nearby heat makes absolute temperature wrong without fault flag. | Forced airflow/heater near terminal; quantify “CJC gradient sensitivity” as °C shift. |
| Input filtering vs settling | Coordinate RC/CM filtering with the update rate; avoid “filter so strong it hides faults” or “so weak it allows RF rectification.” | Either sluggish response or EMI-induced jumps/rectified offsets. | Step response test + injected RF test; record ΔTemp(t) and t_recover. |
During EMC stress, success is defined by ΔTemp_peak, ΔTemp_residual (post-event), and t_recover to return within the H2-11 accuracy band — not by “no reset occurred.”
Example MPNs to evaluate (input protection & filtering)
These are example parts commonly used in industrial signal-chain EMC hardening. Final selection must verify leakage, capacitance, and surge rating under the intended stress.
12.2 Isolation boundary (if used): what crosses, and how parasitics inject noise
- Define the crossing set: data lines (SPI/I²C/UART), power (isolated DC-DC), and any reference-related signals. Minimize crossings that reference analog ground.
- Control the coupling path: isolator parasitic capacitance and creepage leakage can inject common-mode energy into the AFE/Vref/input network.
- Place boundaries intentionally: keep isolators and isolated power switches away from TC/RTD input and ADC reference region; route return currents so they cannot undercut the input network.
- Make it measurable: under injected RF/EFT, track whether faults are correctly flagged (ADC saturation/reference fault) and whether ΔTemp_residual returns to baseline.
Example MPNs to evaluate (digital isolation & isolated power)
12.3 EMC validation plan (measure temperature error shift, not just “no reset”)
| Stress type | What to observe (metrics) | Pass criteria | Must log |
|---|---|---|---|
| Injected RF | ΔTemp(t) during exposure; ΔTemp_peak; whether ADC saturation/reference fault flags trigger; whether output current remains stable or enters the intended fault mapping. | ΔTemp_peak within allowed band; no persistent ΔTemp_residual after RF stops. | Frequency/amplitude; coupling method; update rate + filter setting; fault-state timeline. |
| EFT / Burst | State-machine stability (no rapid toggling); output-current glitches; t_recover back within spec; post-event residual error. | t_recover within budget; no chatter beyond defined limit; residual within spec. | Event count; worst-case ΔTemp_peak; worst-case t_recover; rail monitor flags. |
| Surge | Permanent offset shift after stress; coefficient integrity; output-current accuracy shift; sensor fault detection still correct. | Post-stress error@points stays within H2-11 budget; no new silent drift mode. | Pre/post comparison; error@points; output 4 mA/20 mA check; fault mapping check. |
ΔTemp_peak, ΔTemp_mean (event window), ΔTemp_residual (N seconds after event), t_recover_to_spec, chatter_count (fault-state toggles), and “fault → output-current action” latency.
Example MPNs to evaluate (surge/lightning protection at the loop side)
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H2-13. FAQs (Accordion) — troubleshooting without scope creep
Each FAQ maps back to a chapter and a measurable evidence field (error@points, noise, ΔTemp shift, compliance margin, fault latency). Answers prioritize what to measure first, then the smallest fix that changes the evidence.
RTD
RTD reads high only at warm ambient—self-heating or excitation drift? (→ H2-5 / H2-11)
Likely cause: if the offset grows with ambient while wiring is unchanged, suspect RTD self-heating first, then excitation drift as a gain-like contributor. Measure (1) error@points across temperature with two excitation currents and (2) excitation/Vref stability proxy versus ambient. First fix: reduce excitation current or duty-cycle it, then re-check the error budget. (→ H2-5 / H2-11)
RTD
3-wire RTD still shows lead error—wiring asymmetry or sense routing? (→ H2-5 / H2-12)
Likely cause: 3-wire compensation fails when the two lead resistances are not matched or when the sense return is not truly Kelvin to the same point. Measure (1) lead imbalance by swapping the two “same” leads and (2) span shift versus cable length. First fix: enforce Kelvin routing to a single sense node and keep the two lead paths symmetric. (→ H2-5 / H2-12)
TC
Thermocouple stable on bench, drifts in enclosure—CJC placement or thermal gradient? (→ H2-6 / H2-12)
Likely cause: enclosure airflow and nearby heat sources change the terminal temperature gradient, so CJC no longer tracks the cold junction. Measure (1) CJC gradient sensitivity by applying airflow or a localized heater near the terminal and (2) ΔTemp_residual after the disturbance ends. First fix: move/thermally couple the CJC sensor to the connector and reduce gradients with copper/slots. (→ H2-6 / H2-12)
ADC
Noise spikes at 50/60Hz—ADC filter or input RC tradeoff? (→ H2-8 / H2-4)
Likely cause: line-frequency pickup is leaking through because the ADC notch/rejection setting and the analog input pole are not aligned with the update rate. Measure (1) noise RMS with filter/OSR settings swept and (2) step response settling time after an input step. First fix: choose an OSR/sinc mode with explicit 50/60 Hz rejection, then tune RC to avoid excessive latency. (→ H2-8 / H2-4)
AFE
24-bit ADC but jittery last digits—reference noise or gain-stage 1/f? (→ H2-8 / H2-7)
Likely cause: “24-bit” is not noise-free bits; low-frequency 1/f and reference noise dominate the last digits at slow update rates. Measure (1) input-referred RMS noise over the measurement bandwidth and (2) code wander versus time with a shorted input. First fix: improve Vref filtering/buffering and reduce 1/f exposure by selecting a lower-noise gain stage or changing the update/filter policy. (→ H2-8 / H2-7)
DIAG
Open-sensor detection false-trips—bias path leakage or threshold logic? (→ H2-4 / H2-9)
Likely cause: false opens often come from temperature-dependent leakage (protection parts, PCB contamination) or overly aggressive thresholds that ignore settling after mux/filter changes. Measure (1) open-detect trip rate versus temperature/humidity and (2) fault detection latency relative to the filter settling time. First fix: verify bias return paths and leakage, then add debounce/hysteresis and ensure the check runs after the measurement is settled. (→ H2-4 / H2-9)
LOOP
4–20mA saturates at high loop resistance—compliance headroom or power budget? (→ H2-10)
Likely cause: saturation at high Rloop is usually compliance headroom loss: the transmitter cannot maintain the required voltage across the current regulator plus internal rails. Measure (1) compliance margin (available loop voltage minus internal dropout) at 20 mA and (2) rail headroom under worst-case load. First fix: reduce dropout (rail choices) or lower internal consumption, then re-validate 20 mA accuracy across Rloop. (→ H2-10)
DSP
Step response too slow—digital filter or analog anti-alias? (→ H2-8 / H2-9)
Likely cause: slow response is typically digital filter group delay; analog RC becomes dominant only when set too low for noise/EMI reasons. Measure (1) 10–90% settling time after a known input step and (2) update rate versus filter setting (OSR/sinc). First fix: choose a faster filter mode with acceptable 50/60 Hz rejection, then re-tune analog RC just enough to prevent RF rectification. (→ H2-8 / H2-9)
EMC
After surge, reading offset changed—protection leakage shift or input damage? (→ H2-4 / H2-12)
Likely cause: a post-surge offset shift can be “soft damage” (leakage increase in protection parts) or “hard damage” (input structure degradation). Measure (1) offset with a shorted input before/after stress and (2) ΔTemp_residual after surge plus a re-check of error@points. First fix: isolate by temporarily removing/relocating the protection element and re-testing leakage and offset under temperature. (→ H2-4 / H2-12)
CAL
Calibration doesn’t hold over temperature—drift source or wrong model? (→ H2-11)
Likely cause: if errors grow with temperature distance from calibration points, the dominant issue is drift (AFE/Vref/CJC) or an insufficient model (coefficients not valid over range). Measure (1) residual error curve across temperature points and (2) offset/gain drift sweep of the front-end and reference. First fix: move to a 2-point (or segmented) calibration and enforce coefficient version/CRC gating, then re-run the budget closure. (→ H2-11)
LOOP
Temperature reading jumps but 4–20mA looks steady—filtering, diagnostics, or DAC hold? (→ H2-9 / H2-10)
Likely cause: the measurement path may be unstable while the output stage is smoothing/holding the previous current, masking the issue. Measure (1) internal raw code variance versus reported temperature and (2) fault/state timeline against output current updates. First fix: align output update policy with measurement validity: only update 4–20 mA after the reading passes plausibility/settling checks, and log a diagnostic when clamping/holding occurs. (→ H2-9 / H2-10)
TC
Switching thermocouple type increases error—linearization table/version or CJC offset? (→ H2-9 / H2-11 / H2-6)
Likely cause: wrong polynomial/LUT selection, coefficient version mismatch, or a fixed CJC offset becomes visible when the TC sensitivity changes by type. Measure (1) type-specific residual error at a few temperature points and (2) CJC reading consistency at the connector. First fix: enforce “type + coefficient version + CRC” binding in NVM, then re-validate CJC placement and rerun the residual plot for the selected type. (→ H2-9 / H2-11 / H2-6)
