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Boost LED Driver (CC): Boost Control, Protection & Compensation

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A Boost constant-current LED driver is the go-to choice when the LED string voltage must be higher than the input, because it regulates LED current directly while managing duty-cycle limits, loop stability, and open-string/OVP risks. This page shows how to design and debug the control loop, protection behavior, UV/OV startup, and dimming injection so brightness stays accurate and flicker-free across VIN and temperature.

H2-1. What a Boost Constant-Current LED Driver Is and When to Choose It

Core takeaway (engineering)

A Boost constant-current (CC) LED driver is the right fit when VIN(min) is below the LED string voltage and the system still needs regulated LED current across dimming, faults, and startup. The goal is not “make voltage higher,” but “keep ILED predictable while VOUT and duty cycle move.”

Use when: VIN(min) < VLED Focus: ILED control + protections Risk: duty → 1 region
Decision entry (when Boost CC is mandatory)
  • Voltage relationship: VIN(min) < VLED(string, max) for a meaningful portion of operation. (If this condition is not true, Boost CC is usually not the primary constraint.)
  • Current quality requirements: the application needs a defined ILED accuracy, controlled ripple, and a predictable dimming ratio (including deep dimming behavior).
  • Fault safety requirements: the design must handle open string conditions without uncontrolled VOUT rise, meaning an explicit OVP threshold and fault recovery mode are part of the design, not afterthoughts.
Boundary: Boost CC vs “CV Boost + downstream sink”

This page is strictly about Boost CC (the power stage closes the loop on LED current). A common alternative is a constant-voltage (CV) boost feeding a downstream current sink stage. The boundary matters because protections, loop behavior, and measurement points differ.

  • Boost CC: the regulated variable is ILED. The loop reacts directly to current-sense feedback, so dimming injection, compensation, and fault behavior are coupled to current regulation.
  • CV + sink: the boost stage regulates VOUT while a separate stage manages current. This can help multi-channel matching, but it moves current accuracy and fault handling away from the boost controller.
  • Practical boundary line: if the design requires “the boost stage must guarantee ILED under all conditions,” the architecture is Boost CC. If the boost stage only guarantees a rail and current is allocated elsewhere, it is CV + sink.
The two boost-specific risks that must be called out early

Risk #1 — Duty cycle near 1: as VIN/VLED approaches 1, the controller can lose effective control margin (minimum off-time, switch-node noise injection, and loop phase margin all become more sensitive).
Risk #2 — Open-string OVP: if the LED string opens, the boost stage can push VOUT upward until a clamp/OVP action takes over. A deliberate OVP threshold + recovery policy prevents repeated overstress and EMI bursts.

Evidence fields (inputs that unlock the rest of the page)
  • Input window: VIN(min/max) + input droop/ripple conditions.
  • Load window: VLED range (temperature/binning/aging) and target ILED.
  • Quality: ILED accuracy, allowable ripple %, and required dimming ratio (including dim-to-off behavior).
  • Protection policy: OVP threshold, UVLO thresholds/hysteresis, and fault recovery mode (hiccup vs latch).
  • Control target: intended loop BW/PM and acceptable startup overshoot.
Figure F1 — Decision map (VIN vs VLED, dimming depth, protection need)
Boost CC Selection Map VIN / VLED ratio • dimming depth • open-string protection 0.2 0.4 0.6 0.8 1.0 1.2 100% 30% 10% 1% 0.1% Boost CC “Sweet Spot” VIN(min) clearly below VLED(max) CC dimming + open-string OVP needed Risk Zone: duty → 1 Less control margin OVP sensitivity increases Verify COMP & SW waveforms Boundary VIN/VLED ≥ 1 Boost not the main constraint VIN(min) / VLED(string,max) Dimming depth Open-string OVP required Check: duty margin, startup overshoot, recovery
This diagram is a conceptual selection map. Exact boundaries depend on minimum on/off time, loop design, and protection thresholds. Cite this figure: See References (conceptual block/decision view; confirm limits in controller datasheets).

H2-2. System Architecture: Power Stage + CC Loop + Protection Hooks

What this section delivers

A Boost CC driver becomes “debuggable” only when every function is tied to a node that can be measured. The architecture below is written so each block has a corresponding test point (TP) and each TP has a diagnostic meaning (control stability, fault detection, or power-path stress).

Power path vs control path (why failures look confusing)
  • Power path (energy): VIN → L → SW node → rectifier/SR → COUT → LED string. The SW node carries fast edges (dv/dt) and is the primary EMI/noise source.
  • Control path (information): ILED → RSENSE → error amplifier (EA) → COMP → PWM modulator → duty. Noise that couples into RSENSE or COMP can look like “flicker,” “false OVP,” or “unstable dimming.”
  • Protection hooks: OVP/UVLO/OCP/OTP are not “features”; each is a detector tied to a node plus an action that limits energy.
Test point map (each TP proves something specific)
  • TP_VIN: input droop/ripple and UVLO events (proves “supply weakness” vs “control instability”).
  • TP_SW: duty, ringing, and minimum off-time margin (proves “switching behavior / EMI driver”).
  • TP_IL: inductor current slope/limit/overshoot (proves “OCP/soft-start correctness”).
  • TP_ISENSE: true current-sense waveform at RSENSE (proves “accuracy vs noise injection”).
  • TP_COMP: loop control effort and stability (proves “compensation margin / hunting”).
  • TP_VOUT: open-string rise and clamp effectiveness (proves “OVP policy and stress risk”).
  • TP_ILED: LED current ripple and low-frequency components (proves “no-flicker under dimming”).

Measurement rule of thumb: if a symptom is visible in TP_ILED but not in TP_COMP, the root cause is often power-path ripple or sensing noise. If TP_COMP is oscillating, the loop is “arguing” with the plant or the dimming injection point.

Protection hooks as “detect → act” (avoid checkbox thinking)
  • UVLO: detect on TP_VIN → act by disabling switching and enforcing a restart policy (prevents brownout chatter).
  • Open-string OVP: detect on TP_VOUT → act by clamp/turn-off/hiccup (prevents uncontrolled VOUT rise).
  • OCP: detect on TP_IL or internal current limit → act by cycle-by-cycle limit or shutdown (prevents power-stage overstress).
  • OTP / thermal foldback: detect at NTC/die → act by reducing ILED target (prevents runaway and long-term lumen loss).
Figure F2 — Boost CC block diagram with test points
Boost CC Architecture + Test Points Power path • CC loop • protection hooks • Kelvin sense POWER PATH VIN L Inductor SW MOSFET VSW node D / SR Rectifier COUT LED String RSENSE CONTROL (CC LOOP) ISENSE Kelvin from RSENSE EA Error amplifier COMP Type-II network PWM MOD Duty control Gate drive path Dimming injection PROTECTION HOOKS (detect → act) UVLO OVP OCP OTP Kelvin sense (keep away from SW) Hot loop (minimize area) TP_VIN TP_SW TP_IL TP_VOUT TP_ILED TP_ISENSE TP_COMP
The diagram ties each feature to a measurable node. Keep the power hot loop compact, and route Kelvin sense away from the SW node to avoid false protection triggers. Cite this figure: See References (conceptual block view; confirm pin functions and thresholds in the controller datasheet).
References (placeholder)

Add controller datasheets, application notes, and relevant measurement references here. (This section is a placeholder to support “Cite this figure” links.)

H2-3. How Boost CC Regulation Works: Control Law, Duty Cycle Limits, and Ripple

What is being regulated (keep the mental model correct)

In a Boost constant-current LED driver, the closed loop regulates LED current (ILED), not output voltage. The controller adjusts duty cycle so the inductor transfers the right amount of energy each cycle to hold the sensed current at its target, while VOUT can move with LED string voltage and operating conditions.

Regulated: ILED Actuator: duty Plant: L + switching + COUT + LED
Duty cycle behavior when VIN < VLED
  • Direction: as VIN drops or VLED rises, the required duty increases. This is the unavoidable Boost trade: less input voltage headroom means more time spent storing energy in the inductor.
  • Why this matters: higher duty reduces the available off-time window. When Toff becomes short, several limits appear at once: minimum off-time, current-sense timing margin, and switch-node noise coupling into sensitive sense paths.
  • Practical pre-check: compute a “risk flag” from VIN(min) and VLED(max) and compare it to the controller’s minimum on-time/off-time constraints. If the design frequently operates near these limits, duty clipping and unstable behavior become more likely.

Key evidence fields to log for this chapter: duty estimate range, controller minimum on/off time, and the observed Toff from TP_SW.

Inductor ripple (ΔIL) → LED current ripple (ripple%)

The inductor current is never perfectly flat. Each cycle, it ramps up during Ton and ramps down during Toff, creating a triangular ripple ΔIL. Part of that ripple is buffered by COUT, but whatever is not filtered appears as ILED ripple. In deep dimming or near duty limits, this coupling is more visible because control margin and effective filtering shrink.

  • ΔIL grows when: inductance is low, switching frequency is low, or the inductor sees larger effective volt-seconds per cycle.
  • ILED ripple grows when: COUT is small/high-ESR, LED dynamic resistance is low, or sense noise injects into the loop.
  • How to separate causes quickly: compare TP_IL ripple (ΔIL) with TP_ILED ripple%. If ΔIL is modest but ILED ripple is large, suspect filtering/sensing/noise rather than the inductor itself.
What gets amplified as duty → 1 (control / EMI / thermal)

Control margin shrinks: short Toff increases the chance of minimum off-time limitation and reduces room for clean current sampling and stable loop behavior. A common symptom is TP_COMP approaching a clamp level while TP_SW shows duty clipping.

Noise coupling rises: the switch node dv/dt is unchanged, but the system becomes more sensitive to it. If TP_ISENSE shows switching-synchronous spikes, those spikes can be interpreted as current changes and create flicker or false protection triggers.

Thermal stress shifts: high duty generally raises RMS current stress in the power path. If TP_IL average rises and ripple increases, expect higher copper and switching losses and a narrower thermal margin.

Evidence fields that should appear in lab notes: measured duty and Ton/Toff at TP_SW, ΔIL at TP_IL, ILED ripple% at TP_ILED, and whether TP_COMP is near saturation.

Figure F3 — Waveforms: VSW + IL ripple + ILED ripple coupling
Waveform Coupling: VSW → ΔIL → ILED ripple Duty sets Ton/Toff • inductor ripple becomes LED ripple VSW (TP_SW) Inductor current IL (TP_IL) LED current ILED (TP_ILED) Ton Toff Ton Toff (smaller) Ton Toff (tiny) ΔIL ripple% Duty → 1 effect Toff shrinks Less margin
Measure TP_SW to verify Ton/Toff margin, TP_IL to quantify ΔIL, and TP_ILED to compute ripple%. The arrows show the causal chain: switching timing shapes inductor ripple, which then couples into LED current ripple. Cite this figure: See References (conceptual waveform coupling; confirm timing windows in the controller datasheet).

H2-4. Current Sensing and Error Budget: Getting Real CC Accuracy

Why “CC accuracy” is an error budget, not a single spec

LED current accuracy is the sum of multiple errors that stack and drift. A Boost CC design becomes predictable only when each error term is named, measurable, and tied to a fix. This section decomposes ILED accuracy into component tolerance, amplifier imperfections, and layout-induced parasitics (including ground bounce).

Static error: tolerance + offset Dynamic error: noise + RC delay Layout error: Kelvin + ground bounce
The main error sources (what each one looks like in measurement)
  • RSENSE tolerance & tempco (ppm/°C): sets the baseline unit-to-unit spread and temperature drift. If ILED shifts mainly with temperature while TP_COMP behavior stays normal, RSENSE/thermal gradient is a prime suspect.
  • EA offset & gain error: becomes dominant when the sense voltage is small. If low-current setpoints show a larger percentage error than high-current setpoints, offset/gain terms are often the reason.
  • Kelvin routing quality: determines whether the controller “sees” the true RSENSE voltage or a polluted version of it. A mismatch between “direct RSENSE probe” and “sense pin waveform” is strong evidence of layout parasitics.
  • Ground bounce (ΔV): switching current returning through shared impedance can add an unwanted voltage to the sense signal. Switching-synchronous spikes at TP_ISENSE indicate this mechanism.
  • Sense filter RC delay: reduces noise but adds phase lag and slows the loop’s response. Over-filtering can trade ripple reduction for hunting or sluggish transient response.
Two-measurement localization (fastest way to “assign the blame”)

Measure A: probe directly across RSENSE pads (true Kelvin at the component).
Measure B: probe the controller’s sense input waveform (TP_ISENSE / sense pins).
Interpretation: if A is clean but B contains switching spikes or offsets, the dominant error is routing/ground bounce/coupling, not RSENSE tolerance. If both A and B shift with temperature similarly, RSENSE tempco and thermal gradient are dominant.

Evidence fields to capture: RSENSE tolerance/ppm, observed offset (mV-equivalent at sense), gain error trend vs setpoint, sense RC values, and measured ground bounce ΔV.

Design knobs (how to improve accuracy without creating new problems)
  • Choose RSENSE intentionally: balance power loss vs sense voltage headroom. Lower loss is attractive, but too small a sense voltage makes EA offset and noise more visible in percent error.
  • Enforce Kelvin routing: route two dedicated traces from RSENSE to the sense pins, away from the SW node and hot loop. Keep the sense pair short and shielded by quiet ground.
  • Treat the sense RC as part of control design: filtering is beneficial, but its delay interacts with loop compensation and dimming dynamics. The “quietest waveform” is not always the “most stable loop.”
  • Control ground bounce: avoid sharing high di/dt return paths with sense ground. If TP_ISENSE shows spikes aligned to TP_SW, the fix is often in return routing and hot loop minimization, not in firmware or setpoint values.
Figure F4 — Error budget stack for ILED (measurable and actionable)
ILED Accuracy = Error Budget Split error into measurable terms • localize with two probes Error stack (concept) RSENSE tolerance + tempco EA offset / gain error Kelvin routing parasitic Ground bounce (ΔV) Sense RC delay (dynamic) Fast localization: measure A vs B Measure A Across RSENSE pads True Kelvin at part Checks RSENSE / thermal Measure B Sense pins (TP_ISENSE) What controller “sees” Checks routing / bounce Interpretation (simple rules) A clean, B noisy → routing / ground bounce dominates A & B drift with temp → RSENSE / thermal gradient dominates
Use the stack to keep accuracy discussions measurable. The two-probe method (RSENSE pads vs sense pins) quickly distinguishes component/thermal error from layout-induced error (Kelvin routing and ground bounce). Cite this figure: See References (conceptual error decomposition; confirm sense architecture in the controller datasheet).
References (placeholder)

Add controller datasheets and app notes for minimum on/off time limits, current sense accuracy terms, and measurement guidance. (Placeholder to support “Cite this figure” links.)

H2-5. Loop Compensation for Boost CC: Type-II Design, Crossover, Phase Margin

Why Boost CC compensation has a hard bandwidth limit

Boost constant-current regulation inherits the power-stage “features” that shape stability: an output pole, an ESR zero (device- and temperature-dependent), and a right-half-plane zero (RHPZ) in many CCM operating points. The practical outcome is simple: crossover frequency must stay well below the RHPZ, or phase margin collapses and deep-dimming becomes flicker-prone.

Target crossover (fc) Phase margin (PM) TP_COMP headroom Overshoot / settling
Executable Type-II workflow (design → verify)
  • Step 1 — Choose the worst operating corner: use VIN(min), VLED(max), and the deepest expected dimming point. This corner tends to push duty high and shrink timing margin, which stresses stability.
  • Step 2 — Set a realistic crossover target: pick fc based on desired transient speed and ripple control, but keep fc safely below RHPZ (treat RHPZ as a “do not cross” boundary).
  • Step 3 — Confirm COMP headroom: define a “normal COMP band” where the loop is linear. If TP_COMP sits near clamps, recovery is slow and apparent stability can change with dimming.
  • Step 4 — Place Type-II zeros/pole: use a low-frequency zero to compensate the output pole, a second zero to boost phase around crossover, and a high-frequency pole to reduce switching-noise gain at COMP.
  • Step 5 — Validate with a current command step: apply a controlled ILED step and capture TP_ILED (overshoot/settling), TP_COMP (saturation/oscillation), and TP_SW (duty clipping).
  • Step 6 — Re-check deep dimming: repeat the same step test at the lowest dimming level. If only low-light oscillates, the effective plant moved and the chosen fc/phase margin is insufficient at that corner.

Evidence fields to log: target fc, achieved PM, COMP voltage range (min/max), Type-II zero/pole locations, and transient metrics (overshoot %, settling time).

Waveform acceptance criteria (fast lab judgement)

Stable + responsive: TP_ILED reaches the new setpoint with limited overshoot and a clean settle; TP_COMP moves smoothly and stays away from clamps; TP_SW does not show repeated duty clipping at the step edge.

Marginal stability signs: ringing in TP_ILED, bursty behavior at deep dimming, or switching-synchronous spikes amplified at TP_COMP. These often indicate fc too aggressive or insufficient phase margin.

Figure F5 — Loop sketch: plant features + Type-II placement
Loop Design Map (Boost CC) Plant features set the boundary • Type-II shapes phase near crossover Power stage “plant” features Low High Frequency Output pole ESR zero RHPZ DO NOT CROSS Phase lag grows near poles/RHPZ Type-II compensation placement Type-II Z1, Z2 boost phase P1 tames HF noise Low High Z1 Z2 P1 fc RHPZ Keep fc below RHPZ Evidence TP_COMP range PM at fc Overshoot/settle
A practical sketch for Boost CC loop design: place Type-II shaping around the plant’s dominant behaviors and keep crossover clearly below the RHPZ region. Cite this figure: See References (conceptual placement; verify plant features with the chosen controller and operating corner).

H2-6. LED String Protection: Open-String OVP, Clamp Strategy, and Safe Restart

What happens on open string (why VOUT can spike)

When the LED string opens, TP_ILED collapses toward zero while the control loop still attempts to reach the current setpoint. The loop responds by increasing duty, which drives VOUT upward searching for a conduction path. Without a defined protection path, VOUT can climb until a device limit is hit or an unintended discharge path appears.

Open-string detect OVP threshold Clamp stress Retry / hiccup
Design the protection as a complete chain (detect → clamp → settle → restart)
  • Detect: use a robust open-string condition such as ILED ≈ 0 while VOUT rises or sits above a defined “string present” window. The condition must reject short transients (dimming edges, brief connector bounce).
  • OVP threshold: set OVP above the maximum normal operating VLED plus dynamic margin, but below the safe voltage of power devices and capacitors. Treat this as a design window, not a single number.
  • Clamp strategy: clamp is not only “limit voltage” — it is “handle energy.” Evaluate clamp device stress during the event (voltage, current, and thermal rise) and the resulting burst noise.
  • Discharge/settle: after clamp, allow VOUT to settle to a safe level before retry. This reduces repeated overshoot and lowers burst EMI.
  • Safe restart policy: implement a controlled retry with a timer and a soft-start ramp. Add escalation: after N consecutive failures, enter hiccup (longer off-time) or latch (requires external reset), depending on system needs.

Evidence fields to capture: OVP threshold, clamp device stress, restart timer, latch/hiccup conditions, and open-string detection criteria.

How to validate in the lab (what to capture)

Open event capture: record TP_VOUT overshoot and clamp level, plus TP_SW behavior at detection and clamp entry. Confirm protection triggers quickly and repeatably without uncontrolled spikes.

Restart behavior capture: measure the retry interval, soft-start slope, and whether repeated failures escalate to hiccup/latch. Confirm the behavior avoids rapid visible flashing and avoids thermal accumulation in clamp components.

Figure F6 — Fault state machine: normal → open detect → clamp → retry
Open-String Protection State Machine Detect → Clamp → Settle → Retry • Escalate after repeated failures NORMAL Regulate ILED OPEN DETECT ILED≈0 + VOUT rising OVP CLAMP Hold VOUT DISCHARGE / SETTLE Lower VOUT safely RETRY (SOFT-START) Timer + ramp HICCUP Longer off-time LATCH External reset Open condition VOUT > OVP Clamp entry Settle done Retry pass → NORMAL N failures Parameters OVP threshold Retry timer N_fail (hiccup/latch)
A complete open-string strategy must define detection, voltage limiting, energy handling, and a restart policy that avoids repeated bursts. Cite this figure: See References (conceptual state flow; implement using the selected controller’s OVP and fault modes).
References (placeholder)

Add the specific controller datasheet/app note for: RHPZ/plant guidance, recommended compensation procedure, OVP behavior, and fault/retry modes. (Placeholder to support “Cite this figure” links.)

H2-7. UV/OV and Startup Behavior: Soft-Start, Inrush, and Overshoot Control

Fix “startup flash”, intermittent OV, and cold-start fails

Boost CC startup problems almost always live in a short time window: VIN crosses UVLO, the controller begins soft-start, the LED string may still be non-conducting, and VOUT can rise quickly while the loop is still “searching” for current. The goal is to keep the system inside a safe envelope: avoid repeated UVLO chatter, limit inrush (IL rise), and prevent VOUT overshoot from tripping OVP or overstressing components.

UVLO rising/falling UVLO hysteresis Soft-start ramp IL inrush peak VOUT overshoot Brownout recovery
Phase-by-phase startup checklist (what to measure, what it means)
  • Phase A — VIN near UVLO: log UVLO_rising and UVLO_falling. If TP_VIN crosses the window repeatedly, visible flashing and bursty behavior are expected. Fixes typically include increasing effective hysteresis (avoid “chatter”) and ensuring the input source does not sag under inrush.
  • Phase B — Soft-start ramp begins: capture TP_COMP and TP_IL. A soft-start that is too fast drives a steep IL ramp (large inrush peak), which can charge TP_VOUT aggressively and create overshoot. A soft-start that is too slow can keep the loop saturated longer and delay a clean entry into regulation.
  • Phase C — LED not conducting window: watch for the case where TP_VOUT rises while TP_ILED remains near zero. This is the highest-risk moment for OVP false triggers and overshoot. A safe design keeps VOUT rise controlled and ensures OVP thresholding accounts for the temporary “no-current” window.
  • Phase D — Enter CC regulation: a successful start shows TP_ILED ramping smoothly to target, TP_COMP staying within a normal mid-range band (not pinned), and TP_SW avoiding repeated duty clipping.
  • Brownout behavior: force a controlled VIN dip below UVLO_falling and restore it. A robust system exits cleanly and restarts repeatably without getting “stuck” (COMP pinned, fault mode latched, or repeated OVP events).

Evidence fields to record per start: UVLO_rising/UVLO_falling, soft-start ramp time, IL_peak, VOUT_overshoot, and brownout recovery pass/fail with notes.

Fast acceptance criteria (pass/fail by waveforms)

Pass: VIN crosses UVLO once; IL rises with a controlled slope; VOUT overshoot stays below OVP with margin; COMP does not stay pinned; ILED settles to target without bursts.

Fail patterns: UVLO chatter; large IL spike at enable; VOUT overshoot followed by OVP entry; repeated “start–stop” cycles; or brownout that returns to a stuck or bursty state.

Figure F7 — Startup timeline (VIN, VOUT, IL, COMP) with danger points
Startup Timeline (Boost CC) Four channels • Mark UVLO window, OVP risk, and brownout recovery t0 time VIN VOUT IL COMP UVLO_r UVLO_f OVP VOUT overshoot IL_peak soft-start ramp COMP normal band LED off window / OVP risk Brownout test VIN dip below UVLO_f Evidence UVLO_r / UVLO_f SS ramp time IL_peak VOUT_ovsh
Capture all four channels in one shot: TP_VIN, TP_VOUT, TP_IL, and TP_COMP. The boxed “LED off window” is where overshoot and OVP false triggers most often originate. Cite this figure: See References (conceptual timing; confirm UVLO/soft-start/OVP behavior per controller datasheet).

H2-8. Dimming Interfaces in Boost CC: PWM vs Analog, Deep-Dim Stability, No-Flicker Checklist

Dimming in Boost CC is about injection point (not just “PWM vs analog”)

In a boost constant-current driver, dimming stability is determined by where the dimming command enters the control loop. Three common injection points are used: adjusting the reference (analog dimming), gating the COMP/control effort, or gating the PWM switching/current path. Deep dimming is the stress case: minimum pulse limits, reduced sense signal, and low-frequency energy pulsing can produce visible artifacts unless the loop and timing are designed as a set.

PWM frequency Min pulse width Dim-to-off ILED ripple vs dim Low-frequency ripple Deep-dim stability
Injection options (what they optimize, what they break)
  • REF injection (analog dimming): changes the current target smoothly and avoids hard on/off edges, but deep dimming can become offset/noise-limited as sense signal shrinks. Track ILED ripple% at low dim levels.
  • COMP gate / clamp: limits control effort during transitions and can reduce overshoot bumps, but can introduce nonlinearity and slow recovery if COMP spends time near clamps. Watch TP_COMP range and settling.
  • PWM gate (switching/current path gating): enables wide dimming ratio and clear dim-to-off, but is constrained by minimum pulse width and can create low-frequency ripple if energy is delivered in bursts. Watch for bursty TP_SW patterns and low-frequency envelope in TP_ILED.

A practical rule: deep-dim validation must be done at the lowest dim point, not only at mid-level brightness.

No-flicker checklist (measurable, topology-specific)
  • PWM frequency chosen so dimming does not create a strong low-frequency envelope in TP_ILED.
  • Minimum pulse width stays above controller min on/off-time; confirm on TP_SW at the deepest dim setting.
  • Dim-to-off transitions do not cause overshoot bumps; confirm TP_ILED and TP_VOUT at edges.
  • ILED ripple vs dim level does not spike at 10% and 1% points; log ripple% across the range.
  • TP_COMP behavior remains within a normal band; avoid hunting (sawtooth wandering) at low brightness.
  • Switching pattern avoids burst clusters that repeat in the visible range; verify TP_SW continuity.
  • Repeatability: power-cycle and brownout tests at deep dim produce the same waveform family (no intermittent modes).

Evidence fields to log: PWM frequency, min pulse width, dim-to-off threshold, ripple% at multiple dim points, and low-frequency ripple notes.

Figure F8 — Dimming injection points comparison (REF vs COMP gate vs PWM gate)
Dimming Injection Points (Boost CC) Pick the injection point that preserves stability at deep dim REF injection Analog dim COMP gate / clamp Limit control effort PWM gate Hard on/off Power stage L • SW • D/SR • COUT LED + Rsense EA COMP Inject at REF Risks Offset Noise Drift Power stage L • SW • D/SR • COUT LED + Rsense EA COMP Gate at COMP Risks Nonlinear Recovery Bump Power stage L • SW • D/SR • COUT PWM gate min pulse matters LED + Rsense Risks MinPW LF ripple Hunt Evidence: PWM f • MinPW • ILED LF ripple
Compare injection points using the same Boost CC loop skeleton. Deep-dim issues most often appear as minimum-pulse limits, COMP hunting, or low-frequency ripple in TP_ILED. Cite this figure: See References (conceptual injection points; confirm controller pin behavior and timing limits in the datasheet).
References (placeholder)

Add the specific controller datasheet/app note for: UVLO thresholds/hysteresis, soft-start implementation, OVP behavior during startup, and dimming input timing limits (minimum pulse width / dimming modes). This placeholder supports the “Cite this figure” links.

H2-9. Layout, EMI, and Thermal: The Three Places Boost CC Usually Breaks

Construction checklist — prevent EMI → loop noise → false protection

In a boost constant-current driver, layout errors rarely stay “just EMI.” The same mistake that enlarges the hot loop also injects switching noise into current sensing and can distort protection thresholds. This section focuses on the three break points: (1) hot current loops, (2) sensitive Kelvin sense routing, and (3) thermal paths.

hot-loop area SW dv/dt sense coupling return path PGND/AGND join ΔT (FET/diode)
1) Hot loop (power loop) — smallest area wins
  • Keep the high di/dt loop tight: place CIN and its return so the current path from VIN → SW device → return → CIN is the shortest possible closed loop. A larger hot-loop area typically increases radiated/conducted noise and makes TP_SW ringing worse.
  • Control the SW node geometry: keep the SW copper small and local to the power stage. Large SW copper spreads dv/dt to nearby traces and layers, which often appears as synchronous spikes on TP_ISENSE and TP_COMP.
  • Return path is part of the loop: every “forward” trace needs a deliberate return path. If switching return currents share the same path as the sense reference, current regulation noise and protection mis-trips become likely.

Evidence fields: hot-loop area (layout), SW dv/dt/ringing (scope at TP_SW), and synchronous noise on TP_ISENSE/TP_COMP.

2) Kelvin sense + ground strategy — protect the CC loop from SW noise
  • True Kelvin routing: run a dedicated pair from Rsense directly to the error amplifier inputs. Do not “tap” sense from a shared copper region where switching currents flow.
  • Sense keepout near SW: do not route sense traces under/near the SW copper or parallel to fast edges. If coupling is present, TP_ISENSE often shows spikes aligned with TP_SW, and deep-dim behavior becomes unstable.
  • Single-point join (PGND/AGND): keep the power return (PGND) and analog/sense reference (AGND) separate until a deliberate star-join near the controller reference point. This reduces ground bounce appearing as “fake current.”

Evidence fields: sense trace coupling (spike correlation with TP_SW), ground split/join location, and CC ripple/hunting at low dim.

3) Thermal path — temperature rise changes switching, sensing, and protection timing
  • Hot devices are not only an efficiency issue: MOSFET/diode temperature rise can change switching behavior, which changes SW ringing and dv/dt, which then feeds back into sensing noise and false protection triggers.
  • Current accuracy drifts with temperature: sense resistor self-heating and thermal gradients can shift ILED. Verify ILED at hot steady-state, not only at room temperature.
  • Derating behavior must be observable: if thermal foldback or protection is expected, verify the transition is smooth (no oscillation between “cool” and “protect” states).

Evidence fields: MOSFET/diode ΔT vs time, ILED drift vs temperature, and any increase in synchronous noise on TP_COMP at hot.

Symptom → evidence → likely layout root cause (quick triage)
  • Startup sometimes trips OVP: TP_VOUT overshoot + heavy TP_SW ringing → SW copper spread / hot-loop too large / CIN return not tight.
  • Deep dim hunting or flicker proxy increases: TP_COMP wandering + spikes on TP_ISENSE → sense routed near SW / shared return path (PGND/AGND not controlled).
  • Load-step overshoot is inconsistent board-to-board: same settings, different transient → ground bounce + parasitic coupling into COMP/sense nodes.
  • Works cold, breaks hot: rising ΔT increases ringing/noise and shifts thresholds → insufficient thermal spreading on MOSFET/diode/Rsense, plus noise coupling worsens at temperature.
Figure F9 — PCB loop + sensitive routing map (keepout zones)
PCB Map: Loops + Kelvin Sense Keepout Draw the current loops first; route sense last Board region CIN SW + FET hot node Inductor D / SR COUT LED Rsense Controller EA • COMP • OVP KEEP OUT (SW dv/dt) dv/dt HOT LOOP Kelvin sense PGND ↔ AGND join Sense/COMP: do not cross SW zone Acceptance hot-loop area SW dv/dt sense coupling return path ΔT (FET/diode)
The dashed box is the SW dv/dt keepout. Keep Kelvin sense away from SW copper and avoid shared return paths. Cite this figure: See References (conceptual PCB map; verify per controller and layout guidelines).

H2-10. Validation Plan: Bring-Up → Loop Check → Fault Injection → Dimming Sweep

Repeatable SOP — test points, pass/fail gates, and debug routing

A boost CC driver can appear “fine” at nominal brightness and still fail in the real edge cases: cold start, brownout recovery, open-string protection, or deep dimming. This validation plan is organized as a gated workflow: bring-up safely, confirm loop behavior, inject faults, then sweep dimming. Each stage defines test points, acceptance criteria, and where to look next if the gate fails.

TP_VINTP_SWTP_ILTP_VOUT TP_COMPTP_ISENSETP_ILED
Stage 1 — Bring-up (survive first)
  • Measure: TP_VIN, TP_SW, TP_IL, TP_VOUT.
  • Pass gate: VOUT overshoot stays below OVP with margin; IL peak is controlled (no repeated burst clusters); SW ringing is bounded.
  • If fail: overshoot/OVP → H2-7 (startup) and H2-9 (SW/loop). IL spike → H2-7 (soft-start) and H2-9 (CIN/hot loop).
Stage 2 — Loop check (confirm stability in the real plant)
  • Measure: TP_COMP (band and saturation), TP_ILED/TP_ISENSE ripple, and a controlled current/command step.
  • Pass gate: COMP stays within a normal range (not pinned); step response settles without sustained ringing; ripple% remains stable across operating points.
  • If fail: hunting/oscillation → H2-5 (compensation) plus H2-9 (sense coupling/ground bounce).
Stage 3 — Fault injection (open/short/brownout behavior must be predictable)
  • Open-string: record OVP trip point (VOUT), clamp behavior, and whether recovery is auto or latched.
  • Hiccup/retry: record hiccup period, IL_peak during retries, and conditions that re-enter normal mode.
  • Brownout: dip VIN below UVLO_f and restore; confirm repeatable restart without stuck states.
  • If fail: repeated stress in fault mode → H2-6/H2-7. False trips → H2-9 (layout noise into sense/protection).
Stage 4 — Dimming sweep (0–100% to find the real “risk points”)
  • Sweep: 100% → 10% → 1% → dim-to-off (and back). Log ripple% and any low-frequency envelope in TP_ILED.
  • Timing: confirm minimum pulse width at the deepest dim setting on TP_SW (PWM gating cases).
  • Pass gate: no unstable COMP wandering; no burst clusters in SW; ripple and low-frequency envelope do not spike at deep dim.
  • If fail: deep-dim instability → H2-8 (injection choice + timing) and H2-9 (sense noise coupling).

Evidence fields to save per sweep point: dim level, PWM frequency, min pulse width, ripple%, and a short note about low-frequency ripple.

Figure F10 — Validation flowchart with pass/fail gates
Validation SOP (Gated) Bring-up → Loop → Faults → Dimming • Each step has a pass/fail gate 1) Bring-up 2) Loop check 3) Fault injection 4) Dimming sweep TP_VIN • TP_SW • TP_IL • TP_VOUT Gate: VOUT_ovsh, IL_peak, SW ringing TP_COMP band • step response • ripple% Gate: no pinning, settle cleanly Open-string OVP • hiccup period • recover Brownout: VIN < UVLO_f then restart 100→10→1% • MinPW • LF ripple proxy PASS Proceed to next stage Result Stable CC + predictable faults No deep-dim instability FAIL Route to the right chapter Overshoot/OVP → H2-7/H2-9 Hunting → H2-5/H2-9 Fault stress → H2-6/H2-7 Deep dim → H2-8/H2-9 Brownout → H2-7
Each gate forces a measurable decision: keep waveforms, log evidence fields, and route failures to the matching chapter. Cite this figure: See References (conceptual SOP; confirm protection behavior and dimming limits per controller datasheet).
References (placeholder)

Add the specific controller datasheet/app notes used for: layout recommendations (hot-loop, SW copper), current-sense routing (Kelvin/AGND), protection behavior under faults, and dimming timing limits. This placeholder supports the “Cite this figure” links.

H2-11. Field Debug Playbook: Symptom → 2 Measurements → Discriminator → First Fix

Fast diagnosis with minimal tools (6 common symptoms)

This playbook is structured for repeatable field debugging: each symptom starts with exactly two measurements, then a single discriminator splits the root cause into two likely buckets, followed by a first fix that maps back to earlier evidence points (TP_COMP, TP_ISENSE, TP_SW, TP_VOUT, TP_IL, and thermal ΔT).

Note: Example MPNs below are typical, not universal. Verify voltage/current rating, package, and temperature range for the target LED string and VIN.

Symptom 1

LED flicker / “breathing” (worse at deep dim)

First 2 measurements

  • TP_COMP: look for slow wandering / limit cycling (COMP “hunting”) versus a stable COMP level.
  • TP_ILED (or TP_ISENSE): check ripple % and low-frequency envelope at deep dim points (e.g., 10% → 1% → dim-to-off).

Discriminator

  • COMP hunting (slow oscillation) → closed-loop stability / injection strategy issue (often exposed at deep dim).
  • COMP stable but ILED shows periodic dropouts → PWM gating / minimum pulse width / dimming timing artifact.

First fix (safe first steps)

  • Reduce loop bandwidth (move the compensation zero down, or increase COMP capacitance) to stop hunting at deep dim.
  • If PWM gated: increase PWM frequency and enforce a minimum on-time; consider moving dim injection to a smoother point (REF/EA reference path).
  • Add a small RC filter / deglitch on the dim input if edges are injecting noise into the control node.

Evidence fields to log: dim level, PWM frequency, minimum pulse width, COMP range (min/max), ILED ripple %, presence of low-frequency envelope.

Example MPNs (typical)
  • RC filter parts: Yageo RC0603FR-0710KL (10 kΩ, 0603, 1%) + Murata GRM188R71H104KA93 (0.1 µF, 50 V, X7R, 0603)
  • Comp cap option: Murata GRM188R71H105KA12 (1.0 µF, 50 V, X7R, 0603)
  • Small timing cap option: TDK C1608X7R1H103K (0.01 µF, 50 V, X7R, 0603)
Symptom 2

Startup “flash” then stabilizes

First 2 measurements

  • TP_VOUT: capture overshoot peak at power-up (especially near UVLO crossing).
  • TP_IL: observe inductor current ramp (too fast / bursty ramp indicates overly aggressive startup).

Discriminator

  • IL rises too fast + VOUT spikes → soft-start / current limit ramp is too aggressive.
  • VOUT hits near OVP then “gets clamped” → OVP clamp is intervening (often LED not yet conducting or open-string window too tight).

First fix

  • Slow the soft-start ramp (increase SS capacitance or reduce SS charge current) to limit IL ramp and VOUT overshoot.
  • Add/adjust a startup blanking window for open-string detection so OVP does not trigger before LED conduction is established.
  • If a clamp device is used: confirm the clamp does not “ring” the system (layout + controlled clamp).

Evidence fields to log: UVLO_r/UVLO_f, VOUT peak, IL_peak at startup, COMP trajectory during startup, OVP threshold and any clamp engagement time.

Example MPNs (typical)
  • Soft-start capacitor option: Murata GRM188R71H105KA12 (1.0 µF, 50 V, X7R, 0603)
  • Clamp TVS examples (choose voltage carefully): Littelfuse SMBJ58A or Bourns SMBJ58A (SMBJ series TVS)
  • Bleed / precharge resistor option: Yageo RC1206FR-07100KL (100 kΩ, 1206, 1%)
Symptom 3

Intermittent OVP / “open-string” false alarms

First 2 measurements

  • TP_VOUT: verify whether VOUT truly rises toward OVP during the event.
  • TP_ISENSE: look for spikes synchronized with TP_SW edges (sense coupling / ground bounce signature).

Discriminator

  • ISENSE spikes correlate with SW edges → layout coupling (Kelvin routing or shared return) causing false detection.
  • ISENSE clean but VOUT truly increases → real LED conduction interruption (connector intermittency, string fault, or genuine open-string).

First fix

  • Re-route Kelvin sense pair away from SW copper and enforce a clean PGND/AGND single-point join.
  • Add a small RC filter or deglitch (blanking) on the sense/protection input so switching spikes cannot trip the detector.
  • If the controller supports it: increase open-string qualification time instead of raising thresholds.

Evidence fields to log: VOUT at trip, OVP trip voltage, ISENSE spike amplitude, spike-to-SW correlation, hiccup period and recovery condition.

Example MPNs (typical)
  • Sense RC deglitch: Panasonic ERJ-3EKF1002V (10 kΩ, 0603, 1%) + Murata GRM188R71H103KA01 (0.01 µF, 50 V, X7R, 0603)
  • Ferrite bead (noise isolation example): Murata BLM21PG221SN1D (220 Ω @ 100 MHz, 0805)
  • Small cap for edge filtering (option): TDK C1608X7R1H102K (1 nF, 50 V, X7R, 0603)
Symptom 4

Brightness not accurate / channel mismatch (multi-string variants)

First 2 measurements

  • Measure the true differential drop across Rsense (Kelvin probe) during steady-state.
  • Measure temperature rise near Rsense and the primary hot device (MOSFET/diode) to correlate drift vs heat.

Discriminator

  • Sense drop drifts with temperature → shunt self-heating / tempco dominates ILED error.
  • Sense drop stable but reported/controlled ILED differs → offset, ground bounce, or sense reference contamination.

First fix

  • Upgrade shunt resistor accuracy and thermal behavior; improve copper heat spreading around Rsense.
  • Enforce true Kelvin routing to the controller sense pins; avoid sharing return currents with the sense reference.
  • If sense filtering is used: keep RC small enough to avoid adding control lag that distorts regulation.

Evidence fields to log: ILED accuracy (%), Rsense tolerance, inferred shunt temperature rise, EA offset/gain error assumption, ground bounce signature on ISENSE.

Example MPNs (typical)
  • Precision shunt examples (choose value/rating to match ILED): Vishay WSL2512R1000FEA (0.1 Ω, 2512) or Bourns CRE2512-FZ-R100E-2 (0.1 Ω, 2512)
  • Lower-ohm option (higher current designs): Vishay WSL2512R0100FEA (0.01 Ω, 2512)
  • Kelvin-friendly resistor layout often pairs with: Yageo RC0603FR-07499RL (499 Ω, 0603, 1%) for small sense filters
Symptom 5

Runs hot at high brightness / efficiency collapses

First 2 measurements

  • Measure MOSFET and diode (or synchronous rectifier) temperature rise (ΔT) at steady-state high output.
  • Capture TP_SW: check ringing amplitude, edge speed, and any abnormal conduction timing signature (excessive overshoot or long ringing).

Discriminator

  • MOSFET hottest + very fast edges → switching loss dominant (dv/dt too aggressive, gate drive too strong, frequency too high for the layout).
  • Diode/SR hottest + large SW ringing → recovery/ringing-related loss (snubber need, diode selection, or timing/layout issue).

First fix

  • Slow the switching edge slightly (increase gate resistor) before changing architecture-level decisions.
  • Add a small RC snubber at the ringing source (layout tight) to reduce ringing energy and secondary heating.
  • Improve thermal spreading copper and via stitching under hot parts; confirm airflow assumptions during validation.

Evidence fields to log: ΔT(MOSFET/diode) vs time, SW ringing peak-to-peak, switching frequency, gate resistor value, ILED at hot steady-state.

Example MPNs (typical)
  • Gate resistor option: Panasonic ERJ-3EKF10R0V (10 Ω, 0603, 1%)
  • Snubber pair example: Panasonic ERJ-3EKF51R0V (51 Ω, 0603, 1%) + Murata GRM188R71H102KA01 (1 nF, 50 V, X7R, 0603)
  • Diode example for higher-voltage rails (verify VRRM/IF): STMicro STPS5H100 (100 V Schottky class)
Symptom 6

EMI pre-check fails / AM radio interference

First 2 measurements

  • TP_SW: measure dv/dt and ringing energy (long ringing and high overshoot usually correlates with radiated noise).
  • TP_VIN at the input capacitor: measure input ripple/edge spikes during switching (indicates filter/return weakness).

Discriminator

  • SW ringing large → hot loop / SW geometry / snubber placement issue (layout first).
  • VIN ripple large but SW manageable → input filtering / return path needs reinforcement (π filter tuning, placement).

First fix (no compliance deep dive)

  • Shrink the hot loop and limit SW copper spread before adding more parts.
  • Add a compact RC snubber at the ringing source (short loop) to reduce high-frequency energy.
  • Add a simple input π filter (capacitor–ferrite/inductor–capacitor), placed to control the current return path.

Evidence fields to log: SW edge rate/ringing, input ripple peak-to-peak, hot-loop visual area, bead/inductor position, any change in false trips after EMI fixes.

Example MPNs (typical)
  • Ferrite bead example (π filter element): Murata BLM21PG221SN1D (220 Ω @ 100 MHz, 0805)
  • Input MLCC example: Murata GRM31CR71H106KA12 (10 µF, 50 V, X7R, 1206)
  • RC snubber example: Panasonic ERJ-3EKF51R0V (51 Ω, 0603, 1%) + Murata GRM188R71H102KA01 (1 nF, 50 V, X7R, 0603)
  • TVS example for input surge/ESD staging (verify voltage): Littelfuse SMBJ58A (SMBJ TVS series)
Figure F11 — Decision tree: flicker / OVP / startup / heat / EMI
Field Debug Decision Tree (Boost CC) Symptom → measure 2 points → discriminator → first fix Symptom 2 Measurements Discriminator First fix Deep-dim flicker TP_COMP TP_ILED COMP hunting? Yes → loop No → PWM Lower BW (H2-5) Tune PWM/inject (H2-8) Startup flash TP_VOUT TP_IL Overshoot? SS vs OVP Extend SS (H2-7) Blanking/OVP (H2-6/7) OVP false alarm TP_VOUT TP_ISENSE ISENSE spikes? Coupling vs real Kelvin reroute (H2-9) RC deglitch (H2-4) Brightness error ΔV Rsense ΔT shunt Drift with heat? Shunt vs offset Upgrade shunt (H2-4) Fix returns (H2-9) Runs too hot ΔT FET/D TP_SW Ring/edge? Switch vs ring Gate R + snub Thermal copper (H2-9) EMI / radio noise TP_SW TP_VIN Ring vs ripple Layout vs filter Shrink hot loop (H2-9) Snub/π filter (H2-9)
Six symptom entries lead to two measurements each, then a discriminator and a safe first fix. Cite this figure: See References (MPN examples require datasheet confirmation for the target voltage/current).
References (placeholder)

Add vendor datasheets / product pages for the listed example MPNs (TVS, MLCCs, shunts, ferrite beads, resistors, diodes), plus the specific boost LED controller datasheet/app notes used for: soft-start behavior, OVP/open-string detection, and dimming timing limits.

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H2-12. FAQs (Boost Constant-Current LED Driver)

Each answer stays within boost CC scope and maps back to earlier chapters via measurable evidence fields (TP points, thresholds, and stability indicators).

VIN is stable, but brightness still drifts—sense resistor tempco or loop bias?

Drift with stable VIN is usually a temperature-driven current error or a control-node bias shift. Measure the true differential drop across Rsense (Kelvin probe) and track TP_COMP DC level over temperature. If ΔV(Rsense) changes with heat, shunt tempco/self-heating dominates. If ΔV is steady but TP_COMP shifts, offset/ground-bounce or compensation bias is likely. First fix: improve Kelvin routing and shunt thermal spreading.

Maps back to: H2-4 (Error budget) · H2-5 (Loop compensation)

Example MPNs (typical): Vishay WSL2512R1000FEA (0.1Ω shunt), Bourns CRE2512-FZ-R100E-2 (0.1Ω shunt), Murata GRM188R71H104KA93 (0.1µF X7R).

Why does open-string trigger only at cold start?

Cold start can shift LED conduction timing and raise the chance that VOUT ramps into the open-string/OVP window before current regulation settles. Measure TP_VOUT peak during the first tens of milliseconds and log UVLO rising threshold and any startup blanking timer behavior. If VOUT reaches the OVP threshold before ILED establishes, false open-string is likely. First fix: lengthen soft-start/blanking and qualify open-string after ILED is stable.

Maps back to: H2-6 (Open-string/OVP) · H2-7 (UV/OV & startup)

Example MPNs (typical): Murata GRM188R71H105KA12 (1µF X7R for SS), Yageo RC1206FR-07100KL (100k bleed), Littelfuse SMBJ58A (TVS example—verify voltage).

Deep dimming flickers—PWM frequency or compensation hunting?

Deep-dim flicker is either PWM timing artifacts or a low-frequency limit cycle in the CC loop. Measure TP_COMP for slow hunting and measure TP_ILED ripple with attention to low-frequency envelopes at 10%→1%→dim-to-off. If TP_COMP oscillates, loop bandwidth/phase margin is too aggressive for deep dim conditions. If TP_COMP is stable but ILED drops periodically, PWM minimum pulse width or gating placement is the driver. First fix: reduce bandwidth or revise dim injection.

Maps back to: H2-8 (Dimming injection) · H2-5 (Compensation)

Example MPNs (typical): Panasonic ERJ-3EKF1002V (10k), Murata GRM188R71H103KA01 (0.01µF) for deglitch RC on DIM/CTRL nodes.

OVP trips when LEDs are fine—what noise path causes false detection?

False OVP often comes from switching-edge coupling into the sense/protection comparator reference path. Measure TP_ISENSE and correlate spikes with TP_SW edges while watching TP_VOUT near the trip. If TP_ISENSE spikes line up with SW transitions, Kelvin routing or shared return currents are injecting noise that looks like an open-string condition. If TP_ISENSE is clean but VOUT actually rises, the trip is real. First fix: reroute Kelvin pair away from SW copper and add small deglitch filtering/blanking.

Maps back to: H2-6 (OVP logic) · H2-9 (Layout/EMI)

Example MPNs (typical): Murata BLM21PG221SN1D (ferrite bead), Murata GRM188R71H102KA01 (1nF), Panasonic ERJ-3EKF51R0V (51Ω) for small filters/snubber experiments.

Startup flashes once—soft-start ramp or output capacitor energy?

A one-time flash typically comes from an early VOUT overshoot or an inductor current ramp that briefly overdrives the LED string before CC regulation closes. Measure TP_VOUT peak and TP_IL ramp during the first startup interval. If IL ramps sharply, soft-start is too fast. If IL is controlled but VOUT surges, output capacitor charge and open-string qualification timing are likely. First fix: slow soft-start and delay open-string decisions until LED conduction is established.

Maps back to: H2-7 (Startup/soft-start)

Example MPNs (typical): Murata GRM188R71H105KA12 (1µF X7R), Murata GRM188R71H104KA93 (0.1µF X7R) for SS/blanking timing networks (verify controller pin specs).

Duty cycle near max causes instability—what’s the safe bandwidth rule?

Near-max duty operation reduces effective control margin and amplifies delays and right-half-plane behavior, so overly high crossover can produce oscillation or slow hunting. Estimate duty at VIN(min)/VLED(max), then measure TP_COMP response to a small load/current step and check for ringing. If oscillation increases as duty rises, the crossover is too aggressive for the plant. First fix: lower crossover and keep it well below dominant plant “do-not-cross” features (RHPZ/output pole) and controller min on/off limits.

Maps back to: H2-5 (Comp design) · H2-3 (Duty/ripple limits)

LED ripple is low, but camera banding appears—what should be measured?

Camera banding is often driven by low-frequency modulation or PWM interaction with exposure timing even when high-frequency ripple looks small. Measure TP_ILED with a timebase that reveals low-frequency envelopes (tens of Hz to a few kHz) and log PWM frequency, minimum pulse width, and dimming waveform shape. Then run a dimming sweep and identify the banding-prone ranges. First fix: raise PWM frequency, avoid narrow pulses, and prefer a dimming injection method that minimizes low-frequency current modulation at deep dim levels.

Maps back to: H2-8 (Dimming) · H2-10 (Validation sweep)

Short-string event damages parts—clamp strategy or OCP response time?

A short-string event can abruptly change VOUT operating point and force the power stage into high stress if the protection path is slow or the clamp absorbs too much energy. Measure TP_VOUT peak/undershoot during the event and capture TP_IL peak and duration. If IL peaks exceed safe device limits before protection acts, OCP response/blanking is too slow. If IL stays controlled but VOUT overshoots and parts heat, clamp strategy and placement are suspect. First fix: tighten OCP timing and verify clamp energy rating and layout loop.

Maps back to: H2-6 (Protection/clamp)

Example MPNs (typical): Littelfuse SMBJ58A (TVS example—verify voltage), Panasonic ERJ-3EKF51R0V (51Ω) + Murata GRM188R71H102KA01 (1nF) for snubber experiments (tune to waveform).

Why does CC accuracy worsen after layout change?

Layout changes can inject switching noise into the sense path or alter ground reference, turning true current regulation into “regulation plus error.” Measure the true ΔV across Rsense with a Kelvin probe and compare it to TP_ISENSE at the controller pin while also observing TP_SW edges. If the controller-side sense shows spikes or offset relative to the Kelvin measurement, routing/return coupling is the root. First fix: restore Kelvin pair routing, keep it away from SW copper, and enforce a clean AGND/PGND join.

Maps back to: H2-9 (Layout) · H2-4 (Sense error)

EMI fails only at certain dim levels—what coupling mechanism is typical?

EMI that appears only at certain dim points usually comes from PWM gating sidebands, burst patterns, or control-node injection that changes the switching spectrum. Measure TP_SW ringing and dv/dt across multiple dim levels and measure input ripple at TP_VIN near the input capacitors. If the spectrum worsens when PWM pulses become narrow or discontinuous, gating/injection is the trigger. First fix: avoid very narrow PWM pulses, increase PWM frequency, and add a tight snubber or input π filter placed to control current return paths.

Maps back to: H2-9 (EMI/layout) · H2-8 (Dimming)

Example MPNs (typical): Murata BLM21PG221SN1D (bead), Murata GRM31CR71H106KA12 (10µF 50V X7R), Panasonic ERJ-3EKF51R0V + Murata GRM188R71H102KA01 (snubber pair).

Hiccup recovery takes too long—what timers/thresholds matter?

Long hiccup recovery is typically set by fault qualification time, latch behavior, and restart timers, not by the power stage itself. Measure the hiccup period (time between restart attempts) and capture TP_VOUT and TP_ISENSE during the retry to see whether the fault clears before the timer allows recovery. If VOUT/ISENSE look normal but retries remain delayed, timing parameters dominate. First fix: shorten restart timer or adjust qualification thresholds while keeping enough blanking to prevent false trips under switching noise.

Maps back to: H2-6 (Fault logic) · H2-10 (Fault injection & logs)

How to validate loop stability without a network analyzer?

Loop stability can be screened using time-domain indicators: load/current step response and control-node headroom. Apply a small, controlled step in LED current command or load and observe TP_COMP for saturation and recovery while measuring ILED overshoot and settling time. If TP_COMP rails or rings and ILED shows underdamped oscillation, phase margin is insufficient. First fix: reduce crossover or adjust compensation zero placement, then re-run the same step at high duty and deep dim conditions.

Maps back to: H2-10 (Validation SOP) · H2-5 (Compensation)