Choose a Downlight/Panel PSU when the product needs mains-side power quality (PF/THD), reinforced/basic isolation, and a predictable CV/CC output behavior with measurable evidence for compliance and reliability.

This page treats the PSU as a system: AC input → EMI filter → bridge → boost PFC → DC bus → isolated DC/DC → CV/CC output → LED load, plus safety boundaries and health monitoring. Topology-specific deep dives (AC-direct, isolated flyback/LLC details) belong to their dedicated pages.

Decision gates that justify this PSU class

• Power-quality gate (PFC): target PF/THD under rated line and rated load. If the market or power level demands predictable input-current shaping, a boost PFC front-end is the default route.
• Safety gate (isolation): fixture class and touch-safety typically drive an isolation barrier with defined creepage/clearance and leakage-current budget (especially when Y-capacitors are used for EMI).
• Output-behavior gate (CV/CC): the load and LED module strategy require stable constant-current operation or a controlled CV/CC handoff without visible artifacts. Dimming protocol implementation may live outside the PSU; this page only defines the interface responsibility.

Inputs to lock before design or sourcing

• VAC range: nominal + low-line + high-line conditions (and whether brownout ride-through is required).
• Pout band: low / mid / high power mapping for thermal headroom, EMI margin, and PFC stress.
• PF / THD targets: measured at full load after thermal steady-state (define line condition and measurement method).
• Hold-up time: minimum time the output remains within spec after mains removal (driven mainly by DC bus energy storage).
• Dimming responsibility: PSU-only (analog/PWM input) vs external controller (DALI/DMX/etc. handled elsewhere).

Acceptance evidence to record (minimum set)

• VAC range coverage: low-line / nominal / high-line functional pass.
• PF@full load: measured at rated line + rated load after thermal steady-state.
• THD: measured under the same conditions as PF (avoid mixing measurement setups).
• Hold-up time: mains removal → time until output leaves regulation window.
• Output ripple: ripple amplitude and bandwidth limit declared (ripple can map into flicker risk and EMI behavior).

A downlight/panel PSU is best understood as a chain of energy conversion plus a parallel chain of risk control (conducted EMI, isolation/leakage, thermal/lifetime, fault handling). The architecture below defines the reference test points used throughout validation and debugging.

Architecture checklist (module intent)

1. Input EMI filter: shapes the conducted-noise path before the bridge; also impacts inrush and leakage (via X/Y parts).
2. Bridge rectifier: sets the rectified mains baseline; thermal and surge stress often localize here.
3. Boost PFC stage: aligns input current with mains voltage (PF/THD) and establishes a regulated DC bus.
4. DC bus energy storage: sets hold-up behavior and 100/120 Hz ripple stress (lifetime driver for bulk capacitors).
5. Isolated DC/DC: enforces the safety boundary and delivers a controlled secondary rail for CV/CC regulation.
6. CV/CC output control: enforces LED current (or regulated rail) across load/temperature variation with predictable protection responses.
7. Protection + monitoring: defines fault thresholds, restart policy, thermal derating, and field evidence (counters/events).
8. Bleeder/discharge: safely discharges energy storage after power-off (safety + service + predictable re-start behavior).

Test point map (evidence anchors)

Later chapters will reference TP1–TP6 explicitly to keep every claim measurable and repeatable.

The boost PFC stage sets the PSU’s grid-facing signature (PF/THD) and the PSU’s downstream stability envelope (DC-bus ripple, startup behavior, brownout handling). Treat it as a system coupling point: issues here often reappear as CV/CC jitter, output ripple, or nuisance protection events.

Evidence must be repeatable: PF/THD is only meaningful when the line condition, load point, and thermal state are fixed and recorded.

Checklist (system-level levers)

• PF/THD targets + current-mode choice: mention CCM/CrM only as a selection knob (power band, EMI sensitivity, light-load behavior). Avoid theory; focus on what changes in waveforms and margins.
• Brownout threshold + start policy: set entry/exit thresholds with hysteresis and time qualification so the PSU does not “bounce” during weak mains or long cable drops.
• Inrush strategy trade-off: NTC / relay bypass / active inrush. The best choice depends on “hot re-plug” expectations, breaker sensitivity, EMI X-cap charging, and BOM/complexity.
• DC-bus ripple coupling risk: bus ripple at 100/120 Hz (TP2) can modulate the isolated stage’s operating point and destabilize CV/CC handoff—measure correlation between TP2 and TP4.

Evidence fields (minimum record set)

• Input waveforms: capture mains voltage and input current on the same timebase (shows phase alignment and distortion signatures).
• PF/THD measurement conditions: document VAC (low/nom/high), load level (full load primary), and “thermal steady-state” status.
• TP2 DC-bus ripple: record ripple amplitude at 100/120 Hz and how it moves with load changes (this is the coupling “handle”).
• Startup inrush peak: record peak input current and any line droop / breaker trip symptoms; note “cold start” vs “hot re-plug”.

Practical debug hint: if output artifacts appear, always check whether TP2 ripple and TP4 ripple share the same low-frequency envelope; if yes, treat PFC/bus as the primary suspect before tuning the secondary loop.

Common failure modes to prevent

• PF looks OK but THD spikes: current “flat-topping” or notches—often visible immediately in the input-current waveform even before a numeric report.
• Brownout chatter: threshold too close to operating point, missing hysteresis/time filter → repeated restart cycles (visible as TP2 sawtooth ramps).
• Inrush fixes EMI but trips breakers: X-cap charging and bridge stress can dominate; confirm peak current and line droop during plug-in.
• Bus ripple drives downstream jitter: TP2 envelope modulates the isolated stage and later appears as CV/CC switching jitter or output flicker risk.

CV/CC integration is not a topology lesson. The goal is a stable handoff between voltage regulation and current regulation, with clear priority/limiting rules that prevent visible artifacts (flicker-like modulation), audible noise, and nuisance protection triggers under load dynamics.

Key idea: if the CV loop and CC loop “fight” for authority, the output becomes a modulated waveform. The fix is usually in handoff policy, hysteresis/clamps, or upstream ripple coupling (TP2 → control) rather than in the LED load itself.

Checklist (handoff stability levers)

• Handoff condition: define the CV→CC and CC→CV transition criteria with hysteresis or soft limiting to avoid rapid toggling near the boundary.
• Priority + clamp logic: decide which loop is “master” and which loop provides a limiter (current clamp or voltage clamp). Keep the limiter smooth to prevent “bang-bang” behavior.
• Load dynamics interaction: different LED modules behave differently (direct strings vs driver boards with large capacitance). Design for the worst dynamic impedance case and validate with load steps.
• Ripple-to-flicker path (system-level): treat TP2 low-frequency envelope and TP4 ripple correlation as a first-class diagnostic before tuning the secondary loop bandwidth.

Evidence fields (what to measure)

• CC accuracy: steady-state LED current accuracy at rated conditions and near the transition boundary.
• CV accuracy: voltage regulation accuracy (if used) across load variation and temperature.
• Load-step response: capture TP4 response for step-up and step-down; record settling time and overshoot/undershoot.
• Handoff waveform: capture the transition moment (TP4) and the control evidence node (TP6) to prove whether it’s loop competition or true load fault.

Recommended correlation check: log TP2 bus envelope, TP4 ripple, and TP6 clamp activity. If TP6 repeatedly hits a clamp while TP2 is moving, treat the issue as “handoff policy + coupling,” not “random load behavior.”

Output ripple → visible risk (path-only, no detours)

• Low-frequency envelope: TP2 bus ripple can propagate into regulation margin and appear as a low-frequency modulation at TP4 during or near CV/CC boundary.
• High-frequency residue: switching ripple and layout/EMI interactions can appear at TP4 and confuse measurements unless bandwidth is stated.
• Suppression handles: reduce coupling (bus → secondary), enforce smooth clamp behavior, and verify with bandwidth-limited measurements.

Conducted EMI becomes manageable when noise is treated as current loops with a source, a return path, and a coupling mechanism. This section locks the workflow: identify DM vs CM paths → assign each filter part a role → minimize hot-loop area → prove improvement with repeatable evidence.

Priority: pass conducted emission first; then revisit any remaining coupling that turns into radiated problems.

Component roles (DM/CM path ownership)

• CM choke: raises impedance for common-mode noise current while keeping normal line current nearly unaffected.
• DM inductor: raises impedance for differential-mode noise; affects input ripple and may change PF/THD behavior if pushed too far.
• X-cap (L–N): provides a high-frequency bypass for DM noise; requires a safe discharge path (bleeder) and can influence inrush behavior.
• Y-cap (L/N→PE or primary→reference): creates a controlled return path for CM noise; improves EMI but consumes leakage-current budget (handshake with Safety).
• Bleeder/discharge: supports safety discharge requirements; increases standby loss—select value by discharge time vs power budget.

Layout levers (what matters most)

• Minimize hot-loop area: PFC switch loop and rectifier/bulk loop are the highest di/dt offenders—reduce loop area before adding parts.
• Control dv/dt coupling: keep the high dv/dt switching node away from input/filter and sensing circuits; avoid broad copper that “broadcasts” CM energy.
• Filter placement discipline: place the input filter close to the input connector so DM/CM currents close locally (not across the board).
• Return-path clarity: ensure Y-cap return and PE/chassis reference are intentional; uncontrolled returns often “move” the noise rather than reduce it.

Evidence fields (prove the fix)

• LISN spectrum: compare before/after changes and note which frequency band moved (DM filters often affect lower bands; CM paths often show distinct patterns).
• Switch-node dv/dt: capture waveforms to explain CM bursts; correlate spikes with LISN peaks.
• Return-path check: verify where CM current returns (PE/chassis/reference) and whether it crosses sensitive zones.

Safety must be implemented as boundaries and budgets, not a list of terms. Start by drawing the insulation barrier between Primary (mains), Secondary (SELV/output), and PE/Chassis (if present), then validate leakage and spacing with evidence.

Any CM-EMI improvement using Y-cap or parasitic return must be checked against leakage-current limits and insulation boundary integrity.

Leakage current control (Y-cap budgeting)

• Budget first: define the allowable leakage current under the intended test conditions (line, frequency, PE connection, operating mode).
• Placement matters: Y-cap location and return loop decide whether leakage is useful (controlled CM return) or harmful (uncontrolled coupling).
• Watch hidden contributors: parasitic capacitance from high dv/dt nodes to secondary/chassis can add leakage-like current paths.

Creepage/clearance pitfalls (board-level reality)

• Primary ↔ Secondary: keep creepage/clearance consistent across the full barrier (including around transformer pins and opto/isolation parts).
• Slots/windows: slots can extend creepage distance, but verify that coating/potting does not unintentionally bridge the gap.
• Hardware edges: screw holes, heatsinks, sharp copper edges, and cutouts are common “unexpected cross points”.
• Humidity/contamination: spacing that looks fine in dry lab conditions can drift under humidity/pollution; treat this as a reliability risk factor.

Evidence fields (documented test conditions)

• Leakage current: record VAC, frequency, PE condition, operating state (on/standby), and ambient temperature/humidity.
• Hi-pot / withstand: record applied voltage, duration, and pass/fail criteria; repeat after thermal stress if required.
• Insulation resistance (IR): record test voltage and environment; watch drift under humidity.

A protection system must be explainable (why the thresholds and policies won’t cause nuisance trips) and verifiable (every trip can be reconstructed from waveforms + counters). The fastest path to that is to design protection as a fault state machine with explicit qualification (blanking, hit counters, windows) and explicit recovery rules (derate / hiccup / latch).

Protection strategy matrix (design knobs)

Key rule: qualification logic (blanking/hit counters) must be documented and logged, otherwise nuisance trips cannot be debugged.

Common nuisance-trip sources (and how to suppress them)

• Open-load false detect: output capacitance recharge, connector bounce, or load-step recovery can momentarily lift Vout. Use blanking after mode transitions and a hit counter window.
• Short false detect: current spikes at start-up or after load reconnection can look like SCP. Gate fast protection with a soft-start window and classify SCP by “I high + Vout collapsed”.
• OTP chatter: sensor placement/lag causes repeated entry/exit near threshold. Use derating (T1) + shutdown (T2) and keep a clear hysteresis band.
• Hiccup “breathing light”: retry period too short is visually obvious; too frequent retries add surge/thermal stress. Use backoff (increasing wait) and cap retry count before latch.

Evidence fields (waveforms + timing + counters)

• Trip snapshot: Vout, Iout, temperature, and DC-bus (Vbus) captured at “Detect” and at “Protect entry”.
• Qualification: blanking time, hit counter (N), and window length (M) used for this trip.
• Recovery timing: protect duration, retry period, backoff step, and number of retries before latch.
• Chatter metric: trips per minute and protect-entry/exit counts (detect instability).

Lifetime becomes engineerable when it is treated as a measurable stress stack: temperature + ripple current + surge stress + humidity/contamination. Each driver maps to a failure mode (cap dry-out, drifted thresholds, insulation margin loss), and each has a field-verifiable indicator.

Electrolytic aging (temperature + ripple current + derating)

• What accelerates aging: core temperature rise driven by ripple-current heating (ESR) and ambient enclosure temperature.
• Why “case temp” is not enough: the core can run hotter than the case; use hotspot correlation (thermocouple + operating point) for confidence.
• Derating is multi-axis: voltage derating, ripple-current derating, and ambient temperature derating must all be respected together (one axis alone is not protection).
• Failure signature: bus ripple increases over time, PF/THD stability degrades, and restart/hold-up behavior can drift.

Thermal reliability (heat path + sensor placement)

• Heat path chain: junction → case → PCB copper → enclosure/air → ambient. A single bottleneck dominates lifetime.
• Hotspot owners: PFC switch/diode, bridge, power resistors, and bus capacitor region (avoid heat-soaking capacitors).
• NTC strategy: place NTC near the earliest-to-overheat bottleneck, and account for sensor lag in OTP thresholds (avoid OTP chatter).
• Derate policy: prefer controlled current derating before hard shutdown to reduce thermal cycling and user-visible flicker.

Surge stress (system-level protector choices)

• MOV: strong energy handling but parameter drift with repeated surges; long-term aging must be considered.
• TVS: fast clamp with limited energy; effective for sharp events but must be sized for the surge profile.
• GDT: high energy capability; system coordination matters (trigger behavior, follow-on current handling).
• Post-surge validation: check start-up behavior, PF/THD stability, protection threshold drift, and insulation/leakage trends.

Evidence fields (lifetime-focused)

• Thermal: case temperature, hotspot rise above ambient, time-to-thermal-steady-state.
• Bus capacitor stress: Vbus ripple waveform and an estimated/recorded ripple-current indicator at rated load.
• Surge aftermath: before/after drift of Vbus ripple, restart stability, and protection trip thresholds.
• Humidity sensitivity: leakage/IR drift trends under moisture/contamination exposure.

Telemetry should answer one question: “What happened, under what conditions, and is it getting worse?” A minimal but high-value telemetry set combines low-rate runtime trends with event snapshots. This enables field triage without scope creep into protocol or security-root topics.

Log taxonomy (3 buckets)

• Runtime (trend): periodic sampling to show operating envelope and derating behavior.
• Events (snapshot): trigger-based capture around anomalies (surge, OTP entry, brownout, unexpected reset).
• Production/config (traceability): calibration point ID, threshold revision, configuration CRC, write-lock flag (field names only).

Minimum log field table (Field / unit / sampling / trigger)

Storage guidance: use a ring buffer for runtime trend records and event-priority slots so key events are not overwritten.

Field triage: the 5 most useful items

• vac_bucket (input condition classification)
• vbus_minmax_evt (margin around the event)
• iout + mode (CV/CC/derate context)
• temp_hotspot + derate_level (thermal root cause)
• fault_code + fault_cnt (frequency and drift)

The fastest validation path avoids rework by using gates: stabilize start-up first, verify PF/THD and bus ripple at full load, confirm dynamic behavior (mode transitions), then run conducted-EMI pre-check (LISN), and finally do safety pre-checks (leakage/hi-pot/IR). Each gate must specify operating point, test points (TP), required records, and pass criteria.

Minimal toolchain (pre-check oriented)

• Oscilloscope (with suitable probes) for Vbus/Vout/I sense timing and dv/dt observation.
• Power meter for PF/THD under defined VAC and load points.
• LISN for conducted EMI pre-check and DM/CM dominance identification.
• Leakage / hi-pot / IR instruments for safety pre-check (record conditions, not only pass/fail).
• Temperature measurement (thermocouple/IR) for hotspots and derating confirmation.

Gate checklist with required records

Pass criteria are project-specific; the page must record conditions and waveforms so results are reproducible and comparable across builds.

This playbook compresses common field failures into repeatable actions. Each symptom uses the same four-step pattern: 2 measurements (preferred test points), isolation logic (what the readings imply), and a first fix (the fastest change that usually restores stability).

Default measurement order: TP2 (DC bus) → TP4 (output V/I) → TP5 (temperature) → logs. This prevents chasing EMI/loop issues when the real root cause is bus collapse, inrush, or thermal derating.

Preferred field test points (same names as earlier chapters)

• TP1: AC after EMI filter (for line events & conducted noise context)
• TP2: DC bus (PFC output / bulk capacitor node)
• TP4: Secondary output (Vout/Iout, CV/CC behavior)
• TP5: Temperature sense (NTC region / hottest bottleneck correlation)

1) Cold-start fail / “breathing” brightness at low temperature

Typical pattern: start attempts repeat, output ramps then drops, or visible cyclic dimming. Common roots are bulk-cap ESR at low temp, inrush limiter behavior, and protection qualification (blanking/hit counters).

2) PF drops / THD spikes at full load

Typical pattern: input current loses sinus alignment, harmonic content increases, or PF collapses only near maximum power. Common roots are PFC saturation/thermal stress, bus ripple interaction, or current-sense distortion.

3) Breaker trips on plug-in / inrush too high

Typical pattern: immediate trip at plug-in, or repeated trips only at certain line impedance / breaker types. Root causes are usually bulk-cap charging surge, NTC/relay timing, or MOV leakage/aging.

4) Conducted EMI fails at a specific band (single-peak problem)

Typical pattern: one dominant peak fails margin while the rest looks acceptable. Root causes often map to DM resonance, CM return path, or switch-node dv/dt coupling.

5) Brightness drops only when hot / intermittent reboot after warm-up

Typical pattern: output current derates after minutes, or the PSU restarts after reaching a thermal plateau. Most often this is OTP derating, thermal bottleneck, or bulk-cap ripple heating.

6) Sporadic latch / slow recovery (rare but painful)

Typical pattern: the PSU rarely latches off, and recovery requires long cooldown or repeated AC cycling. Root causes are often threshold drift, fault misclassification, or recovery backoff tuned for safety but too conservative.

Minimal field kit (tools, not BOM)

• Oscilloscope: Keysight DSOX3054T (example)
• Current probe: Tektronix TCPA300 + TCP312A (example)
• PF/THD analyzer: Yokogawa WT310E (example)
• LISN (pre-check): TDK-Lambda / Schaffner class LISN (example)
• Thermal: FLIR E8-XT (example)

Note: tool models are examples; the key requirement is repeatable capture of TP2/TP4/TP5 waveforms and consistent PF/THD/EMI pre-check conditions.