EMC & Compliance Subsystem for Lighting & LED Drivers
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The EMC & Compliance Subsystem turns “mystery EMI / random resets / bus errors” into an engineerable, testable chain: control noise return paths, harden the isolation and interfaces, and prove fixes with repeatable evidence (LISN spectra, near-field hotspots, and reset/error logs). When tradeoffs conflict (Y-cap vs leakage, CM choke vs resonance, TVS vs ground lift), the right answer is the one that closes the current loop locally and survives dimming and real-world transients.
Purpose & scope: what this subsystem “buys you”
“EMC & compliance” becomes an engineerable subsystem when its outcomes, modules, and evidence artifacts are defined up front. The goal is predictable behavior under noise, surge, and isolation boundary stress—not guesswork.
Two-sentence overview (for readers)
The EMC & Compliance Subsystem is a modular set of filters, protection, isolation, and monitoring blocks that contain switching noise, survive electrical stress, and make leakage/ground faults observable. It is designed to reduce EMI failures, random resets, bus miscommunication, and false trips—using measurable evidence.
What it includes (subsystem blocks)
| Block | What it controls | Evidence artifacts |
|---|---|---|
| EMI filter front-end CM / DM paths |
Conducted noise energy and return paths (dominant CM vs DM) | LISN spectra delta, CM/DM hypothesis, near-field hotspot map |
| TVS / clamp network surge routing |
Surge/ESD current routing so it does not lift control ground or upset PHY | Reset reason logs, ground bounce waveforms, post-stress fault counters |
| Isolation barrier signal + power |
Safety boundary stability (CMTI margin, common-mode containment) | PHY error counters, isolator edge integrity, boundary coupling signature |
| Leakage / ground monitor decision chain |
Detect and classify leakage/ground faults without false trips from switching noise | Monitor output trend, threshold crossing histogram, trip cause code |
| Event logging evidence chain |
Make “intermittent” issues measurable and repeatable (stress → symptom → cause) | Surge event count, brownout count, bus error count, timestamped state |
Failure patterns this page targets (symptom → likely class → first evidence)
- Deep-dimming flicker / instability → envelope modulation / mode hopping → LED current ripple + spectrum “skirts”
- EMI over limit → CM-dominant vs DM-dominant → LISN band lift + near-field hotspot location
- Bus mis-communication → CM-to-DM conversion / ground reference drift → PHY error counters + edge distortion
- Resets after surge/ESD → clamp current through wrong return path → reset reason register + ground bounce waveform
- Leakage trips after adding Y-cap → leakage increase + monitor chain sensitivity → monitor output jitter + trip histogram
Figure F1. Compliance subsystem map that decomposes “EMC & compliance” into engineerable blocks and measurable evidence artifacts.
EMI in lighting drivers: the real noise sources (and why dimming makes it worse)
EMI failures become solvable when noise is classified by source (dv/dt vs di/dt), path (DM vs CM), and evidence fingerprints (waveforms + spectra + system logs). Dimming commonly spreads noise energy and destabilizes operating modes.
Noise sources: dv/dt nodes vs di/dt loops
| Class | Typical locations | What changes the outcome |
|---|---|---|
| dv/dt nodes fast voltage edges |
SW node / MOSFET drain rectifier reverse recovery synchronous-rectifier commutation |
edge-rate control & damping clamp placement and return path isolation CMTI margin and barrier coupling |
| di/dt loops fast current edges |
input capacitor hot loop switching loop (FET–L–C) output/LED current loop |
loop area minimization (partitioning) DM filtering + resonance damping controlled return paths (avoid control-ground lift) |
Why dimming often worsens EMI (three practical mechanisms)
- Envelope modulation (spectral “skirts”): PWM/analog dimming can modulate the switching noise envelope, creating sidebands that broaden conducted spectra beyond a narrow peak.
- Mode hopping at low power: deep dimming may trigger burst/skip or intermittent regulation cycles, turning steady noise into pulse trains that are harder to filter and more likely to excite resonances.
- Loop restart interactions: extremely short on-time or repeated restart can inject low-frequency components into current regulation, coupling to flicker, audible artifacts, and sometimes false fault detection.
Evidence fingerprints (turn “suspected EMI” into proof)
| What to capture | What it tells | How it routes the fix |
|---|---|---|
| Scope waveforms SW node, VIN ripple, GND bounce, LED current |
dv/dt spikes, di/dt hot-loop signature, ground reference lift during stress | Choose: edge damping vs loop containment vs return-path correction |
| LISN / spectra band lift + sidebands |
DM-dominant vs CM-dominant bands; skirt broadening under dimming | Choose: DM LC damping vs CM choke/Y-path strategy and boundary coupling control |
| System counters / logs reset reason, PHY error count, fault flags |
Whether noise becomes functional failure (reset, mis-comm, false trip) | Prioritize: clamp routing, isolation robustness, monitor-chain immunity |
Fast triage mapping (symptom → likely path)
- Conducted limit fails mainly at lower bands → DM energy + resonance risk (start with DM LC damping)
- Unstable bus / random mis-comm during switching → CM coupling across barrier (review CM path + isolation CMTI)
- Only deep dimming fails → envelope + mode hopping + restart interaction (inspect PWM envelope and pulse-train spectra)
- Resets after ESD/surge → ground lift / clamp return path issue (correlate reset reason with clamp current route)
Figure F2. A practical map of dv/dt nodes and di/dt hot loops, plus the “return path” concept that often decides whether EMI becomes functional failure.
TVS / surge / ESD: placement, return path, and “why it still resets”
A clamp that holds voltage is not the same as a system that survives stress. The deciding factor is where surge/ESD current returns and whether it lifts sensitive references (MCU ground, PHY ground, sense ground).
Core rule (extractable)
TVS works as a system only when the clamp loop is short, stays inside the power-entry zone, and prevents clamp current from crossing control ground or signal reference planes.
Common failure signatures (symptom → path → first proof)
| Failure signature | What typically happens (path-level) | First evidence to capture |
|---|---|---|
| Voltage clamps, but MCU brownouts | Surge current returns through a shared ground segment near MCU/LDO, lifting the logic reference even if VIN is clamped. | Reset reason / BOR flag + ground-bounce waveform (MCU GND vs power-entry GND) |
| DALI/DMX mis-comm or lock-up | Port injection bypasses a diversion path; current/energy enters PHY front-end, causing false edges, latch-up, or burst errors. | PHY error counters / CRC loss + scope edges at receiver pins during stress |
| TVS + input filter resonance makes EMI worse | TVS dynamic impedance/junction capacitance interacts with input LC, creating a new peak or widening a band. | LISN spectrum delta (before/after TVS) + band-specific peak “growth” |
Evidence chain template (keep fixes measurable)
- Waveforms: clamp node vs entry ground, MCU VDD vs MCU GND, and port-line common-mode during stress.
- Logs: reset reason / brownout counters, port error counters, and “stress event” timestamps if available.
- Spectra: LISN band lift and “skirts” changes after protection/layout changes.
Fix directions (principle-level, no certification steps)
- Re-route surge current: keep clamp current inside the power-entry zone; avoid shared impedance with logic ground.
- Template the port front-end: protect → filter → isolate/PHY, with a dedicated return path to prevent CM-to-DM conversion.
- Control resonances: treat protection+filter as a coupled network; add damping or re-balance the filter placement/partition.
Figure F5. A path-focused view of why “TVS installed” can still lead to resets or bus failures: surge current must be routed locally, not through control ground or PHY references.
Digital isolation: selecting isolation topology for lighting buses & telemetry
Isolation is not only about safety spacing; it is about preserving signal meaning under common-mode stress. Choose topology and specs using CMTI, edge integrity, and fail-safe behavior—then verify with evidence.
Isolation goals (engineering view)
- Safety boundary: keep hazardous and SELV/control domains separated with predictable behavior.
- Break ground loops: prevent shared-impedance coupling from power stage into buses and sensing.
- Improve immunity: reject dv/dt-driven common-mode transients without false switching.
Topology options (concept level)
| Type | Why it is used in lighting buses | Main engineering constraints |
|---|---|---|
| Capacitive | High-speed data isolation with strong common-mode transient performance (when CMTI is sufficient) | CMTI margin vs dv/dt severity, edge distortion under stress |
| Magnetic | Robust digital isolation with good timing stability across temperature | Propagation delay/skew budget for bus timing and PWM integrity |
| Optical | Classic isolation option with clear boundary behavior in many systems | Aging/CTR drift impacts margins; bandwidth and power may constrain |
Key specs in engineering language (what they actually protect)
- CMTI: how much dv/dt the barrier tolerates without treating common-mode movement as data (prevents false edges).
- Propagation delay / distortion: whether PWM and RS-485-like signaling preserves shape and timing (prevents duty skew and bit errors).
- Fail-safe & power-up state: whether outputs default predictably during reset/brownout (prevents unintended light pulses or phantom frames).
Evidence fingerprints (prove isolation is robust)
- Bus integrity: error counters, CRC loss, retries, and response timeouts during switching and stress.
- Edge integrity: receiver pin waveforms, eye opening, and glitch events correlated with dv/dt edges.
- Startup behavior: power-up capture of outputs (no unintended toggles), plus state logs at boot.
Figure F6. Isolation must be specified and verified against dv/dt-driven common-mode stress. The barrier blocks direct ground sharing, but a common-mode loop can still exist via parasitics—so CMTI, edge integrity, and fail-safe behavior matter.
Creepage & clearance: turning safety spacing into layout constraints
Treat spacing as a boundary-first layout constraint: draw the isolation fence, lock keepout zones, and prevent late copper/vias/rework from creating a new shortest path.
Constraint inputs (concepts only)
- Working voltage + transients: defines the stress the boundary must tolerate.
- Environment / pollution tendency: affects how risky surface paths become over time.
- CTI (material tracking index): indicates surface tracking robustness; lower CTI demands more conservative surface design.
Boundary-first method
- Step 1 — place the fence: define the isolation barrier line and the two domains (hazard/noisy vs SELV/control).
- Step 2 — lock keepout: ban copper, vias, and test pads from crossing or approaching the fence beyond a defined margin.
- Step 3 — place cross-boundary parts: isolators, transformers, opto parts, Y-cap networks must sit at the fence with controlled geometry.
Geometry rules (principle-level)
- Copper & pours: any nearby copper can create a new “shortest path” across the barrier—especially on inner layers.
- Vias: via pads, barrels, and stitching can unintentionally bridge the surface or create a closer air path.
- Slots/cutouts: slots can force longer surface paths, but must be placed so they do not concentrate contamination or weaken the structure.
Late-stage rework risks (common layout regressions)
- “Just add copper” fixes: patch pours, shields, or jumpers can violate keepout without being noticed in schematic reviews.
- Coating/conformal changes: partial coverage or rework residues can alter surface behavior and tracking risk.
- Test-point additions: emergency test pads or probe rings near the fence can become the closest path.
Figure F7. Turn safety spacing into enforceable layout constraints: fence line, keepout zones, slot placement, and “no-copper/no-via” rules around critical cross-boundary pin pairs.
Leakage current & ground fault monitoring: architectures that survive real noise
A leakage monitor is only useful if it remains stable under switching noise. Build a full chain (sense → filter → decision window → debounce → action) and log evidence so false trips can be proven and fixed.
Leakage sources (real-world)
- Intentional: Y-cap return currents and coupling across the isolation barrier.
- Parasitic: transformer/inter-winding capacitance, heatsink/fixture capacitance, wiring harness coupling.
- Environmental: humidity, contamination films, residues that change surface conduction.
- Aging: insulation degradation, cracks, potting defects that evolve over time.
Monitoring chain (functional blocks)
- Sensing: current transformer / shunt / capacitive coupling (choose based on where leakage returns).
- Filtering: reject switching-edge energy; keep the slower leakage trend observable.
- Decision: threshold + time window to avoid spikes; encode “cause codes” for logs.
- Action: derate → alarm/log → shutdown (layered response instead of immediate hard-off).
EMC critical points (avoid false triggers)
- Reference integrity: sense ground must not ride on the switching return or surge clamp currents.
- dv/dt immunity: do not allow common-mode edge energy to look like leakage magnitude.
- Threshold stability: manage offset/temperature drift and define decision windows (debounce).
Evidence fields to log (make “intermittent” measurable)
- Monitor outputs: raw sample / filtered value / peak or RMS proxy (whichever the chain uses).
- Decision metadata: threshold crossed, duration in window, repeat count, and debounce state.
- Correlation tags: dimming mode/state, switching state, and recent surge/ESD event flags if available.
Figure F8. A noise-robust leakage monitoring chain: sensing, filtering, windowed decision, debounce, and layered actions with evidence logging to distinguish real faults from switching-noise artifacts.
“Y-cap vs EMI” tradeoff: when compliance fights each other
Y-cap can reduce common-mode EMI by providing a high-frequency return path, but it can also increase leakage, reshape common-mode loops, and stress isolation/monitor chains. The first variable is the return path, not capacitance value.
What Y-cap can improve (why it exists)
- Lower CM EMI: provides a controlled HF return for common-mode energy instead of letting it ride on cables.
- Stabilize spectra: can reduce peak CM voltage by shortening the effective loop at high frequency.
What it can break (three common side-effects)
- Higher leakage / GFD sensitivity: baseline leakage rises and can push monitoring chains closer to trip thresholds.
- New CM loop geometry: in some structures it creates a larger “antenna-like” loop that worsens radiated behavior.
- Isolation stress changes: the barrier sees different common-mode waveforms; marginal CMTI can turn into data errors.
Resolution framework (path-first co-design)
- Start with a loop map: draw where common-mode current returns with and without Y-cap.
- Co-design with isolation: ensure the chosen return path does not push isolators beyond CMTI edge-case behavior.
- Co-design with monitors: verify the leakage/ground-fault chain stays stable under the new CM waveform.
Figure F9. Y-cap decisions must be made from a return-path map: a controlled short CM loop can reduce EMI without destabilizing leakage monitoring, while an enlarged loop can increase leakage and radiated risk.
Bus EMC: DALI / DMX / RS-485 physical-layer hardening (subsystem view)
Keep this chapter physical-layer only: how common-mode disturbance becomes differential errors via imbalance, reference shift, or isolation/transceiver distortion—and how to harden the port front-end without touching protocol details.
How common-mode turns into data errors (three conversion paths)
- Imbalance → CM-to-DM conversion: asymmetry in wiring, component parasitics, or layout turns common-mode energy into differential noise that rides on A/B.
- Reference shift → moving thresholds: ground bounce or clamp-return currents lift local reference; receivers interpret edges against a drifting baseline.
- Distortion → edge/window damage: isolation or filtering can stretch, round, or create false edges under dv/dt, shrinking the sampling margin.
Key building blocks (roles + placement principles)
- TVS / ESD clamp: the goal is to keep surge/ESD current inside the port zone; clamp-return must not traverse control ground.
- Common-mode choke: blocks HF common-mode current on the cable; place close to the connector and avoid excessive differential distortion.
- Bias + termination: stabilize the idle state and reference; keep bias/termination tied to the intended local reference domain.
- Isolation + transceiver: breaks ground loops and improves noise tolerance; ensure the isolation barrier and isolated supply keep dv/dt from causing false transitions.
Field signatures that point to PHY hardening issues
- Random flicker / brief glitches: often tracks reference shift or false edges during switching or surge events.
- Address or state “lost” intermittently: commonly linked to brownout/reset induced by clamp-return lifting local ground.
- Occasional no-response (e.g., diagnostics timeouts): frequently caused by edge distortion or isolation delay/shape changes under noise.
Minimal debug checklist (evidence-first)
- Waveforms to capture: A/B differential + local reference (receiver ground) during the failure moment.
- Correlate: dimming state / power-stage switching state / recent surge events to error bursts.
- Log fields: error counters, reset reason, “trip cause code,” and a timestamped event flag near the port.
Figure F10. Subsystem template for hardened bus PHY: port protection, common-mode filtering, isolation barrier, transceiver, and MCU logging. The main design variable is the return path: keep clamp currents local to the port zone.
Pre-compliance & evidence chain: debug with measurable artifacts
This is a repeatable debug path—not a certification tutorial. The goal is to turn every mitigation into a measurable delta: spectrum screenshots, near-field hotspot maps, and immunity-after artifacts (reset reason, fault logs, error counters).
Evidence chain mindset (what “good” looks like)
- Same test conditions every time: input source, load, cable routing, dimming mode/level, and enclosure state must be repeatable.
- One hypothesis per iteration: change only one variable (placement, return path, filter corner, clamp routing) per run.
- Artifacts are versioned: each run stores “before/after” screenshots + logs with a timestamp and build tag.
Step 1 — Measure: make noise repeatable (conducted + near-field)
- Conducted (LISN + spectrum): capture a baseline trace under fixed dimming states (e.g., 100% / deep-dim / burst/skip). Save screenshots with the same RBW/VBW and detector settings.
- Near-field scan: translate “a peak exists” into “the peak has a physical source.” Map hotspots over the switching loop, isolation barrier, and cable exit region.
- Tag the run: operating mode, input, load power, cable layout photo, and firmware/build ID.
Step 2 — Classify: decide whether the peak is DM or CM (avoid wrong fixes)
- DM suspicion: peaks track input current pulses / power-stage operating point; mitigation tends to live in the differential current loop and input network stability.
- CM suspicion: peaks track dv/dt node activity, barrier coupling, or cable routing; mitigation tends to be return-path control, CM impedance, and barrier/cable management.
- Write the label on the screenshot: “DM-likely” or “CM-likely” + one sentence explaining why (pattern + path hypothesis).
Step 3 — Localize: hotspot dictionary (what the scan usually means)
- Hot loop hotspot: bright area around the switching loop / input cap loop → loop area or return path is radiating.
- Barrier hotspot: strong field around isolation boundary/transformer/isolators → parasitic capacitance coupling is injecting CM energy.
- Cable/connector hotspot: bright cable exit/port region → common-mode current is escaping and turning the harness into an antenna.
Step 4 — Mitigate: bind the fix to the classified root cause
- DM fixes (principle-level): shrink differential current loops, avoid filter resonance, and keep the input network stable across dimming states.
- CM fixes (principle-level): control return paths, add CM impedance at the correct boundary, and prevent barrier/cable from becoming the dominant CM loop.
- Robustness fixes (immunity artifacts): route clamp currents to stay inside the port zone; keep control reference stable; ensure isolators/transceivers don’t create false edges under dv/dt.
Step 5 — Re-test: quantify the delta (your content’s “verifiable” advantage)
- Spectrum delta: same markers, same settings; record peak reduction and whether new peaks appeared (avoid “fix one, create another”).
- Hotspot delta: hotspot intensity/area should shrink or move to a less sensitive region; record a “before/after” photo pair.
- Immunity-after delta: resets go to zero and error counters stop climbing; log reset reason and fault codes with timestamps.
Recommended artifact pack per iteration: 2× spectrum screenshots (before/after) + 2× near-field photos (before/after) + one log snippet showing reset reason / counters.
Example BOM (specific MPNs) for repeatable pre-compliance debug
| Bucket | MPN examples | Why it helps in the evidence chain |
|---|---|---|
| Conducted setup |
TekBox TBLC08 (50 µH LISN) Tektronix EMI-LISN50UH (re-badged TBLC08) |
Makes conducted noise repeatable and comparable run-to-run; baseline evidence for “before/after delta”. |
| Spectrum capture | SIGLENT SSA3032X (SSA3000X series) | Captures peaks/sidebands and tracks changes across dimming modes; screenshots become artifacts with the same RBW/VBW settings. |
| Near-field localization | Langer EMV RF2 set (near-field probes) | Turns “a frequency peak exists” into “this physical area radiates it” (hot loop vs barrier vs cable exit). |
| Port hardening parts (tie-in to H2-10) |
Littelfuse SM712-02HTG (RS-485 TVS array) Würth 744232090 (WE-CNSW CM choke) TI SN65HVD3082E (RS-485 transceiver) |
Lets the debug loop validate: “port-zone clamp return + CM impedance + controlled edges” reduces errors and prevents noise escape into the cable. |
| Isolation robustness |
TI ISO7741 (quad digital isolator) ADI ADM2587E (isolated RS-485 with iso power) |
Supports “immunity-after” evidence: reduced false edges under dv/dt and fewer error bursts; easier correlation to reset reason and counters. |
Notes: MPNs above are examples used to anchor the evidence chain to concrete hardware. Selection still depends on bus speed, isolation needs, and layout constraints.
Figure F11. Repeatable evidence-chain workflow for pre-compliance debug: measure, classify (CM/DM), localize, mitigate (one change), and re-test with versioned artifacts and immunity-after logs.
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FAQs (evidence-based, no scope creep)
Each answer is short, measurable, and maps back to the subsystem evidence chain (H2-2…H2-11). Example MPNs are included as practical anchors (selection still depends on voltage, speed, layout, and test results).
Q1
Conducted peak rises in 150 kHz–1 MHz—DM or CM first?
Mapped: H2-4 / H2-11
Answer: Classify before changing parts. Start with a LISN trace and correlate peaks with operating state: if peaks track input current pulsation, suspect DM; if they track dv/dt events and cable routing, suspect CM. Confirm with a quick near-field scan (input network vs cable exit). Capture “before/after” screenshots with identical settings.
Q2
CM choke made EMI worse—resonance or saturation?
Mapped: H2-4 / H2-11
Answer: A narrow, sharp new peak often indicates resonance with nearby capacitors/ESR, while “worse at higher current” can indicate choke saturation reducing CM impedance. Verify by repeating the same LISN sweep at two load points and checking whether the peak frequency stays fixed (resonance) or scales with load stress (saturation). Apply one change: add damping or swap choke.
Q3
TVS installed but MCU still resets—did surge current take the wrong ground path?
Mapped: H2-5 / H2-3
Answer: If the TVS clamps voltage but reset persists, suspect ground reference lift: clamp current may be returning through control ground, triggering BOR/UVLO. Confirm by logging reset reason and probing local MCU ground shift during the event. The first fix is zoning: keep the TVS return loop inside the port/power entry zone and away from logic reference.
Q4
Deep dimming worsens EMI—PWM envelope or loop burst/skip?
Mapped: H2-2 / H2-7
Answer: Look for low-frequency modulation: sidebands and “breathing” in the spectrum often point to burst/skip or periodic loop restart, not just PWM itself. Confirm by capturing a time-domain current waveform and matching envelope frequency to the spectral sidebands. First fix: stabilize the operating mode at deep dim (avoid restart cycles) before adding more filtering.
Q5
Bus still errors after isolation—insufficient CMTI or return-path coupling?
Mapped: H2-6 / H2-10
Answer: If error bursts align with dv/dt switching edges, suspect CMTI stress or barrier coupling. If errors correlate with surge/ground bounce events, suspect return-path coupling across zones. Verify using an error counter timestamp plus a dv/dt node probe/near-field scan at the barrier. First fix: either raise isolator robustness or redesign the cross-barrier return path so CM energy stays local.
Q6
Y-cap fixes EMI but triggers leakage alarm—how to balance?
Mapped: H2-8 / H2-9
Answer: Treat return path as the first variable, not just capacitance. A larger Y-cap can reduce CM voltage but also increases leakage and may create a new CM loop that excites radiation or false trips. Verify by measuring leakage monitor input ripple and correlating trips with switching state. First fix: move/partition the return so CM current closes in a controlled path, then adjust value.
Q7
Leakage monitor false-trips—did switching noise contaminate the sensing chain?
Mapped: H2-8
Answer: If trips align with switching edges or dimming transitions, the sensing chain is likely seeing injected CM noise as “leakage.” Confirm by probing the sense node and the post-filter node (before the decision stage) and checking whether the decision threshold is crossed by spikes rather than true leakage. First fix: improve filtering/debounce and enforce sensing-zone layout separation from dv/dt nodes.
Q8
Near-field hotspot at isolation barrier—shielding first or zoning first?
Mapped: H2-3 / H2-6
Answer: Zoning and return-path control come first; shielding without a defined return can create a larger antenna. Confirm barrier coupling by scanning both sides of the barrier and checking whether hotspots follow cable routing or dv/dt nodes. First fix: enforce a clean barrier boundary (no uncontrolled copper/return crossings), then add targeted shielding tied to the intended reference (functional earth or defined shield node).
Q9
Long DMX cable causes instability—CM→DM conversion or termination mismatch?
Mapped: H2-10
Answer: Termination mismatch shows as ringing/overshoot and reflections in the differential waveform; CM→DM conversion shows as common-mode steps that translate into differential glitches due to imbalance or reference shift. Capture A/B differential and common-mode (A+B)/2 at the receiver during failure. First fix: verify bias/termination in the correct reference domain; then add CM impedance at the connector to keep cable CM current local.
Q10
Failures spike during thunderstorms—how to inspect surge path and protection zoning?
Mapped: H2-5 / H2-3
Answer: Thunderstorm correlation strongly suggests surge energy entering through mains/cable and lifting local references. Confirm by checking reset reasons (BOR/UVLO) and whether error counters jump immediately after events. Inspect whether clamp currents are forced through logic ground or thin traces. First fix: enforce a dedicated high-current return path and keep protection components physically in the port/power-entry zone with short loops.
Q11
Conducted passes but radiated fails—what are the 3 most common structural causes?
Mapped: H2-2 / H2-3 / H2-11
Answer: The common trio is: (1) a hot switching loop with excessive area acting as a radiator, (2) barrier/transformer coupling injecting CM energy into the “quiet” side, and (3) cable/harness CM current turning the lead into an antenna. Localize using a near-field scan and cable-exit probing. First fix: reduce loop area, control barrier return, or add CM impedance at the boundary—one at a time.
Q12
Revision suddenly violates creepage—what changes most often cause surprises?
Mapped: H2-7
Answer: Common “silent killers” include adding copper pours/thermal relief that shorten surface paths, placing vias too close to the barrier, removing/relocating slots, and adding coating or mechanical parts that change effective spacing routes. Verify by marking the barrier line and re-measuring along the actual surface path, not just straight-line clearance. First fix: restore a no-copper keepout and slot strategy before re-optimizing routing.
Figure F12 (optional). Matrix showing how each FAQ maps back to chapters H2-2…H2-11 to prevent scope creep and keep answers evidence-driven.
