H2-1. Scope & System Role in Lighting (What this PSU is / is not)

In lighting systems, an LLC stage is typically the isolated PSU block that converts an upstream high-voltage bus into a usable output bus (CV or CV/CC). Downstream blocks may implement constant-current regulation or per-string management, but those are outside this page’s scope. Here, the focus is the LLC PSU itself: stable regulation, predictable mode transitions, and efficiency choices that can be verified by evidence.

• What this page provides: CV/CC dual-mode stability, SR timing guardrails, and evidence-based diagnosis for startup / hiccup / protections.
• What this page avoids: flyback details, non-isolated LED CC driver deep dives (buck/boost/buck-boost), and dimming protocol tutorials.
• Evidence-first mindset: each claim ties back to measurable fields (VDS, Ires, SR Vds, Vout/Iout ripple, mode/fault flags).

Boundary note: any mention of PFC, EMI, or downstream CC is only to show system placement, not to teach their design.

H2-2. When to Choose LLC for CV/CC Lighting PSU (Decision & trade-offs)

LLC is chosen when constraints favor an isolated stage that can achieve high efficiency and good thermal headroom while staying quiet and stable across the intended load range. The decision is not “LLC is always best”; it is whether the product’s operating envelope can stay inside a practical control window (frequency range, ZVS margin, and acceptable light-load behavior).

H2-3. Reference Architecture (Blocks + signals + where CV/CC lives)

A practical LLC lighting PSU can be read as three layers: power path (how energy flows), sense/feedback (how output conditions are observed), and mode & fault logic (who controls regulation and what happens during limits). This chapter locks the placement of CV/CC arbitration, frequency command generation, and hiccup/burst decisions so later debug steps have a consistent map.

Power path (energy flow)

• Half-Bridge (HB) + gate driver creates a high-frequency drive waveform.
• Resonant tank (Lr/Cr/Lm) shapes current (I_res) and enables soft switching behavior.
• Transformer provides isolation and scaling.
• Secondary SR + output filter converts to DC and reduces ripple.

Sensing & feedback (what the controller “sees”)

• V sense and I sense produce CV-error and CC-error candidates.
• Isolation link (opto / digital isolator) carries a feedback level to the primary controller.
• FB level is the controller-side representation of “how hard to regulate” (e.g., COMP/ADC code/opto current).

CV/CC arbitration (where dual-mode lives)

• CV and CC loops both exist; the PSU selects the active mode state (CV-dominant vs CC-dominant).
• Arbitration must avoid chatter via hysteresis / debounce around the transition boundary.
• The arbitration output becomes a single actuator request: frequency command (fSW cmd) and/or gate enable limits.

Protection & hiccup state machine (how limits are enforced)

• Limits such as OCP/OPP/OVP/OTP/UVLO are evaluated against thresholds.
• Fault response defines behavior: hiccup (restart attempts), burst/skip (light-load control), or latched stop.
• State transitions should be loggable: burst entry/exit and fault flags become first-class evidence.

H2-4. Resonant Control Fundamentals (Gain curve, ZVS window, frequency modulation)

An LLC regulates output primarily by shifting switching frequency (f_SW) relative to the resonant region. The goal is to stay inside a workable window where regulation is strong enough while soft-switching margin remains acceptable. This chapter is intentionally “engineering intuition”: it defines what the frequency region means, how ZVS is proven on waveforms, and why light-load conditions often introduce burst/skip behavior and low-frequency artifacts.

Frequency region: what changes when fSW moves

• Near resonance: control tends to be efficient and predictable (trend-level statement, not a formula).
• Frequency up/down: gain shifts with f_SW movement; the controller uses this to correct Vout/Iout.
• Practical constraint: the design must tolerate a real fSW range across line/load/temperature.

ZVS margin: verify by VDS during deadtime

• ZVS is not “a checkbox”; it is a margin that must survive worst cases.
• Waveform test: during deadtime, VDS should naturally transition toward the next state before the gate turns on.
• Low margin shows up as late/partial transition, higher switching stress, and potentially higher noise.

Light-load & no-load: burst/skip and audible risk

• At light load, continuous fine regulation may be inefficient; controllers enter burst/skip to reduce loss.
• Burst creates packet envelopes that can raise Vout ripple and excite audible/mechanical noise paths.
• Entry/exit thresholds must be stable to avoid “breathing” and mode chatter.

H2-5. CV Regulation Loop (Sampling, compensation, stability evidence)

The CV loop in an LLC lighting PSU must be treated as a measurable system: a defined signal path from output sensing to a single actuator (switching frequency command). Tuning is successful only when it is backed by evidence—overshoot, recovery time, and observable loop signals (EA/FB behavior) that remain stable across line/load and do not trigger unwanted mode toggling.

Signal path (secondary sense → primary frequency command)

• Vout sense (secondary) produces a voltage error relative to the target.
• Error amplifier (EA) shapes the loop response (compensation goal-focused, not math-focused).
• Isolation link (opto / digital isolator) transfers a feedback level to the primary side.
• Primary controller converts FB level into fSW command (the actuator for regulation).

Engineering goals (what “good compensation” looks like)

• Phase margin in practice: no sustained ringing after a disturbance and no “hunting” at light load.
• Transient recovery: fast return to regulation after a load step without excessive overshoot.
• No boundary instability: the loop should not provoke burst entry/exit chatter near light-load limits.

Common symptoms mapped to evidence

• Load-step overshoot: Vout spikes high after load release → measure Vout overshoot and recovery time.
• Light-load hunting: Vout slowly oscillates while mode stays “CV” → inspect EA/FB waveform for low-frequency swing.
• Burst-boundary oscillation: visible “breathing” or repeated transitions → track mode toggling frequency and burst entry/exit behavior.

Fast discriminator: loop issue vs state-machine interference

• If mode toggling frequency matches the Vout envelope, boundary logic (burst/CC/limits) is likely involved.
• If mode state is steady but Vout rings, loop dynamics (sense noise / EA behavior / actuator response) are more likely.

H2-6. CC Mode Implementation (Current sense + CV/CC arbitration)

CC mode in an LLC CV/CC PSU is implemented by sensing output current and letting a CC loop compete with the CV loop for the same actuator. The system is stable only if arbitration is explicit: a selector decides which loop is in control, while hysteresis and timing filters prevent boundary chatter caused by ripple, noise, and transient events.

Mainline implementation used here (secondary current sensing)

• I sense element (shunt / CT / sampled sense node) measures output current on the secondary side.
• A CC EA (or CC regulator block) generates a CC control request.
• CV and CC requests share the same control channel: fSW cmd and, at limits, burst / OPP behaviors.

Arbitration: selector + hysteresis + timer

• Selector logic: CV EA and CC EA compete; the “tighter” request takes control of the actuator.
• Hysteresis: separate enter/exit thresholds so ripple does not force repeated switching at the boundary.
• Timing filter: require the condition to persist for N ms / N cycles before switching modes.

Lighting scenarios that commonly trigger CC behavior

• Overload / short-circuit: current clamp engages and may escalate into hiccup depending on thresholds.
• Abnormal LED string behavior: effective load changes can push the PSU into CC/OPP limits.
• Startup limiting: soft-start and unknown load conditions can require temporary current limiting.

What “good” looks like (evidence-backed)

• Iout clamp level is repeatable and not excessively temperature-sensitive.
• Mode hysteresis is large enough that the boundary does not chatter.
• CV/CC boundary chatter stays low; repeated toggling should not create visible “breathing”.
• Fault counters meaningfully differentiate a real overload from a noisy threshold.

H2-7. Soft-Start, Start/Stop, and Light-Load Behavior (no pop, no hiccup surprise)

Lighting systems are sensitive to startup artifacts and low-load envelopes: a brief flash, a “breathing” envelope, audible noise, or a surprise hiccup cycle can be more noticeable than steady-state efficiency loss. This section treats startup and light-load as a reproducible timeline with measurable markers—ramp shape, resonant current peak, burst envelope frequency, and restart timing.

Soft-start goals (what must be controlled)

• Limit Ires peak: reduce startup stress and avoid unintended OCP/OPP engagement.
• Prevent Vout overshoot: avoid “pop/flash” and overshoot-driven mode transitions.
• Avoid SR mis-conduction: keep SR gated off until secondary conditions are valid.

Start/stop strategy (brownout, UVLO, and “no surprise” restart)

• Entry to stop: brownout/UVLO should force a clear stop state (gates disabled, mode state updated).
• Output discharge path: controlled discharge avoids ambiguous “half-charged” restarts and inconsistent flash behavior.
• Restart condition: restart should be governed by a defined restart timer and input recovery, not noise.

Light-load behavior (burst/skip and low-frequency envelope risk)

• Burst/skip entry/exit: thresholds and timers decide when to packetize switching.
• Envelope impact: burst packets create a low-frequency envelope that can appear as Vout ripple, visible breathing, or audible excitation.
• Chatter avoidance: repeated entry/exit creates a “surprise” feel—tune for stable boundaries and consistent restart behavior.

H2-8. Synchronous Rectification (SR) for Lighting: timing, reverse current, reliability

SR is a major efficiency lever in LLC lighting PSUs, but it is also a common failure amplifier: incorrect timing can extend body-diode conduction, create reverse current (backfeed), and let ringing trigger false turn-on at light load. This section frames SR as a waveform- verifiable subsystem using Vds_sr, secondary current behavior, blanking windows, and temperature evidence.

Where SR efficiency comes from (high-level)

• Lower conduction loss: MOSFET conduction replaces part of body-diode conduction during rectification.
• More benefit at higher current: diode loss rises quickly with load, making timing quality more valuable.

Key risks that break SR in lighting

• Reverse current / backfeed: SR stays on (or turns on) when secondary current reverses during light-load or transitions.
• Excess body-diode time: deadtime/latency issues keep the diode conducting longer than intended, raising heat.
• Ringing false trigger: secondary ringing and noise can mimic a turn-on condition without real forward current.

Waveform evidence to confirm SR health

• SR Vds waveform: confirm clean low Vds during intended conduction and clean transitions at turn-off.
• Reverse current evidence: verify behavior around the Isec zero-cross; SR should not promote negative current.
• SR blanking time: a defined “no-turn-on” window helps prevent false triggers during ringing/light-load.
• Temp delta vs diode: compare temperature rise with SR enabled/disabled to infer excessive diode conduction time.

H2-11. Validation & Field Debug Playbook (symptom → evidence → isolate → first fix)

This playbook is designed for field speed: each symptom uses exactly two high-value measurements, a discriminator that separates likely causes, and a first fix that is minimal (tuning knobs and policy changes) before any redesign. The same evidence fields are reused across all symptoms so logs and waveforms stay comparable across builds.