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Digital X-ray Flat Panel Detector (FPD) Readout Front-End

Digital X-ray Flat Panel Detector (FPD) Readout Front-End

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This page explains how a digital X-ray flat panel detector (FPD) reliably converts tiny pixel charge into clean, frame-synchronous digital data. The practical focus is on controlling leakage and drift, keeping noise and fixed patterns low, and meeting clock/trigger timing so images remain stable across temperature and operating modes.

H2-1 · What this page answers

Featured answer

This page explains how a digital X-ray flat panel detector reads tiny pixel charge and turns it into a stable, synchronized image frame. It focuses on leakage control, low-noise analog front ends, and clock/frame timing so the output pixel stream is repeatable, calibratable, and ready for downstream processing.

What readers can take away
  • Leakage: how to spot the dominant leakage paths (panel, switches, AFE inputs, contamination) and which checks become non-negotiable as integration time or temperature rises.
  • Noise: how kTC/1-f/thermal noise and channel mismatch become fixed-pattern artifacts, and why CDS + offset/gain calibration are the fastest route to stable low-dose performance.
  • Sync: which timing signals define frame integrity (exposure trigger, frame/line sync, sampling clock), and what must be verified so every line/column is sampled consistently.
Digital X-ray FPD: three engineering levers for a stable frame Block-style diagram showing Leakage, Noise, and Clock/Sync feeding a Stable Digital Frame outcome, with small sub-blocks for common checks such as bias/leakage paths, CDS/calibration, and frame/line timing. Stable frame = Leakage + Noise + Sync FPD readout focus: repeatable pixel codes with calibratable baselines Stable Digital Frame repeatable • calibratable • synced Leakage control panel dark current switch / input bias symptoms baseline drift • image lag Noise floor kTC + 1/f + thermal channel matching tools CDS • offset/gain cal Clock & Sync trigger • frame/line • sampling Tip: When integration time or temperature increases, leakage-driven drift and lag often dominate before ADC resolution does.

H2-2 · Where the FPD readout sits in the imaging system

In a digital X-ray imaging chain, the FPD readout is the boundary between the detector physics and the rest of the digital pipeline. This page covers the path from pixel integration and row/column scanning through AFE and ADC, and stops at a well-defined digital handoff: a synchronized pixel stream plus the timing and calibration information needed to interpret it correctly.

Downstream handoff (what must be provided)
  • Digital pixel stream: pixel codes organized by line/frame (parallel or multiplexed), with stable baseline behavior under the intended integration window.
  • Timing contract: exposure trigger alignment, frame/line sync relationship, and the sampling clock requirements that keep every channel consistent.
  • Calibration artifacts: offset/black reference, gain/uniformity references, and channel correction data needed to suppress fixed-pattern drift and stripes.
Scope boundary (intentionally out of scope here)
  • Frame grabber / PCIe / SerDes / DMA buffering details
  • Storage/recorder implementation, compression, encryption and key management
  • Full system clock network architecture and system-level EMC/medical isolation design
System position of the digital X-ray FPD readout front end Left-to-right block diagram from X-ray source through scintillator/photoconductor, pixel array, readout ASIC/AFE, ADC and data aggregator, ending at a digital handoff. A side panel lists the three handoff items and an out-of-scope area for downstream frame grabbing and storage/security. FPD readout boundary: detector → synchronized digital data Stops at “digital handoff”; downstream capture/processing is separate X-ray source exposure pulse Converter scint / photo Pixel array integrate charge Readout ASIC / AFE row/col scan • CDS ADC codes Aggregator digital out Timing contract (requirements) exposure trigger frame / line sync sampling clock stability Digital handoff pixel stream timing contract calibration artifacts Out of scope here: frame grabber • storage/recorder • compression/security • full timing network • system EMC/isolation Engineering cue: higher frame rate tightens settling time; longer integration increases leakage-driven drift and lag.

H2-3 · Pixel & panel basics you must know (only what impacts readout)

Panel type matters to the readout front end only when it changes the three engineering levers: leakage behavior (baseline drift and lag), the integration window (how long charge is stored before sampling), and speed constraints (how tight settling and sampling timing must be). The goal here is to map a-Si, a-Se, and CMOS panels into concrete readout priorities—without drifting into detector physics.

a-Si TFT + scintillator (indirect)
  • Leakage / drift: dark current and switch/input leakage show up as slow baseline drift and image lag, especially at higher temperature.
  • Integration window: longer or variable integration windows increase sensitivity to bias current and contamination paths.
  • Readout priority: push leakage down first (guarding, cleanliness, input bias), then optimize ADC resolution.
a-Se (direct conversion)
  • Dynamic range: charge handling and saturation behavior define reset/clear strategy and full-scale limits at the readout node.
  • Leakage sensitivity: baseline stability depends on controlled leakage paths under bias; drift and lag must be corrected with repeatable calibration.
  • Readout priority: define full-scale + reset timing clearly, then enforce channel matching and stable offset/gain references.
CMOS panel (active pixel)
  • Speed constraint: higher parallelism and tighter sampling windows make settling time and timing consistency the first-order risk.
  • Timing/clock impact: sampling jitter and channel phase mismatch can hard-freeze into stripes or fixed-pattern artifacts.
  • Readout priority: lock the timing contract and channel alignment first, then optimize the noise floor.
Practical selection cues (readout-first)
  • When integration time or temperature increases, leakage-driven drift and lag often dominate before ADC bit depth does.
  • When frame rate increases, settling time, switch injection, and clock consistency dominate before incremental noise improvements.
  • When full-scale handling is unclear, define reset/clear timing and saturation behavior before tuning downstream correction.
Panel type mapped to readout priorities: leakage, window, speed Three column block diagram comparing a-Si TFT, a-Se direct conversion, and CMOS panels. Each column highlights the readout-impact differences: leakage/drift, integration window/dynamic range, and speed/timing constraints. Panel basics that change readout design Only readout-impact: leakage • integration window • speed/timing a-Si TFT (indirect) Leakage / drift dark current • bias paths Integration window long/variable windows Readout priority guarding • low bias stable black cal Leak map Drift check a-Se (direct) Dynamic range full-scale • reset Baseline stability bias paths • lag Readout priority clear reset timing match channels FS plan Cal data CMOS panel Speed / timing tight sampling Channel alignment phase • jitter Readout priority lock timing contract align channels Jitter Settle Design cue: longer integration amplifies leakage; higher frame rate amplifies settling and timing errors.

H2-4 · Readout architecture in one chain

A flat panel readout is a repeated sequence that converts stored charge into stable pixel codes. Each step exists to control a specific error class: slow accumulation errors from leakage and bias current, fast transient errors from switching injection and settling, and random noise that defines the low-dose floor. Understanding where each error enters the chain is the fastest way to diagnose drift, stripes, and lag.

One readout cycle (pixel → code)
  1. Reset: clears the integration node; sets the initial baseline that CDS must stabilize.
  2. Integration: stores charge over a defined window; leakage and bias current accumulate as baseline drift or lag.
  3. Row select: connects a row to the column lines; switching injection and ground bounce must settle before sampling.
  4. Column sampling: captures the signal at a precise time; insufficient settling freezes errors into stripes/FPN.
  5. CDS / amplify: suppresses offset and low-frequency noise; improves repeatability and calibration stability.
  6. Mux: trades area for throughput; can amplify crosstalk and transient sensitivity if timing is not controlled.
  7. ADC: converts to codes; channel matching and clock alignment often matter more than nominal bits for image uniformity.
Why “integration + sampling” is so sensitive to leakage and bias current
  • Integration stores charge over time, so any leakage path or input bias current continuously removes or injects charge during the window.
  • Error grows with window length: longer integration and higher temperature make drift and lag visible even when instantaneous noise looks good.
  • Sampling freezes the result: switching transients and incomplete settling at the sampling instant become fixed-pattern artifacts (stripes, column bias).
FPD readout chain: where slow, fast, and random errors enter Left-to-right chain diagram showing reset, integration, row select, column sample, CDS/amplify, mux, and ADC. Three colored lanes underneath label slow leakage accumulation, fast transient settling, and random noise floor. Readout chain in one loop Reset → Integrate → Select → Sample → CDS → Mux → ADC Reset baseline Integration store charge Row select connect Column sample freeze time CDS / Amp stabilize Mux throughput ADC codes Slow errors (accumulate during integration) leakage paths input bias current temperature drift Fast errors (frozen at sampling time) switch injection settling time clock alignment Random noise (low-dose floor) kTC thermal noise 1/f & ref noise Diagnostic cue: drift/lag points to slow leakage; stripes point to sampling/settling; grain points to noise floor.

H2-5 · Leakage: what it is, where it comes from, and how it hurts images

In an FPD readout, leakage means any path that continuously removes or injects charge during the integration window. Because the error accumulates with time, leakage often becomes visible as baseline drift, gray-level lift in dark areas, lag/ghosting after exposure changes, or fixed-position stripes when a leakage path is channel-correlated. The sections below group leakage sources for quick Ctrl+F verification and map each group to typical symptoms and front-end controls.

Leakage sources (Ctrl+F groups)
Group A — Pixel dark current / material background
  • Signature: strongly temperature- and integration-time-dependent; drift grows as the window lengthens.
  • Typical symptoms: black-field drift, slow lift in low-signal regions, uneven recovery after long holds.
  • Front-end controls: define a stable black-reference refresh cadence and temperature-aware calibration points.
Group B — TFT off-leakage, ESD / protection-device leakage
  • Signature: correlated with scan state, bias conditions, and switch stress; can appear as channel- or region-specific behavior.
  • Typical symptoms: fixed-position column/row artifacts, scan-mode-sensitive stripes, localized lag.
  • Front-end controls: select low off-leakage switch structures and avoid stressing off devices; use bootstrapped approaches when needed to reduce leakage and injection tradeoffs.
Group C — AFE input bias, switch leakage, PCB contamination / moisture
  • Signature: strongly dependent on high-impedance node layout and environment; humidity and residues can dominate.
  • Typical symptoms: global slow drift, drifting offsets that worsen in humidity, unpredictable dark lift that improves after cleaning.
  • Front-end controls: guarding around high-Z nodes, ultra-low-bias input selection, disciplined cleaning + conformal coating, and keeping sensitive nodes short and well-isolated.
Group D — Dielectric absorption / residual charge (image lag)
  • Signature: exposure-history dependent; shows time-constant recovery across multiple frames and changes with reset/clear timing.
  • Typical symptoms: lag/ghosting after bright-to-dark transitions, delayed baseline recovery, “memory” of previous frames.
  • Front-end controls: reset/clear strategy (timing and amplitude) aligned with sampling/CDS to reduce residual-charge carryover.
Practical symptoms and fast discrimination cues
  • Black-field drift / gray lift: if it grows with integration time and temperature, suspect Groups A/C before chasing ADC bits.
  • Lag / ghosting: if it depends on exposure history and decays across frames, suspect Group D and reset/clear timing.
  • Fixed-position stripes: if stripes are channel-locked or scan-state dependent, suspect Groups B/C or sampling-window sensitivity.
Front-end controls (what is actually controllable here)
Guarding
Use guard rings and controlled return paths around high-impedance input nodes to suppress surface leakage and humidity-driven drift.
Cleaning / coating
Residues and moisture can dominate leakage; disciplined cleaning and conformal coating often reduce drift more than circuit tweaks.
Bootstrapped switch
Reduce off-device stress and improve linearity by keeping effective switch voltages controlled, easing the Ron/leakage/injection trade space.
Input stage choice
Ultra-low input bias and well-defined input protection prevent slow charge errors from accumulating across long integration windows.
Reset strategy
Reset/clear timing and amplitude determine how much residual charge and memory is carried into the next frame, directly shaping lag/ghosting.
Leakage map: sources → symptoms → front-end controls Block diagram with four leakage source groups feeding a symptom panel (drift, gray lift, lag/ghost, stripes) and then a front-end control panel (guarding, cleaning/coating, bootstrapped switch, input choice, reset strategy). Leakage path map Sources → symptoms → controllable front-end actions Leakage sources (Ctrl+F) A · Pixel dark current temp • long window B · TFT / ESD leakage scan-state linked C · AFE / PCB leakage humidity • residue D · Lag / residual charge history dependent Image symptoms Black drift baseline shift Gray lift long window Lag / ghost memory Stripes channel-locked Front-end controls Guarding Clean / coat Bootstrapped SW Input choice Reset strategy Rule of thumb: longer integration amplifies leakage errors; history dependence points to lag; channel-locked artifacts point to switch/AFE paths.

H2-6 · Row/Column switches & drivers (selection rules)

Row and column switching define whether a pixel is sampled cleanly or whether the sampling instant freezes transient errors into stripes. Selection is not only about on-resistance. Long integration emphasizes off-leakage and bias current; high frame rate emphasizes settling time, injection, and channel alignment. The rules below focus on readout-visible risks and suppression ideas.

Row driver (gate line)
  • Pulse amplitude & edge rate: edges that are too fast increase coupling and ground bounce; edges that are too slow consume settling budget.
  • Coupling into column lines: gate transitions can capacitively inject steps into columns; if sampling is close, the step is frozen as a stripe.
  • Ground bounce & return path: uncontrolled return currents shift references at the sampling instant, creating frame-locked artifacts.
Column switch (signal path)
  • Ron vs leakage: Ron sets settling time; off-leakage sets long-window drift. Both matter, but the priority depends on window and frame rate.
  • Charge injection: switching events can shift the sampled baseline; if the shift is channel-correlated, it becomes stripes/FPN.
  • Bandwidth & parasitic capacitance: parasitics reduce effective bandwidth and eat the settle margin, raising risk at higher frame rates.
Engineering selection boundaries (quotable rules)
  • When integration time is longer or temperature drift is larger, prioritize off-leakage and input bias current before chasing Ron or bandwidth.
  • When frame rate is higher, prioritize settling budget, injection control, and sampling-window stability before incremental noise tuning.
  • When stripes track scan timing, prioritize coupling/ground bounce and sample timing checks before increasing ADC resolution.
Row/column switching and the sampling window Diagram showing row driver (gate line) selecting a row, column line feeding sample/hold and CDS/ADC, with a highlighted settle window and sampling instant. Callouts show leakage, charge injection, and ground bounce risks. Switching → settling → sampling Errors become stripes when the sampling instant freezes transients Row driver Gate pulse Edge rate coupling • bounce Panel row/column Column line Sampling chain Sample / Hold CDS / Amplify ADC Timing window Row select Settle window Sample Convert Leakage Injection Ground bounce Selection boundary: long integration → prioritize leakage & bias; high frame rate → prioritize settling, injection, and sampling stability.

H2-7 · Low-noise AFE: what actually sets the noise floor

In an FPD readout, the visible noise floor is set by where noise enters the chain and whether the sampling instant freezes a transient. Some terms are truly random (grain), while others are repeatable timing-linked offsets that look like “noise” but become stripes or fixed-pattern texture. The checklist below groups the dominant terms by entry point and ties each to practical consequences and readout-level controls.

Noise terms by where they enter (engineering view)
Reset & sampling terms (often amplified by timing sensitivity)
  • kTC (reset uncertainty): defines a hard baseline unless correlated sampling removes it.
  • Charge injection / feedthrough: can be repeatable; becomes stripes when channel-correlated or when sampling is too close to switching.
  • Sampling/settling sensitivity: if small phase shifts change texture, the dominant error is often a frozen transient rather than white noise.
Amplifier/input terms (true random noise contributors)
  • Thermal noise: grows with bandwidth; tight settle windows push bandwidth upward, raising the floor.
  • 1/f noise: dominates low-frequency stability; shows as slow baseline “breathing” or low-dose texture if not suppressed.
Reference & supply coupling (system-injected noise seen at readout)
  • Reference noise: directly maps into code jitter and channel mismatch, especially in parallel channels.
  • Supply/digital coupling: can appear as frequency-locked texture; changes with clocking activity more than with gain.
CDS vs auto-zero vs chopper (what each solves, and what it costs)
CDS (Correlated Double Sampling)
Solves: reduces reset-related offsets and low-frequency drift in the sampled result. Cost: tighter timing/settling requirements; switching transients and coupling become more visible if the sampling window is not clean.
Auto-zero (AZ)
Solves: reduces amplifier offset and slow drift, improving channel consistency. Cost: can introduce sampling/folded noise behavior and demands disciplined timing so the correction does not create texture.
Chopper
Solves: strongly suppresses 1/f at the readout output (especially valuable for baseline stability). Cost: introduces ripple/modulation products; filtering and sampling alignment must prevent visible patterning.
Noise floor map for an FPD AFE readout Block diagram of the readout chain with grouped noise entry points (reset/sampling, amplifier, reference/supply) and mitigation blocks (CDS, auto-zero, chopper). Includes an indicator separating random grain from repeatable timing-linked artifacts. Noise floor contributors Where noise enters + how it becomes visible Readout chain Reset Integrate Sample / Hold AFE ADC Reset & sampling entry kTC Injection Settling Frozen transients → stripes / texture if sampling is too close to switching Amplifier & reference entry Thermal 1/f Ref / Supply Random grain → input-referred noise and channel-to-channel matching Mitigation at readout level CDS Auto-zero Chopper Tradeoff: timing sensitivity / ripple / artifacts Practical rule: if small sampling shifts change texture, focus on injection/settling and coupling before chasing ADC bits.

H2-8 · ADC choices that match FPD constraints

ADC selection for an FPD is dominated by parallelism and consistency, not just nominal resolution. Column-parallel architectures win throughput but raise channel-matching and thermal-gradient risks. Shared ADC architectures ease matching but tighten settling and switching-injection control. The selection logic below frames SAR, ΣΔ, and pipeline as “when to choose what,” and ends with acceptance metrics that can be audited during bring-up.

Column-parallel ADC vs shared ADC (FPD-specific trade space)
Column-parallel ADC
  • Strength: throughput and tight per-column timing alignment for higher frame rates.
  • Risk: channel mismatch (offset/gain/INL drift) can become column stripes and fixed texture.
  • System pressure: power/area and thermal gradients can worsen drift and matching over time.
Shared ADC (multiplexed)
  • Strength: improved converter consistency (same ADC reused) and reduced area.
  • Risk: tighter settle budget and higher sensitivity to mux injection/crosstalk near sampling.
  • System pressure: switching activity and timing discipline determine whether artifacts appear as stripes or texture.
SAR vs ΣΔ vs pipeline (when to choose which)
SAR
Choose when: higher throughput and deterministic sampling are required. Watch for: reference noise and sample/hold errors mapping directly into codes and channel mismatch. Audit: input-referred noise, S/H error, drift, and channel matching under thermal gradients.
ΣΔ (Sigma-Delta)
Choose when: low-noise and linearity are prioritized and the system can tolerate filtering/latency management. Watch for: delay and alignment constraints across channels if frame/line timing is strict. Audit: low-frequency noise spectrum, drift, and channel-to-channel latency alignment.
Pipeline
Choose when: extreme throughput is the top constraint (frame rate dominates). Watch for: power/thermal impact on matching and sensitivity to reference/supply disturbances. Audit: INL/DNL across temperature, reference sensitivity, and channel consistency versus activity.
Acceptance metrics (auditable checklist)
  • Input-referred noise: predicts low-dose grain more directly than nominal bits.
  • INL/DNL: impacts gray-level uniformity and subtle contrast; nonlinearity can create slow texture.
  • Channel matching: the primary driver of column stripes/FPN in parallel architectures.
  • Temperature drift: baseline and gain stability over time; thermal gradients amplify mismatch.
  • Sample/hold error: creates sampling-time texture and sensitivity to switching/settling near the acquisition edge.
ADC decision map for Digital X-ray FPD readout Diagram mapping FPD constraints (long integration, high frame rate, consistency) to architecture choices (column-parallel vs shared ADC) and ADC types (SAR, Sigma-Delta, Pipeline), ending with an acceptance checklist. ADC choices under FPD constraints Parallelism, matching, drift, and sampling errors dominate outcomes FPD constraints Long integration noise + drift High frame rate settling budget Consistency avoid stripes Audit-first thinking measure what matters noise • match • drift Architecture Column-parallel ADC Throughput Matching Thermal drift risk Shared ADC (mux) Consistency Injection Tight settling ADC type SAR deterministic S/H + ref ΣΔ low-noise latency Pipeline throughput power/heat Acceptance checklist Noise INL/DNL Matching Drift S/H error Audit focus: input-referred noise and channel consistency usually predict image outcome better than nominal resolution alone.

H2-9 · Clock & sync distribution (requirements only)

Synchronization in an FPD readout is a contract, not an implementation detail. The readout chain must agree on which events define exposure, where frame and line boundaries begin, and which sampling edge is considered “truth.” Jitter and phase noise matter because they degrade sampling consistency and create channel-to-channel phase skew, which can appear as texture, stripes, or unstable edges when frames are compared.

Required signals and timing relationships
1) Exposure trigger (event anchor)
  • Defines: the exposure event used to align integration and readout timing.
  • Must guarantee: repeatable trigger-to-integration and trigger-to-readout timing (stable latency).
  • Failure signature: frame-to-frame inconsistency that does not average out, especially in low-dose comparisons.
2) Frame sync (frame boundary)
  • Defines: start/end of each frame for scan, buffering, and calibration-table switching.
  • Must guarantee: stable frame period and consistent frame boundary alignment with readout state.
  • Failure signature: residual stripes or drift when corrections are applied at the wrong time boundary.
3) Line sync (scan cadence)
  • Defines: line stepping and the safe scheduling of row/column switching events.
  • Must guarantee: consistent line-to-line phase and a “quiet” settle window before sampling.
  • Failure signature: timing-linked column stripes that change when scan phase is nudged.
4) Sampling clock (the truth edge)
  • Defines: the exact sampling instant relative to switching, CDS/AZ phases, and settle time.
  • Jitter focus: primarily impacts sampling consistency and channel-to-channel phase skew.
  • Failure signature: unstable texture/edge detail when frames are compared under identical exposure.
Implementation note (kept out of this page)

Detailed PTP, genlock, and full clock-tree design belong on the dedicated Sync / Trigger & Timing page. This section defines only the required signals and their timing contracts.

Sync contract timeline for an FPD readout Timeline diagram showing exposure trigger anchoring integration, frame and line sync defining scan boundaries, and sampling clock edges occurring after a settle window to avoid switching transients. Notes that jitter/phase noise affects sampling consistency and channel phase alignment. Clock & sync requirements Define the timing contract (not the distribution implementation) Timeline Exposure trigger event anchor Integration window Frame sync frame boundary state reset Readout scan Line sync + switching + settle + sample Line sync scan cadence Row/Col switching transients Settle window quiet time Sampling clock truth edge Jitter / phase noise focus Sampling consistency Channel phase skew Requirement-only rule: define edges and guard windows first; distribution methods belong to the timing page.

H2-10 · Calibration & correction you cannot skip (FPD-specific)

FPD image quality depends on repeatable correction of unavoidable non-idealities: offset drift (DSNU), gain mismatch (PRNU), defective pixels, column stripes from channel mismatch and timing sensitivity, and temperature-driven changes. These are not optional enhancements; they are required steps to make raw readout data stable, comparable, and diagnostically usable. The sections below state why each correction is mandatory and where it is most reasonable to apply it: ASIC, FPGA, or host.

Mandatory corrections (what, why, and best placement)
1) Offset / DSNU (dark signal non-uniformity)
  • Why it matters: removes baseline drift and dark-field texture that swamps low-dose contrast.
  • Typical symptom: black-field lift, slow drift, blotchy dark shading.
  • Best placement: ASIC/FPGA for per-frame streaming correction; host for long-term modeling or adaptive strategies.
2) Gain / PRNU (photo response non-uniformity)
  • Why it matters: equalizes pixel/column sensitivity so uniform exposures look uniform.
  • Typical symptom: mottled shading under flat-field conditions.
  • Best placement: FPGA/host for flexible LUTs and mode/temperature segmentation; ASIC/FPGA for simple fixed-gain maps.
3) Bad pixel map (defect handling)
  • Why it matters: prevents fixed bright/dark defects from becoming obvious after enhancement or averaging.
  • Typical symptom: stable dots or short streaks at the same positions across frames.
  • Best placement: FPGA/host for upgradeable interpolation and easy table updates; ASIC for minimal masking only.
4) Column stripe correction (channel/timing mismatch)
  • Why it matters: column artifacts are among the most visible and hardest to hide with later processing.
  • Typical symptom: vertical stripes that persist across the full frame and change with timing conditions.
  • Best placement: FPGA for real-time streaming compensation; host for heavier models if bandwidth/latency allow.
5) Temperature compensation (drift control)
  • Why it matters: leakage and reference behavior are temperature-sensitive; without compensation, calibrations do not stay valid.
  • Typical symptom: baseline/gain changes during warm-up or ambient shifts, with drifting residual shading.
  • Best placement: FPGA/host for segmented LUTs, interpolation, and policy updates; ASIC for basic temperature telemetry hooks.
Boundary (kept out of this page)

This section covers only FPD-required corrections (DSNU, PRNU, defect maps, stripe correction, temperature compensation). ISP/HDR pipelines, compression, and codec/recording algorithms belong to other pages.

FPD calibration and correction pipeline map Pipeline diagram from raw FPD frame to corrected frame, with mandatory correction blocks: offset/DSNU, gain/PRNU, bad pixel map, column stripe correction, and temperature compensation. Each block indicates the most common placement layer: ASIC, FPGA, or host. Mandatory correction pipeline Raw output → stable, comparable frames Raw frame FPD output Streaming correction stages Offset / DSNU drift / shading ASIC / FPGA Gain / PRNU flat-field FPGA / Host Bad pixel map dot defects FPGA / Host Column stripe mismatch FPGA Temp comp stability FPGA / Host Corrected frame stable output Rule: stabilize raw non-idealities first; advanced ISP and compression belong to other pages.

Scope Guard — Digital X-ray FPD (H2-11 / H2-12)

Vertical only · No cross-topic spill
Allowed keywords
noise · temporal noise · DSNU · drift · temperature sweep · linearity · saturation · low-dose consistency · crosstalk · row/column coupling · charge injection · FPN/stripe · lag · ghosting · step response · trigger latency · frame drop · frame jitter · vendor questions · AFE · analog switch · driver · ADC · reference noise · channel matching · jitter · fanout · monitoring
Banned keywords
frame grabber · PCIe · DMA · retimer · recorder · NVMe · UFS · codec · compression · ISP · HDR · denoise · security · HSM · secure boot · PTP · Genlock · full clock tree · hospital network

H2-11 · Bring-up & validation checklist (engineering acceptance)

This checklist turns “looks good” into measurable pass/fail evidence for an FPD readout chain. Each item defines how to measure, what to calculate, and what failure signatures imply—so noise, drift, stripes, lag, and sync problems can be separated quickly.

0) Preconditions (lock repeatability before measuring)
  • Thermal state: record at least “cold start” and “thermal steady” (log temperature).
  • Dark condition: light fully blocked; exposure disabled for noise/drift baselines.
  • Fixed timing: keep frame rate, integration time, and sampling phase constant per run.
  • Frame count: capture a stack (e.g., 32/64/128 frames) under identical conditions.
  • Output boundary: validation stops at digital frame output (no storage/codec topics).
Bring-up checklist (printable)
Tip: keep one condition per run; change only one knob (integration / temperature / sampling phase) at a time.
Item How to measure (setup) Metric to compute Interpretation (what it usually means)
Noise — dark stack
black-field baseline
 Dark frames; fixed integration (short + long); capture N frames; repeat at cold and steady temperature. Per-pixel temporal σ (std across frames); column/row mean profiles; mean vs time drift curve. Random-like σ → readout noise; stable stripe in mean profile → channel mismatch / sampling phase; mean drift → leakage/offset thermal behavior.
Noise stability — over time
repeatability
 Repeat the same dark run after warm-up; keep all timing identical; log temperature and supply status. σ map difference (run A vs run B); drift rate (mean slope); stripe amplitude delta. Large changes without configuration change → thermal settling, bias/leakage sensitivity, or sampling edge too close to switching.
Linearity & dynamic range
low-dose + saturation
 Step exposure levels (low→high); capture a few frames per level; keep integration and timing fixed per sweep. Fit line in operating region; residual vs signal; identify saturation onset (per-channel if possible); check low-end consistency across pixels/columns. Early saturation in subsets → channel mismatch; nonlinearity at low end → drift/leakage dominates; residual structure → timing/settle artifacts.
Crosstalk & fixed patterns
row/column coupling
 Use single-line/single-region stimuli (or controlled patterns); compare before/after; optionally shift sampling phase/settle window slightly. Crosstalk ratio (leak amplitude / main amplitude); stripe amplitude vs sampling phase; neighbor response map. Strong phase dependence → switching transient sampled; weak phase dependence but persistent stripes → channel mismatch or calibration placement.
Lag / ghosting
step response decay
 High→low and low→high steps; record K frames after the step; repeat for short/long integration and at multiple temperatures. Lag(k) curve = residual / step amplitude; compare Lag(1), Lag(5), Lag(20) across conditions; track temperature sensitivity. Strong temperature dependence → leakage/thermal drift influence; strong dependence on reset/phase settings → residual charge paths in readout/reset.
Sync behavior
how to measure
 Probe exposure trigger, frame sync, and a “frame arrival marker”; capture long runs; repeat under stress (temperature / frame rate). Trigger→frame latency distribution; frame period jitter; frame drop count (missing sequence/marker). Wide latency spread → unstable boundary timing; drops tied to conditions → bandwidth/timing margin issue; jitter growth → sampling consistency risk.
Fast triage cues (what to change first)
  • If stripes change when sampling phase/settle window is nudged: treat as “switching transient sampled” first.
  • If mean drifts with temperature or time: treat as leakage/bias/offset thermal behavior (separate from random noise).
  • If lag changes strongly with reset strategy: treat as residual charge path/reset phase sensitivity before tuning later stages.
Bring-up validation matrix for an FPD readout Block-diagram matrix showing input captures (dark stack, step exposure, pattern stimulus, step decay, trigger sync capture) producing maps/curves/distributions used to accept or triage FPD readout performance. Bring-up validation matrix Capture → compute → accept / investigate Captures Dark frame stack short + long integration Step exposure sweep low-dose → saturation Pattern stimulus row/column crosstalk Step response capture lag / ghosting Trigger + frame capture latency / jitter / drops Compute outputs Temporal σ map noise floor Column/row means stripe fingerprint Drift curve time / temp Line fit + residual linearity check Crosstalk ratio map neighbor leakage Lag(k) decay k = 1/5/20 Latency + jitter drops counter Accept / Investigate (with evidence) Keep conditions fixed per run; change one knob at a time to reveal root causes.

H2-12 · IC selection cues: what to ask vendors (with part anchors)

Vendor conversations fail when key parameters are not pinned to temperature, timing phase, and channel-to-channel consistency. Use the questions below as an RFQ checklist. Part numbers listed are spec anchors (reference points for the level of leakage/noise/jitter transparency to request), not mandatory design choices.

Before asking vendors, provide these inputs
  • Panel type (a-Si TFT / a-Se / CMOS) and approximate rows/columns.
  • Integration time range and frame-rate range for each mode.
  • Estimated per-column/per-pixel effective capacitance range (or best current estimate).
  • Acceptance priorities: low-dose stability, stripe sensitivity, lag targets.
  • Where correction is expected: ASIC vs FPGA vs host (policy preference).
A) AFE / front-end amplifiers
Focus: input bias/leakage, low-frequency stability, matching, and temperature behavior
Ask for temp-binned evidence
  • Input bias / leakage: typ/max at 25°C and high temperature, with test conditions and input voltage range.
  • Low-frequency stability: 0.1–10 Hz behavior (drift/1/f), and warm-up settling guidance.
  • Sampling/reset structure: support for CDS / auto-zero / chopper; what artifacts each can introduce in a sampled chain.
  • Channel matching: offset/gain/skew consistency across channels; how it is guaranteed (trim, calibration, or characterization).
  • Temperature curves: provide plots (bias, offset, gain vs temperature) rather than a single-point table.
Spec anchor part numbers (examples)
TI OPA140 · ADI ADA4522-2
B) Row/column switches & drivers
Focus: off-leakage, charge injection, ESD side effects, and timing sensitivity
“Typical” is not enough
  • Off-leakage vs temperature: provide max values at high temperature and across relevant input voltages.
  • Charge injection / feedthrough: how it scales with signal level and timing; ask for characterization, not marketing claims.
  • ESD structures: whether protection paths increase leakage or distortion at high temperature.
  • Parasitics: Ron and capacitance ranges that determine settling margin before sampling.
  • Fingerprints: ask how stripe artifacts change with sampling phase (helps separate transient sampling vs mismatch).
Spec anchor part numbers (examples)
ADI ADG1201 · TI TMUX1108
C) ADCs (per-column or shared)
Focus: channel-to-channel consistency, reference behavior, and synchronization support
Consistency > headline bits
  • Channel matching: how offset/gain/skew mismatch is specified and bounded across channels and temperature.
  • Reference noise sensitivity: what reference quality is required, and how reference disturbances map into visible artifacts.
  • Sampling behavior: sensitivity to settle time; ask for guidance on “switch → settle → sample” constraints.
  • Linearity stability: INL/DNL over temperature and across sampling rates relevant to frame timing.
  • Calibration hooks: internal self-cal features or documented procedures to support system-level calibration.
Spec anchor part numbers (examples)
ADI AD4003 · TI ADS127L01
D) Clock / sync components (requirement-level questions)
Focus: jitter/phase-noise reporting, fanout additive effects, and monitoring
Keep to requirements
  • Jitter/phase-noise disclosure: require measurement conditions and frequency ranges, not a single isolated number.
  • Fanout additive effects: how each stage impacts alignment and sampling consistency.
  • Skew control: whether per-output delay/skew can be adjusted or characterized.
  • Monitoring: loss-of-lock / ref-missing / output status visibility for validation and bring-up diagnostics.
Spec anchor part numbers (examples)
TI LMK04828 · ADI AD9528
Mini RFQ template (copy/paste)
Provide typ/max values at 25°C and high temperature; include test conditions and plots where applicable. Confirm channel-to-channel consistency limits and whether artifacts change with sampling phase/settle time. Attach characterization data for leakage/bias/drift, charge injection behavior, reference sensitivity, and jitter/fanout additive effects.
Vendor question map for FPD readout IC selection Four-block map (AFE, switches/drivers, ADC, clock/sync) with question tags and example spec-anchor part numbers. Diagram emphasizes temperature-binned leakage, matching, reference noise sensitivity, and monitoring. Vendor question map Ask for evidence across temperature, phase, and channel consistency Readout blocks to qualify AFE bias / drift / match OPA140 · ADA4522 Switch / driver leakage / Qinj / ESD ADG1201 · TMUX1108 ADC consistency / ref AD4003 · ADS127L01 Clock / sync jitter / fanout LMK04828 · AD9528 Question tags (keep short, require evidence) Bias vs temp Leakage max Charge injection Matching Plots Ref sensitivity Skew limits Phase dependence Jitter conditions Use part numbers as spec anchors; require temperature-binned max values and characterization plots.

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H2-13 · FAQs (Digital X-ray FPD readout)

These FAQs help diagnose FPD readout problems along three lines: leakage/drift, noise/fixed patterns, and sync/timing. Each answer is self-contained and points to a measurable next step.

1) What is the fastest way to tell leakage drift from random readout noise in a dark field?
Random readout noise shows up as frame-to-frame variation (pixel standard deviation) with a stable mean, while leakage drift shows up as a moving mean level over time or temperature. Capture a dark-frame stack at fixed timing, then compare per-pixel std and the mean-versus-time curve. Next step: repeat at a second temperature to confirm drift sensitivity.
2) Why does longer integration time amplify bias and leakage errors in FPD readout?
Integration converts tiny currents into charge, so any pixel dark current, switch leakage, or AFE input bias accumulates into a visible offset. A key check is whether black level rises roughly with integration time and grows faster at higher temperature. Next step: run short vs long integration dark tests and prioritize lower leakage/bias paths (guarding, cleanliness, switch selection, reset strategy).
3) How can you separate image lag caused by residual charge from timing or reset strategy issues?
Use a step test (high→low and low→high) and plot residual versus frame index, such as Lag(1), Lag(5), and Lag(20). If the lag changes strongly when reset pulse width/level or sampling phase is adjusted, the readout/reset timing is a prime suspect. If lag mainly tracks temperature, leakage paths dominate. Next step: sweep reset and sampling phase while logging lag curves.
4) Why do column stripes appear even when temporal noise looks low?
Column stripes are fixed-pattern components, not random noise. Temporal noise can be low while column-to-column offsets or gains remain different, or while sampling captures a consistent switching transient. Check the column-mean profile within a frame and whether stripe amplitude changes when the sampling phase/settle window is nudged. Next step: separate “phase-sensitive stripes” (transient sampling) from “phase-insensitive stripes” (mismatch/calibration).
5) What switch parameters most often turn into visible fixed patterns (FPN) in FPD panels?
The usual culprits are off-leakage at high temperature, charge injection and feedthrough at the sample moment, parasitic capacitance that limits settling, and ESD/protection structures that add unexpected leakage. A practical check is whether artifacts grow with longer integration or shift with sampling phase. Next step: ask vendors for max leakage vs temperature and charge-injection characterization, then verify with a phase sweep on real hardware.
6) How do you quantify row/column crosstalk in a way that is comparable across builds?
Use a controlled pattern or localized stimulus, then compute a crosstalk ratio such as Neighbor/Main (or dB) for defined neighbors (±1, ±2 columns or rows). Keep exposure level, integration time, frame rate, and sampling phase fixed so results compare across builds. Next step: report both the ratio and the conditions, and re-measure after changing only one knob (gate edge rate or sampling window).
7) When should you prefer column-parallel ADCs over a shared ADC in FPD readout?
Column-parallel ADCs are favored when frame rate is high, settle windows are short, and channel-to-channel timing and consistency must be tightly controlled. A shared ADC can work when throughput is lower or power/area is constrained, but it increases mux settling and skew sensitivity. Next step: compute the per-column time budget (settle + sample + convert) and choose the architecture that preserves margin with temperature and process variation.
8) SAR vs sigma-delta vs pipeline: which ADC family matches FPD constraints and why?
SAR fits well when sampled signals must be captured quickly with deterministic timing, especially in multiplexed column chains with limited settle time. Sigma-delta is strong when bandwidth is lower and noise shaping helps push quantization noise out of band, but latency and digital filtering matter. Pipeline suits very high throughput when sampling windows are extremely tight. Next step: map required sample rate per channel, allowable latency, and the settling margin before selecting by “bits.”
9) What ADC specs most strongly predict “uniform images” rather than headline resolution?
Uniform images depend most on channel-to-channel gain/offset consistency, reference-noise sensitivity, linearity stability across temperature, and sampling behavior (aperture uncertainty and sample/hold errors) that can freeze timing artifacts into stripes. A quick validation is whether column means stay consistent across temperature and frame-rate modes. Next step: require max mismatch bounds, reference guidance, and temperature characterization, then verify with dark and step sweeps.
10) Which sync signals are truly required for stable frame formation in a digital X-ray FPD?
At minimum, an exposure trigger defines the integration window, a frame sync anchors frame boundaries, line/row timing aligns row select and column sampling, and a sampling clock sets ADC timing. Jitter matters because it degrades sampling consistency and channel-to-channel phase alignment. Next step: probe trigger, frame sync, and a frame-arrival marker, then measure trigger-to-frame latency distribution, inter-frame jitter, and any frame drops under stress conditions.
11) Where should offset/gain/stripe corrections live: ASIC, FPGA, or host—and how to choose?
Put corrections where bandwidth and determinism match the need. ASIC-side correction is best for per-channel, real-time consistency with minimal latency. FPGA is ideal when correction tables and modes must be updated and validated frequently while keeping timing predictable. Host correction is flexible for heavier computation, but can suffer from throughput and latency limits. Next step: place DSNU/offset and stripe-sensitive steps as early as practical to avoid amplifying artifacts downstream.
12) What is a minimal bring-up test set that catches most FPD readout failures early?
A minimal set is: (1) dark-frame stack to separate temporal noise, stripes, and drift; (2) step exposure sweep to check linearity, low-dose consistency, and saturation; (3) a crosstalk pattern to quantify neighbor leakage; (4) step response to measure lag decay; and (5) trigger/frame capture to measure latency, jitter, and drops. Next step: run the same set at cold and steady temperature to expose leakage-driven behavior.
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