PET Front-End: SiPM Charge AFE, TDC Timing & Energy Windowing
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PET front-end design is about reliably outputting an event triplet—timestamp, energy, and channel ID—while keeping timing pickoff, energy windowing, and multi-channel sync stable under temperature drift and high count-rate. A buildable solution balances fast/slow paths, calibration, and jitter/skew control so events remain comparable and filterable without hidden drift or pile-up errors.
H2-1 · What this page answers (core answer + boundary)
A PET front-end is successful when it outputs stable per-event data while count-rate rises: an event must carry a comparable { timestamp, energy, channelID } with timing resolution and energy resolution preserved, and with synchronization good enough that timestamps from different channels remain on the same time scale.
The key constraint is coupling: improving timing often pushes bandwidth and noise sensitivity, improving energy often pushes longer shaping and pile-up risk, and synchronization errors (jitter/skew/deskew drift) can erase the value of fine time resolution.
What must be engineered (practical targets)
- Comparable timestamps: fine time (TDC) + coarse time (clock counter) must remain aligned across channels through reset, temperature drift, and cable/trace skew.
- Energy that survives count-rate: shaping/peak/ADC and energy windowing must tolerate pile-up and baseline shift without silently biasing the window.
- Channel identity that stays consistent: mapping of sensor → channelID must remain stable under multiplexing, multi-ASIC layouts, and calibration updates.
Boundary: this page stops at the front-end event output and synchronization interface. Image reconstruction, coincidence algorithms, and storage/recording subsystems are not expanded here.
How to read Figure F1: the same sensor pulse drives two engineered paths. Timing and energy are measured differently and then merged; the clock/sync bus keeps timestamps comparable across channels.
H2-2 · Signal physics that matters (only what shapes the front-end)
PET front-ends do not see a clean “photodiode waveform.” A scintillator creates a pulse with its own decay, and a SiPM turns that into a charge waveform shaped by input capacitance, microcell recovery, and stochastic noise events. These physics directly determine which AFE architecture works, how stable a trigger threshold can be, and how energy integration drifts under count-rate and temperature.
The few “physics knobs” that dominate front-end behavior
- SiPM input capacitance (Cin) + microcell recovery: sets edge speed and how quickly the baseline returns after a large pulse.
- Quench resistance / recovery tail: lengthens the pulse tail, raising pile-up probability at high count-rate.
- Dark count rate (DCR): produces random baseline excursions that translate to false triggers and added timing jitter.
- Optical crosstalk / afterpulsing: adds correlated “extra charge,” biasing energy integration and widening the energy distribution.
- Scintillator decay constant: determines how much useful charge arrives late, impacting optimal shaping time for energy accuracy.
How these non-idealities show up as measurable symptoms
Trigger stability (timing path impact)
- DCR-driven baseline noise → discriminator crossing jitter grows; timing resolution can degrade even if TDC resolution is fine.
- Baseline shift at high count-rate → an apparently “fixed” threshold behaves like a drifting threshold, increasing false triggers or missed events.
- Amplitude variation → leading-edge time-walk appears unless corrected (CFD or multi-threshold schemes addressed later in this page).
Energy integrity (energy path impact)
- Crosstalk / afterpulsing → extra correlated charge inflates measured energy, widening the distribution and destabilizing the window boundaries.
- Recovery tail + pile-up → integrated charge can be biased up or down depending on shaping and baseline restoration behavior.
- Decay constant mismatch → too-short shaping misses late charge (energy low bias), while too-long shaping increases pile-up sensitivity.
Quick front-end checks that confirm the physics is under control
- False-trigger scan vs threshold: plot trigger rate while sweeping threshold; a knee dominated by DCR indicates baseline noise control is the first lever.
- Energy peak drift vs temperature: if window pass rate changes with temperature, SiPM gain/bias tracking and baseline restoration need attention.
- Count-rate ramp test: watch energy peak position and timing jitter while increasing rate; early collapse typically points to recovery tails and pile-up.
How to use Figure F2: if false triggers grow with temperature or count-rate, the baseline/threshold path is being driven by DCR and recovery tails; if energy windows drift or widen, correlated extra charge (crosstalk/afterpulsing) and pile-up are biasing the integration path.
H2-3 · Charge AFE architectures (CSA vs TIA vs active integration)
In PET, the front-end is judged by whether it can preserve event information under large input capacitance, stochastic SiPM noise, and high count-rate. A charge-oriented AFE is used because the detector delivers charge bursts whose edge, tail, and recovery must remain controlled: timing pickoff needs a stable crossing point, while energy measurement needs a repeatable integrated charge with minimal bias from baseline shift and pile-up.
Decision snapshot (what each architecture tends to buy you)
| Engineering axis | CSA (Cf/Rf) | TIA (Rf) | Active integration (gated / dual-path) |
|---|---|---|---|
| Small-signal sensitivity | Often strong when Cf is chosen to convert charge efficiently | Can be strong but stable bandwidth/noise needs careful Cin handling | Strong if integration window is well controlled; supports energy accuracy |
| Recovery & pile-up tolerance | Tunable via Rf·Cf; overload recovery is a key selection criterion | Recovery can be fast, but baseline/threshold stability can suffer under high rate | Best when gate/busy logic avoids integrating overlapping tails |
| Input capacitance (Cin) sensitivity | Still matters (noise-bandwidth trade), but often manageable with Cf/Rf choices | Strong sensitivity: stability and noise rise quickly as Cin increases | Depends on front buffer/split strategy; integration helps energy at large Cin |
| Timing vs energy co-optimization | Works well but can be single-path limited when both timing and energy are pushed hard | Often better suited for fast timing pickoff path | Splits the conflict: fast path for timing, slow/integration path for energy |
Architecture mechanics → selection boundaries
- CSA (charge-to-voltage): feedback capacitor Cf converts event charge into a voltage step; feedback resistor Rf sets the return-to-baseline constant. A practical boundary is set by saturation recovery: if overload recovery is slow, both timing pickoff and energy measurement degrade during high-rate bursts.
- TIA (current-to-voltage): the pulse current produces Vout through Rf, keeping fast waveform features accessible for timing. The boundary is the Cin-dominated stability/noise trade: as Cin grows, noise bandwidth and phase margin constraints become the limiting factor.
- Active integration: a controlled integration window (or dual-path split) stabilizes energy extraction when tails and pile-up are present. The boundary is window discipline: integration must be gated/busy-managed or it will integrate overlapping tails and silently bias energy.
Why saturation recovery matters more than static linearity (PET-specific)
A front-end that clips but recovers quickly may preserve throughput, while a front-end that “looks linear” at low rate can collapse at high rate if it takes too long to return to baseline. In PET, recovery time directly changes (a) threshold crossing stability for timing pickoff and (b) baseline bias for energy integration, which then shifts energy windows.
How to use Figure F3: choose the architecture that remains stable when Cin and count-rate rise. If timing and energy are both being pushed hard, dual-path often becomes the clean way to separate bandwidth needs (timing) from integration needs (energy).
H2-4 · Dual-path front-end (fast for timing, slow for energy)
A dual-path front-end exists to separate two incompatible requirements on the same SiPM event: timing pickoff wants high bandwidth and low latency to stabilize the crossing point, while energy extraction wants controlled shaping/integration to improve SNR and repeatability. When both timing and energy must stay good under high count-rate, splitting the chain reduces hidden coupling and makes calibration tractable.
Dual-path checklist (what must be true for it to work)
- Fast path: keep baseline stable at the discriminator/CFD input; enforce retrigger rules so noise and recovery tails do not create timing storms.
- Slow path: choose shaping/integration to maximize energy repeatability while controlling pile-up bias and baseline shift.
- Input sharing: the split must avoid loading/coupling that lets one path distort the other, especially during overload recovery.
- Merge: event builder must join timestamp (from fast path) with energy (from slow path) using a stable channelID and consistent gating.
Three common coupling traps (symptom → cause)
- Energy shifts when timing thresholds are tuned: split/load coupling or limiter behavior is moving the shared baseline seen by the slow path.
- Timing worsens after large pulses: slow-path overload recovery is bleeding into the shared node, effectively shifting the fast-path threshold.
- Both metrics degrade with rate: pile-up and baseline restoration are not coordinated with gating/busy rules, so events are merged inconsistently.
Merge rules (front-end event builder, minimum logic)
- Reference time: define which fast-path edge becomes the timestamp reference (e.g., CFD crossing) and keep it consistent under amplitude variation.
- Energy window timing: energy must be sampled/peaked under a defined window aligned to the event; busy/holdoff should prevent ambiguous merges.
- Channel consistency: channelID must map to the same sensor for both paths; do not allow independent remaps without updating the merge logic.
How to read Figure F4: the fast lane defines the timestamp reference, the slow lane defines energy and acceptance, and the merge block must join both under consistent gating. The clock/sync bus ensures timestamps remain comparable across channels.
H2-5 · Timing pickoff (threshold vs CFD vs multi-threshold / TOT)
Timing drift in a PET front-end is often dominated by time-walk and crossing jitter, not by the TDC LSB. A fixed-threshold pickoff shifts in time when pulse amplitude or rise shape changes, while random noise turns into time jitter at the crossing point. A practical timing budget uses the crossing “slope rule”: time jitter increases when noise grows or when dV/dt at the crossing becomes smaller.
Two errors with different fixes
- Time-walk (systematic): threshold crossing shifts with pulse amplitude or rise-shape variation. Fix: CFD or multi-threshold/TOT compensation.
- Crossing jitter (random): noise produces time variation around the crossing. Fix: reduce noise at the decision point and/or increase the crossing slope (dV/dt).
Pickoff options (selection boundaries)
| Method | What it reduces | Cost / typical failure mode | When it is usually enough |
|---|---|---|---|
| Leading-edge threshold | Minimal logic, simple timestamp | Large time-walk under amplitude spread; baseline shift looks like threshold drift | Narrow amplitude distribution, stable rise shape, controlled rate/pile-up |
| CFD (constant fraction) | Reduces amplitude-dependent time-walk by referencing a fractional crossing | More analog complexity; still sensitive to noise and pulse-shape variation | Time-walk dominates the timing budget and extra complexity is acceptable |
| Multi-threshold / TOT compensation | Learns amplitude proxy (TOT or multiple crossings) to correct residual time-walk | Needs calibration LUT; pile-up and tails can corrupt TOT unless gating is disciplined | CFD cost is too high, but time-walk must still be reduced with digital help |
Jitter budget (useable front-end view)
- Noise at decision node: integrated noise near the pickoff bandwidth directly raises crossing jitter.
- Crossing slope: shaping/limiting that reduces dV/dt at the decision point enlarges time jitter even if the TDC is fine.
- Baseline motion: tails, overload recovery, and rate-dependent baseline shift appear as effective threshold drift.
- Comparator behavior: propagation delay variation and internal noise can set a floor when analog noise is already low.
Practical validation: sweep amplitude and count-rate while measuring timing mean and RMS. If the mean shifts with amplitude, time-walk dominates. If RMS grows while mean stays stable, crossing jitter or baseline motion dominates.
H2-6 · TDC choices & timestamping (resolution, dead time, calibration)
A PET timestamp is a coarse time counter plus a fine time measurement. Improving fine-time LSB alone does not guarantee better timing if nonlinearity (DNL/INL), dead time, or temperature drift dominates the error. A usable TDC solution makes its errors measurable, calibratable, and stable across channels.
Key specs (front-end interpretation)
- LSB: quantization step, not the full timing RMS.
- DNL/INL: code-width variation and nonlinear mapping that must be corrected by calibration.
- Dead time / multi-hit: minimum re-trigger interval and whether multiple hits can be captured without ambiguity.
- Temp drift: fine-time mapping changes with temperature/voltage; requires monitoring and compensation.
- Channel alignment: per-channel offsets must be measured and stored to keep timestamps comparable.
Implementation routes (front-end-side tradeoffs)
| Route | Typical strengths | Typical boundaries | What must be designed in |
|---|---|---|---|
| FPGA carry-chain TDC | Flexible, tightly integrated with event logic, calibration-friendly | Sensitive to PVT drift and code nonuniformity; requires strong calibration discipline | Code-density calibration, temp tracking, resource/thermal stability |
| Dedicated TDC / ASIC | Predictable timing core, clearer dead time and linearity behavior | Less flexible; interfaces and channel sync strategy must be planned early | Coarse-clock alignment, channel deskew tables, periodic recalibration hooks |
Calibration and channel alignment (minimum viable discipline)
- Startup mapping: build a fine-time LUT to correct DNL/INL into a monotonic time estimate.
- Temp compensation: track temperature (or a reference timing beacon) to update LUT or apply offsets.
- Deskew: maintain per-channel offsets so equal events do not produce systematic channel-to-channel timestamp bias.
- Dead-time characterization: measure multi-hit behavior under rate ramp so event loss is explainable and gated correctly.
Rate stress test: ramp hit rate and measure (a) dead-time losses, (b) channel-to-channel bias, and (c) temperature drift of fine-time codes. A TDC is production-ready only when its LUT and deskew remain stable under realistic thermal gradients.
H2-7 · Energy measurement & windowing (shaping, peak/ADC, stable energy gates)
Energy-window “drift” usually comes from changing measurement conditions: baseline motion, pile-up statistics, and rate-dependent recovery. A stable window is achieved by matching shaping to rate, choosing a robust peak/ADC strategy, and enforcing baseline/quality discipline before accept/reject.
What “energy” means in the front-end
- Peak-amplitude estimate: energy is inferred from the shaped pulse peak; sensitive to baseline offset and peak capture timing.
- Area/charge proxy: energy is inferred from a controlled integration equivalent; sensitive to baseline stability and pile-up contamination.
- Windowing: low/high thresholds define the accepted energy band; stability depends on consistent measurement, not just fixed thresholds.
Shaping choices (CR-RC equivalent): noise vs pile-up boundary
| Shaping direction | Typical benefit | Typical risk | Practical selection cue |
|---|---|---|---|
| Slower / longer shaping | Better energy SNR, narrower spectrum when isolated pulses dominate | More pile-up, more baseline drag, rate-dependent peak bias | Choose when count-rate is moderate and baseline control is strong |
| Faster / shorter shaping | Better pile-up tolerance and rate capability | Higher noise bandwidth, timing-sensitive peak capture, potential linearity stress | Choose when rate/pile-up dominates and window stability is threatened |
Peak detect vs sampling ADC (rate, linearity, complexity)
| Approach | Strength | Boundary under high rate | Stabilization must-haves |
|---|---|---|---|
| Analog peak hold | Lower ADC sampling requirements; simple energy readout path | Reset/hold behavior creates dead-time; droop/leakage and baseline shift can bias peaks | Clear hold/convert timing, rate-aware gating, baseline restore discipline |
| Sampling ADC + digital peak | Consistent calibration and temperature correction; flexible quality rules | Data-rate and sync burden; pile-up makes “peak” ambiguous without gating rules | Sufficient sampling margin, deskew, rate stress tests, pile-up rejection logic |
Window stability checklist (front-end side)
- Baseline control: verify baseline returns within a defined time after large pulses and under rate ramp.
- Calibration discipline: verify energy mapping does not shift with temperature or rate within the expected operating envelope.
- Pile-up handling: define accept/reject rules for ambiguous peaks (quality gating is part of window stability).
- Low/high window reasoning: set low window to suppress scatter/low-energy background and high window to suppress overload/abnormal events.
Rate/temperature sanity test: hold the same nominal window and verify the accepted fraction and peak position remain stable across temperature and count-rate ramp. If the peak shifts with rate, baseline restore / recovery and pile-up handling are the first suspects.
H2-8 · High count-rate pain points (pile-up, saturation, recovery, gating)
High count-rate failures are usually predictable: pile-up biases energy, overload recovery drags the baseline, and comparators retrigger on tails. A robust front-end uses busy/hold-off/retrigger policies to protect measurement integrity and keep throughput explainable.
Symptom → likely cause → first fix (front-end view)
| Symptom | Likely cause | First fix to try |
|---|---|---|
| Spectrum widens or shifts with rate | Pile-up + baseline drag; peak capture is no longer single-event | Strengthen busy/hold-off and baseline restore; reject ambiguous peaks |
| Trigger storm / excessive hit rate | Tail retrigger, noise + low hysteresis, overload recovery oscillation | Apply retrigger suppression + short hold-off around sensitive zones |
| Timing RMS degrades at high rate | Baseline shifts change effective threshold; comparator delay varies after saturation | Enforce recovery-aware gating and verify post-overload settling time |
Recovery-first checklist (what to measure)
- Overload recovery time: time for baseline and noise to return to “valid measurement” after a large pulse.
- False-hit rate: measure hits with input blocked or below threshold; tails and noise often dominate.
- Multi-hit behavior: characterize dead time and whether close events are merged, lost, or mis-timestamped.
- Energy bias under pile-up: track peak shift and acceptance fraction while sweeping count-rate.
Event gating policy (busy, hold-off, retrigger suppression)
- Busy: blocks new events during energy capture or known recovery windows to prevent mismatched peaks.
- Hold-off: short inhibition around comparator-sensitive tail zones to stop re-crossing storms.
- Retrigger suppression: rules that limit repeated hits per channel within a short interval; can tag multi-hit rather than blindly accept.
Most common pass/fail rule: under rate ramp, the accept fraction and energy peak position must remain within defined limits, while false-hit rate and retrigger bursts stay bounded. If tightening windows reduces throughput dramatically, quality gating and recovery timing need adjustment first.
H2-9 · Sync distribution & jitter budgeting (make timestamps comparable)
Comparable timing across modules requires a shared time reference, measurable/compensated skew, and a jitter budget that explains how clock noise, pickoff jitter, and TDC quantization combine into the final timestamp uncertainty.
What “comparable time” means (front-end definition)
- Same reference: coarse counters and fine-time engines are traceable to a common reference clock.
- Skew is systematic: channel-to-channel delay offsets are measured and deskewed (not “averaged away”).
- Jitter is stochastic: clock phase noise, pickoff jitter, and quantization form a budget that predicts RMS timestamp error.
Clock-tree building blocks (where comparability is usually lost)
- PLL / jitter cleaner: sets the phase-noise profile seen by fine timing and coarse counters; lock state must be monitored.
- Fanout & routing: distributes clocks but also introduces additive jitter; routing asymmetry becomes measurable skew.
- Module interfaces: connectors and board-to-board links add fixed delay and temperature drift, requiring periodic deskew.
- SYNC pulse path: if SYNC takes a different path than the clock, counters may “agree” while physical time does not.
Synchronization methods (acquisition-side ladder)
| Method | What it fixes | What it does not fix | Must-have monitor |
|---|---|---|---|
| SYNC pulse (coarse align) | Coarse counter phase alignment and deterministic start | Random jitter and per-channel pickoff noise | SYNC arrival skew & coarse phase error |
| Timestamp alignment (deskew) | Fixed offsets and slow drift (channel-to-channel) | Clock phase noise that is truly stochastic | Skew monitor + deskew LUT validity |
| Periodic calibration (re-deskew) | Temperature drift, aging, and connector variability | Event-level pickoff jitter without SNR improvements | Ref lock status + drift trend alert |
Jitter budget (what to measure and bound)
| Contributor | Where it enters | How it is seen | Primary mitigation |
|---|---|---|---|
| Clock phase noise | Ref, cleaner, fanout, routing | Shared RMS timing spread across channels | Cleaner selection + fanout discipline + routing symmetry |
| Pickoff / comparator jitter | Threshold crossing / CFD decision point | Event-level jitter that tracks noise and slope | SNR improvement, stable baseline, slope-aware pickoff |
| TDC quantization + residual nonlinearity | Fine-time measurement engine | Apparent “extra jitter” if not calibrated | Periodic calibration LUT + temperature compensation |
Pass/fail sanity: with temperature and count-rate ramps, channel-to-channel skew must remain measurable and convergent after deskew, and the timestamp RMS must track the stated budget contributors rather than drifting unpredictably.
H2-10 · Calibration & drift control (production-grade stability)
Long-term stability comes from closing the loop on gain drift and time alignment drift. Temperature-driven SiPM bias changes move the energy spectrum and windows, while channel delay and time-walk tables must remain valid across operating conditions.
Drift chain that causes “window drift”
- Temperature changes shift SiPM gain unless bias is trimmed.
- Gain shift moves measured pulse amplitude/area, so the same physical energy maps to a different code.
- Fixed windows then accept/reject differently, creating the appearance of drifting energy gates.
Calibration assets (front-end side LUTs and validity rules)
| Asset | Input | Output | Version / validity cue |
|---|---|---|---|
| Gain LUT (piecewise) | raw peak/area code + temp bin | corrected energy code | LUT version + temp range + self-test pass flag |
| Delay LUT (deskew) | channel id + drift state | per-channel delay trim | calibration timestamp + drift trend monitor |
| Time-walk LUT | amplitude proxy (energy/TOT) + temp bin | timing correction | LUT version + validity window under rate ramp |
Self-test and calibration source (front-end only)
- Charge injection: validates gain linearity, recovery behavior, and code stability without requiring real scintillation events.
- Light pulser: validates the electro-optical chain response consistency (used as a repeatable reference), without expanding into optics.
- Result flags: self-test pass/fail gates LUT activation and triggers re-calibration if drift is detected.
Production-grade acceptance cues (practical)
- Temperature sweep: energy peak position stays bounded when bias trim + gain LUT are active; otherwise windows must not be trusted.
- Rate ramp: LUTs remain valid (no unexplained peak shift or timing RMS jump) and self-test metrics remain repeatable.
- Version traceability: LUT version, temp range, timestamp, and pass/fail are logged and tied to the current operating state.
Practical field rule: enable LUTs only when self-test passes and reference/temperature are inside the validated range. If a drift alarm fires, freeze acceptance decisions or widen quality gating until re-calibration restores traceability.
H2-11 · Validation checklist & BOM map (make it buildable)
This section closes the loop with what to measure, how to judge pass/fail, and typical failure signatures, then provides a BOM map that stays within front-end scope (categories + key parameters + example part numbers).
Note: Example part numbers below are selection starting points. Final choices must be validated against required bandwidth, dynamic range, channel count, supply rails, and recovery behavior in the target front-end chain.
Validation checklist (measure → method → failure modes)
1) Timing — trigger jitter, time-walk residual, channel alignment
- Trigger jitter (RMS): repeated identical injections; histogram RMS of pickoff timestamp.
- Time-walk residual: sweep amplitude/energy proxy; compare before/after correction table.
- Ch-to-ch alignment residual: same reference event; deskewed relative timing error across channels.
- Charge injection for repeatability; run amplitude sweep to emulate energy spread.
- Test matrix: temperature points (several bins) × count-rate points (low/medium/high).
- Report: jitter vs amplitude, residual time-walk curve, deskew residual trend vs temperature.
- Low-amplitude jitter explosion → insufficient crossing slope, baseline noise, threshold drift.
- Time-walk correction does not converge → unstable proxy (TOT/energy) vs temperature or rate.
- Deskew “works once” but drifts → sync/clock path mismatch or missing periodic re-deskew trigger.
2) Energy — linearity, resolution proxy, window stability (temp & supply disturbances)
- Linearity: injected charge sweep → corrected energy code monotonicity + piecewise slope stability.
- Resolution proxy: fixed injection → energy code distribution width (RMS or FWHM, consistently defined).
- Window stability: lower/upper window edge equivalent code drift vs temperature and supply perturbation.
- Run temperature sweep with bias trim + gain LUT enabled/disabled to quantify improvement.
- Apply mild supply disturbance to confirm window edges are not reference-noise limited.
- Under rate ramp, track peak position and acceptance fraction for fixed windows.
- Peak shifts with count-rate → pile-up, baseline restore instability, or slow shaping not matched to decay.
- Window edge “chatters” → threshold DAC noise, insufficient comparator hysteresis, drifting baseline.
- Temperature drift looks like window drift → missing/incorrect bias temp compensation or LUT validity bins.
3) Count-rate — dead time, pile-up mis-tag rate, overload recovery
- Dead time: accepted event rate vs injected event rate; locate nonlinearity onset.
- Pile-up mis-tag: dual-pulse spacing sweep → wrong energy / wrong timestamp fraction.
- Overload recovery: large pulse → time to return to valid baseline and stable pickoff.
- Dual-pulse generator is the highest-value test: sweep inter-pulse interval and amplitude combinations.
- Under rate ramp, verify busy/holdoff/retrigger rules prevent systematic mis-tags.
- Record: recovery tail length vs shaping constants and amplifier overload specs.
- Long “blind” interval after big events → amplifier overload recovery or too-large Rf·Cf reset constant.
- Energy bias at high rate → baseline restore and pile-up discrimination not robust.
- Trigger storm under pile-up → holdoff too short or retrigger suppression missing.
4) Sync — clock jitter, skew/deskew, reset & power-cycle recovery
- Reference lock/holdover: lock state transitions + alarm counters.
- Skew drift: deskew residual trend vs temperature and time.
- Recovery: after reset/power-cycle, time comparability restore time (SYNC + LUT reload + deskew).
- Reset loop test: repeated reset/power-cycle; verify counter alignment and LUT version correctness.
- Temperature cycling: confirm skew monitor remains repeatable and deskew remains convergent.
- Confirm SYNC path consistency with clock path (avoid “aligned counters, misaligned time”).
- Fixed offset after reset → initialization order, SYNC arrival differences, wrong LUT loaded.
- Skew diverges with temperature → periodic re-deskew trigger missing or temp-binned tables required.
- Timestamp RMS grows beyond budget → unmonitored phase-noise contributor or uncalibrated TDC residuals.
BOM map (category + key parameters + example part numbers)
| Category | Key parameters | Typical pitfalls | Example part numbers |
|---|---|---|---|
| Front-end amplifier (fast / interface) | bandwidth, input noise, input C stability, overload recovery, settling | “High BW” but poor overload recovery; unstable with SiPM + parasitics |
TI OPA858 / OPA855 / OPA857 ADI ADA4817 / ADA4899-1 |
| Comparator / timing pickoff | propagation delay, delay vs overdrive, input sensitivity, hysteresis control, overload behavior | delay shifts with amplitude; false triggers under baseline drift |
ADI ADCMP580 / ADCMP572 TI LMH7322 ADI (Linear Tech) LTC6752 |
| ADC / sampling (energy chain) | ENOB/linearity, sample rate, input BW/driver, reference noise, temp drift | focusing on bits only; ignoring reference + thermal drift and linearity |
TI ADS4149 ADI AD9643 / AD9230 |
| Threshold / window DAC (and refs) | resolution, INL, output noise, drift, reference stability, update glitch | noisy DAC/ref makes window edges “move” and acceptance unstable |
ADI AD5686R TI DAC8568 |
| TDC / timestamp unit | resolution, INL/DNL, dead time, temp drift, retrigger ability, calibration table interface | good LSB but poor INL/temp drift → appears as extra jitter if not calibrated |
TI TDC7200 / TDC7201 ams TDC-GPX2 |
| Clock & sync distribution | phase noise / integrated jitter, fanout additive jitter, skew, lock/holdover alarms, deskew hooks | building for lock only; missing observability and periodic deskew triggers |
TI LMK04828 / LMK05318 / LMK1C1104 ADI AD9516 / AD9545 |
Pass/fail anchor: a front-end is “buildable” when timing RMS, energy-window stability, and count-rate behavior remain explainable by the budget and converge after calibration across temperature, supply disturbance, and reset/power-cycle loops.
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H2-12 · FAQs × 12 (with answers) + FAQ JSON-LD + Scope Guard
These FAQs focus strictly on the PET front-end event chain—how to keep timestamp, energy, and channel ID reliable under drift and high count-rate, without crossing into reconstruction or other sibling topics.
