Skin / Core Temperature: RTD/NTC AFEs, Linearization & ADCs
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Skin/core temperature accuracy comes from controlling the whole chain—sensor choice, excitation, wiring, low-leakage front-end, stable reference/ADC, and disciplined filtering—not from chasing “more bits.” Build an explicit error and timing budget (lead R, self-heating, leakage, EMI, settling) so multi-point readings stay stable, repeatable, and calibratable.
H2-1 · What this page solves: skin vs core temperature chains
Practical temperature accuracy comes from controlling the full chain—not from “more ADC bits.” A robust skin/core measurement path is: probe (RTD/NTC) → excitation/divider → AFE (sense + filter) → low-drift ADC → linearization → calibration storage → stable °C output with artifact handling.
Skin and core temperature channels often share the same electrical blocks, but their engineering constraints differ. Skin sensing is usually dominated by thermal contact variability and external disturbance, while core sensing is dominated by traceable accuracy, long-term drift, and controlled self-heating. This page focuses strictly on the temperature chain: sensor physics, excitation, analog front end, references/ADC, linearization, filtering, and calibration/verification.
Where “skin vs core” differs in real designs
- Dynamics (time constant): the displayed temperature follows a system time constant (contact + encapsulation + placement + digital smoothing), not just the sensor element.
- Thermal coupling: poor contact increases thermal resistance, creating a stable offset even when the electronics are perfect.
- Self-heating budget: excitation that is “electrically quiet” can be thermally wrong; allowable sensor power is often tighter for skin probes placed under insulation or tape.
- Cable length & motion: long leads add resistance error (RTD) and increase EMI pickup, often appearing as slow drift, periodic ripple, or sporadic steps.
- Acceptance criteria: some workflows require tight absolute accuracy; others prioritize stable trend and reliable thresholds. The chain must be sized to the real criterion.
Design goals that should be stated up front
- Accuracy target: allowable error at steady state (after stabilization) and under realistic probe placement conditions.
- Response target: maximum acceptable delay to reach a percentage of final value (mechanical + digital latency combined).
- Stability target: short-term noise (flicker + quantization) and long-term drift (sensor + reference + front-end leakage).
- Fault behavior: how open/short/misplug should be detected and how the output should degrade safely (freeze, flag, clamp).
Quick checklist before choosing parts
- Decide whether the chain must be ratiometric (to cancel reference drift) or can tolerate reference movement.
- Estimate self-heating from excitation and decide a maximum allowable sensor power.
- Decide the wiring model (2/3/4-wire RTD or divider/constant-current NTC) based on cable length and interchangeability needs.
- Define how artifacts should be handled (motion/contact changes): detect and suppress, not just “average longer.”
H2-2 · Sensor choice: RTD vs NTC (and probe mechanics)
RTD and NTC probes can both meet medical temperature requirements, but they fail in different ways. The best choice is made by setting the real acceptance criteria (absolute accuracy vs stable trend), the wiring model (cable length and interchangeability), and the thermal mechanics (contact quality and response time). The electronics should be designed around the dominant error source, not around “generic sensor pros/cons.”
Practical selection boundaries (when RTD is the safer bet)
- Traceability & stability matter: RTDs generally support more predictable long-term drift management and calibration retention.
- Linear behavior is preferred: simpler modeling reduces sensitivity to coefficient mismatch and rounding/lookup artifacts.
- Cable resistance can be controlled: 3-wire (matched leads) or 4-wire sensing is feasible, or cable is short enough that 2-wire error is bounded.
- Failure mode clarity: open/short detection can be implemented with clear thresholds if excitation and protection leakage are controlled.
Practical selection boundaries (when NTC is the better system choice)
- High sensitivity is needed: NTCs deliver large resistance change per °C, which can relax front-end gain requirements.
- Cost and probe variety drive the design: many form factors exist (skin patch, ear, esophageal, catheter), often favoring NTC packaging.
- Digital linearization is acceptable: LUT / Steinhart–Hart / segmented linear fits are already part of the software stack.
- Interchangeability strategy exists: probe binning, probe ID, or system calibration flow is planned so “one curve fits all” is not assumed.
Probe mechanics: why “perfect electronics” still reads the wrong temperature
- Contact thermal resistance: tape pressure, gel, airflow, and skin curvature change the thermal path, shifting steady-state readings.
- Encapsulation & placement: metal tip vs plastic housing changes heat spreading; placement depth changes what is being measured.
- System time constant: sensor thermal mass + contact path + any digital smoothing combine into the response time users experience.
- Cable motion & microphonics: movement can modulate contact and EMI pickup; artifacts often look like steps or slow wander.
Output requirements that drive the choice
| Decision axis | RTD tends to fit when… | NTC tends to fit when… |
|---|---|---|
| Interchangeability | Probe-to-probe variation is expected to be small or handled via wiring compensation. | Probe variation is managed via LUT/ID/bins or calibration workflow. |
| Long cable | 3/4-wire sensing is feasible or cable errors can be budgeted. | Divider/current design and filtering handle pickup; modeling handles nonlinearity. |
| Dominant error | Lead resistance and drift control are the main concerns. | Model mismatch and coefficient drift are the main concerns. |
| Response vs stability | Response is largely mechanical; electronics target stable, drift-aware readout. | High sensitivity helps noise, but response still depends on packaging/placement. |
H2-3 · Excitation & wiring: 2/3/4-wire RTD, NTC divider, ratiometric
Wiring and excitation decide whether lead resistance and reference drift become temperature error. Choose the wiring model first (2/3/4-wire RTD or NTC divider/constant-current), then size excitation to keep self-heating below the error budget while maintaining enough signal above noise.
RTD wiring: what each option actually cancels (and what it cannot)
- 2-wire RTD: lead resistance adds directly to the sensed resistance, so cable/connector changes look like a temperature shift. Use only when leads are short and the allowable error budget can absorb worst-case lead variation.
- 3-wire RTD: cancels lead resistance only under a matching assumption (two leads ≈ equal). The dominant risk is lead mismatch from connector contact, routing asymmetry, aging, or cable bend stress.
- 4-wire RTD: separates excitation and sensing. Sense leads carry ~zero current, so their resistance drop is negligible; lead error is minimized and becomes easier to budget. Cost is pin count, connector complexity, and more nodes to protect from leakage.
NTC excitation: divider vs constant-current (pick by dominant error source)
- Divider (voltage mode): simple and low cost, but accuracy depends on the reference resistor and the ADC reference behavior. Good fit when ratiometric measurement is easy to implement and resistor drift is controlled.
- Constant-current (resistance mode): improves linearity of the transfer in some ranges and can simplify thresholding, but shifts sensitivity to current-source drift and compliance/headroom. Best when current stability is measurable and controlled over temperature.
- High-impedance nodes: in cold ranges NTC resistance can become high; leakage and input bias currents can dominate. Layout, protection choice, and cleanliness become part of the accuracy budget.
Ratiometric measurement: when drift cancels, and when it does not
- Cancels well: reference drift that affects both excitation scaling and ADC reference scaling in the same direction (same source, same path).
- Does not cancel: leakage currents into the sense node, input bias currents through the sensor/resistors, connector contact resistance changes, and self-heating. These create real offsets that remain even with perfect ratiometric structure.
- Practical rule: if long-term drift dominates your spec, start with a drift-canceling structure (ratiometric or 4-wire sense) before increasing ADC resolution.
Excitation sizing: keep self-heating under control without falling into the noise floor
- Set allowable temperature rise from excitation as a budget item (self-heating error). This is often tighter for skin probes under tape/insulation.
- Convert to allowable probe power using probe thermal behavior (vendor guidance or quick bench test). Power must remain below this limit in worst-case ambient and placement.
- Back-calculate excitation level (current or divider values) that respects the power limit across the full temperature range (resistance changes with temperature).
- Check signal-to-noise margin: verify the resulting sense voltage span still exceeds front-end and ADC noise after filtering and averaging constraints.
Debug checklist: how to prove the dominant error is lead R, drift, or self-heating
| Symptom | Most likely cause | Verification step | Fix direction |
|---|---|---|---|
| Offset changes with cable bending / connector touch | Lead/contact resistance variation (2-wire) or mismatch (3-wire) | Substitute a precision resistor at the connector; repeat bend/touch | Move to 4-wire or improve 3-wire matching + connector quality |
| Reading drifts slowly with ambient board temperature | Reference/resistor drift (non-ratiometric) or bias/leakage changes | Log output vs board temp; test with ratiometric mode if available | Adopt ratiometric structure; reduce leakage & bias sensitivity |
| Temperature rises when excitation increases, even in stable bath | Self-heating dominates | Step excitation and observe steady-state ΔT in stable environment | Lower excitation, duty-cycle sampling, or improve thermal coupling |
| Noise is low but absolute offset remains | Model/linearization mismatch or residual lead error | Compare against known points; check probe coefficients / bins | Probe binning, LUT update, or calibration coefficients |
H2-4 · Analog front-end: PGA/instrumentation, filtering, input protection (temperature-only)
A temperature AFE is not only about gain. It is about keeping low-frequency drift, leakage, and aliasing under control, so the digital linearization and calibration can work consistently across cables, probes, and environments.
When PGA/INA is justified (and when it creates new error)
- Long cable / noisy environment: an instrumentation-style front end helps suppress common-mode pickup and provides a defined input impedance path.
- Low excitation (self-heating limited): PGA improves effective resolution when the sensor voltage span is small.
- Multi-probe or wide range: PGA allows consistent ADC usage without sacrificing either low-end sensitivity or high-end headroom.
- Watch-outs: higher gain increases sensitivity to input bias currents, leakage paths, and switch charge injection. These often appear as slow drift or small offsets that do not average away.
Filtering for temperature channels: anti-alias first, then smoothness
- Anti-alias filter (ADC-side): prevents higher-frequency interference from folding into low-frequency wander that looks like “drift.”
- 50/60 Hz coupling: often shows up as periodic ripple or step-like artifacts after sampling; ensure the analog pole + sampling plan does not convert it into a slow beat.
- Do not hide faults with long averaging: contact changes and open/short events should be detected and flagged, not merely smoothed.
Input protection (temperature-only): “near the connector” is not always correct
Protection is mandatory for probe plug/unplug and ESD, but protection components can introduce leakage that becomes a temperature offset—especially on high-impedance nodes (NTC at cold ranges or sensitive RTD sense points). A practical approach is two-stage protection: a rugged interface stage to absorb ESD, plus an accuracy-friendly stage close to the AFE that limits fault current without injecting large leakage into the measurement node.
Do / Don’t checklist for stable AFEs
- Do: keep the high-impedance sense node short, clean, and away from connector-edge contamination paths.
- Do: place anti-alias filtering so the ADC never sees uncontrolled wideband interference.
- Do: validate leakage sensitivity by testing across humidity/contamination conditions and checking for reproducible offsets.
- Don’t: hang high-leakage protection directly on the precision sense node.
- Don’t: rely on long digital averaging to hide probe contact changes; detect artifacts and handle them explicitly.
Fast fault isolation: symptom → cause → verification → fix
| Symptom | Likely AFE cause | Verification | Fix direction |
|---|---|---|---|
| Slow drift with humidity / after cleaning | Leakage into high-Z sense node (protection, residue, board surface) | Measure input bias/leakage with sensor substituted by known resistors | Move protection, reduce node impedance, improve cleanliness/guarding |
| Periodic ripple or beat pattern | 50/60 Hz pickup + aliasing or inadequate anti-alias filter | Change sampling rate; observe frequency shift/beat behavior | Rework analog pole placement; improve common-mode suppression |
| Step changes during probe motion | Cable microphonics + contact change + AFE high gain sensitivity | Repeat with fixed probe; compare to motion; check node impedance | Reduce gain at sensitive nodes; add artifact detection; improve cable routing |
| Offset changes after plug/unplug events | Protection network leakage shift or input clamp recovery behavior | Log reading before/after plug; test with dummy resistor at connector | Two-stage protection; ensure recovery path; tighten leakage specs |
H2-5 · Linearization: Callendar–Van Dusen & Steinhart–Hart (practical implementation)
Linearization is an engineering control problem: the chosen method must be stable under noise, drift, and probe variation, and it must be version-controlled so updates do not silently change the meaning of “°C”.
RTD: practical Callendar–Van Dusen usage (choose the implementation boundary)
- LUT (table + interpolation): best when repeatability and field maintainability matter. It can encode the target curve and handle local non-idealities. Main risks are table resolution (step artifacts) and interpolation choices that amplify code noise.
- Polynomial / segmented polynomial: compact storage and smooth output. Main risk is edge-region mismatch (fit error grows where data is sparse) and coefficient sensitivity in fixed-point implementations.
- Piecewise linear (PWL): simplest to debug and most stable under limited compute. It trades some accuracy for predictable behavior and easy verification. Main risk is slope/segment boundary handling (continuity and monotonicity).
NTC: Steinhart–Hart vs LUT vs PWL (probe variation is the real decision driver)
- Steinhart–Hart: continuous and compact (few coefficients). Best when the probe family is consistent or the system has a controlled bin/ID strategy. Watch for coefficient mismatch and numeric sensitivity if fixed-point math is used.
- LUT: strongest for interchangeability strategies (per-probe ID curve, per-batch curve, or factory-calibrated curve). The critical requirement is robust table ownership: version, CRC, and traceable provenance.
- PWL: “less compute for more predictability.” Useful when only a few anchor points are needed and field debugability matters. Ensure monotonic mapping and continuity across segments.
Three hidden failure modes in digital linearization
- Code noise becomes °C jitter non-uniformly: the same ADC-code fluctuation maps to different °C jitter depending on the local slope of the curve. Evaluate jitter after linearization, not only at raw code level.
- Filtering delay changes the meaning of “temperature response”: a stable display often comes from filtering. Define whether the output is an instant estimate, a smoothed estimate, or both, so calibration/verification uses the same definition.
- Parameters must be versioned: coefficients/LUT updates can change absolute readings. Store version, CRC, generation source, and applicable probe type/range to keep °C traceable across firmware updates.
Comparison cards: LUT vs Polynomial vs Piecewise Linear (implementation-oriented)
Option A · LUT (table + interpolation)
- Compute: low (lookup + interpolation)
- Storage: moderate to high (table points)
- Best for: per-probe/per-batch curves and long-term maintainability
- Sensitivity: table spacing and interpolation choice can create step/jitter artifacts
- Must-have controls: version + CRC + curve provenance
Option B · Polynomial / segmented polynomial
- Compute: medium (multiply/accumulate)
- Storage: low (few coefficients)
- Best for: fixed temperature ranges with stable probe families
- Sensitivity: coefficient error and numeric format (fixed-point rounding) can shift output
- Must-have controls: coefficient versioning and range validation
Option C · Piecewise linear (PWL)
- Compute: low (segment + linear interpolation)
- Storage: low to medium (anchor points)
- Best for: predictable behavior and easy verification/debug
- Sensitivity: segment boundaries (continuity, monotonicity)
- Must-have controls: boundary tests + monotonic mapping checks
H2-6 · Reference & ADC: low-drift measurement without chasing “too many bits”
In temperature channels, long-term accuracy is usually limited by drift (reference, resistors, bias/leakage, self-heating), not by ADC resolution. Pick architecture to bound drift terms first, then optimize noise and latency.
Drift vs noise: identify what dominates before selecting ADC “bits”
- Drift-dominated: output slowly moves with board temperature, humidity, or time. More bits do not fix this; structural cancellation and leakage/bias control do.
- Noise-dominated: output jitters around a stable mean. Improve excitation signal, front-end noise, filtering, and ADC noise density.
- Sampling/interference dominated: periodic ripple or “beat” patterns appear. Fix anti-alias filtering and sampling plan (especially around 50/60 Hz pickup).
ΣΔ vs SAR (temperature-only boundary)
- ΣΔ ADC: strong fit for low-bandwidth temperature signals and low-frequency noise shaping, often simplifying effective resolution. Watch the digital filter latency and define how that latency maps to “response time” requirements.
- SAR ADC: strong fit when multi-channel scanning and flexible timing are needed, with predictable latency. It requires disciplined anti-alias filtering and layout to prevent wideband interference from folding into low-frequency wander.
- Practical selection: if stable low-bandwidth accuracy is the priority and fixed latency is acceptable, ΣΔ is usually easier to make stable. If timing flexibility and low latency dominate, SAR works well when anti-alias and interference controls are designed as a system.
Reference strategy: when ratiometric cancels drift, and what remains
A ratiometric structure can cancel reference drift when the same reference sets both the excitation scale and the ADC scale. This is a structural drift-cancel mechanism, not a “higher spec reference” requirement. However, ratiometric cancellation does not remove errors that change the sensed node itself.
| What cancels well (ratiometric) | What does NOT cancel |
|---|---|
| Reference voltage drift that scales both excitation and ADC reference | Input bias current offsets through sensor/resistor network |
| Some resistor ratio drift when the ratio is preserved (same network / tracking) | Leakage paths into high-impedance nodes (humidity, contamination, protection) |
| Supply scaling effects that are common to both paths | Self-heating and contact/lead resistance changes (they change the measured element) |
Selection criteria checklist (temperature-only)
- Dominant error type: drift vs noise vs interference folding (choose structure accordingly).
- Need for ratiometric: if drift budget is tight, prefer ratiometric or 4-wire structures before “more bits.”
- Latency allowance: define acceptable delay (especially if ΣΔ digital filters are used).
- Multi-channel behavior: scanning strategy affects aliasing and settling; ensure analog poles support it.
- High-impedance sensitivity: if NTC high-R regions exist, treat bias/leakage as first-class specs.
- Verification path: ensure the architecture supports substitution tests with known resistors and repeatable fixtures.
H2-7 · Error budget: lead resistance, self-heating, drift, and long-cable effects
An error budget is an engineering ledger: define the output accuracy target first, then allocate it to sensor, wiring, self-heating, leakage/bias, ADC/reference drift and noise so each term has a measurable limit.
Define the measurement “error ledger” (use consistent error language)
- Absolute accuracy: difference to true temperature under steady conditions.
- Repeatability (jitter): short-term scatter around a stable mean.
- Drift: slow movement with time, PCB temperature, humidity, or aging.
- Interchangeability: reading shifts when swapping probes/cables/connectors.
- Latency: output delay; treated separately in dynamics (next section).
Practical budget workflow (actionable, test-driven)
- Set the top-line target: steady-state accuracy, allowed drift, and interchangeability limits (°C).
- Pick a combination rule: use worst-case for drift/interchangeability, and RSS for random noise/jitter where justified.
- Allocate limits by category: sensor, lead/contact, self-heating, bias/leakage, ADC/ref drift, noise/interference.
- Back-calculate each bound: convert “allowed °C” into “allowed ΔR / allowed leakage / allowed power” per category.
- Attach a test to every line item: substitution resistors, cable bend/plug cycles, humidity exposure, excitation-step test.
- Lock assumptions: probe type/range, cable length, excitation mode and output filter definition.
Error budget table (source → symptom → how to bound → mitigation)
| Error source | Typical symptom | How to bound (quantify) | Mitigation |
|---|---|---|---|
| Sensor tolerance / aging | Probe swap shifts reading; error depends on temperature range | Use known temperature points or probe datasheet limits; separate electronics by using substitution resistors | Probe binning/ID curves; calibration at key points; stable mechanical coupling |
| Excitation scale error | Board temperature causes slow scaling drift | Compare readings across supply/board temperature; check if drift is common-mode (scaling) vs offset | Prefer ratiometric structures; use matched resistor networks and stable excitation control |
| Lead & contact resistance | Bending cable/plug cycles cause steps; intermittent shifts | Convert allowed °C into allowed ΔR at the operating range; run bend/plug tests and track step magnitude | 3-wire with good matching or 4-wire; robust connector design; strain relief; avoid high-contact variability |
| Self-heating (real ΔT) | Higher excitation reads hotter; effect grows with insulation/poor heat sinking | Estimate P≈I²R or V²/R; verify by stepping excitation and measuring steady ΔT in a stable environment | Lower excitation, duty-cycle measurement, improve thermal coupling, set a self-heating test limit |
| Bias current & leakage | Humidity/contamination sensitivity; slow drift; worse at high-impedance nodes | Swap in multiple resistor values; if error scales with resistance, bias/leakage dominates; run humidity/cleanliness checks | Lower node impedance; guard/clean layout; select low-leakage protection; define leakage budget explicitly |
| ADC gain/offset drift | Whole system shifts with board temperature; stable probes still drift | Substitution resistors at the connector: track gain/offset vs board temperature to isolate ADC/ref chain | Ratiometric where possible; stable reference/resistor networks; periodic self-check on known points |
| Noise / interference folding | Jitter, periodic ripple, beat patterns (often near mains pickup) | Measure raw code spectrum over time; validate anti-alias plan and sampling strategy; compare shield/ground configurations | Anti-alias filtering, sampling plan, shielding and cable routing; digital filtering with defined latency budget |
Practical rule: spend budget where the chain is structurally sensitive (lead/contact, leakage/bias, self-heating). Extra ADC resolution mainly reduces jitter; it rarely fixes slow drift by itself.
H2-8 · Dynamics & filtering: response time, smoothing, and artifact handling
Temperature “slowness” is the sum of probe thermal dynamics and digital smoothing latency. Temperature “jumps” are often artifacts from disconnects, open/short events, or interference folding—best handled by outlier gating and clear degrade/recover rules.
Response time is additive: probe thermal model + digital processing latency
- Probe thermal RC: the physical coupling to skin/body tissue defines the dominant time constant in many designs.
- Sampling + digital smoothing: moving average or IIR improves stability but adds output delay.
- Latency budget: define the maximum allowable output lag first, then distribute it between thermal and digital components.
Filter choices (how they trade jitter, step response, and delay)
| Filter | Strength | Weakness | Best use |
|---|---|---|---|
| Moving average | Good at reducing random jitter with simple implementation | Fixed window causes fixed delay; outliers can “smear” into output | Stable environments; when fixed delay is acceptable |
| 1st-order IIR | Smooth response with tunable time constant; predictable behavior | Still affected by spikes unless paired with gating | General-purpose temperature display with controlled lag |
| Median filter | Excellent at rejecting impulse artifacts (disconnect spikes, brief glitches) | Less effective for continuous noise; window size impacts responsiveness | Systems with intermittent plug/contact artifacts or bursty interference |
Artifact handling: open/short detect, outlier gating, degrade & recover rules
- Boundary checks: detect open/short or out-of-range codes before applying linearization and smoothing.
- Rate-of-change gating: compare each new sample against a plausible maximum ΔT/Δt; reject impossible steps.
- Degrade strategy: hold-last-good value, freeze-and-reacquire, and set a status flag for downstream logic.
- Recover strategy: require N consecutive valid samples before returning to normal output to prevent flapping.
Practical rule: smoothing is for jitter; gating is for artifacts. Use both. Set parameters by latency budget and expected step behavior, not by fixed “magic” numbers.
H2-9 · Safety & EMC (temperature chain only): protection placement and leakage pitfalls
Temperature probes often look “low-speed and easy,” but protection mistakes create precision problems: leakage into high-impedance sense nodes and common-mode EMI converting into differential error can show up as slow drift, periodic ripple, or plug/bend steps.
Two-stage protection mindset (energy handling vs precision protection)
- Stage 1 (connector side): handle ESD/plug events without letting “high-leakage parts” sit directly on the sense node.
- Stage 2 (AFE side): keep leakage/bias paths controlled, define a clean return path, and keep symmetry so EMI does not become differential error.
- Key pitfall: “closest to the interface” can be wrong if it places temperature-dependent leakage and parasitic capacitance on a high-impedance node.
Four-column troubleshooting table (symptom → root cause → verify → fix)
| Symptom | Likely root cause | How to verify | How to fix (minimum needed) |
|---|---|---|---|
| Slow drift with stable environment | Leakage/bias into sense node (protection device leakage, PCB surface leakage, contamination) | Replace probe with stable substitution resistor; compare dry/clean vs humid/dirty conditions | Reduce node impedance; partition protection; choose low-leakage devices near AFE; improve cleanliness and creepage |
| Periodic ripple or beat pattern | Common-mode EMI couples through cable; imbalance converts CM→DM; aliasing/sampling interaction | Move cable routing near/away from aggressors; compare shield/ground configurations; check if ripple changes with symmetry | Improve symmetry, define return path, add controlled RC/anti-alias near AFE; prevent CM→DM conversion |
| Step changes when plugging/bending cable | Contact resistance variation; protection capacitance pulling node; intermittent leakage paths | Plug/bend cycle test; compare multiple cables/connectors; swap wires to see if effect follows imbalance | Connector/strain relief improvements; 3/4-wire where needed; keep sensitive nodes short and protected |
| Probe-dependent instability (worse in high-R regions) | High-impedance sensitivity to bias/leakage; protection leakage becomes dominant | Substitute different resistor values and observe error scaling with resistance | Lower impedance design; limit high-R operating region; keep leakage budget explicit and verified |
Practical placement rules (temperature channel only)
- Keep the sense node short and protected: avoid long exposed high-impedance traces between connector and AFE.
- Separate “energy clamp” from “precision node”: do not attach unknown leakage directly to the sense node.
- Design for symmetry: imbalance is the usual CM→DM converter; symmetric routing and components reduce conversion.
- Make leakage observable: define a leakage budget and verify it with substitution resistors under humidity/temperature stress.
H2-10 · Calibration & interchangeability: factory test, probe ID, and drift tracking
Calibration is only valuable when it is repeatable and traceable: define interchangeability level first, then choose 2-point or 3-point calibration with stability criteria, version/CRC controls, and a locked verification step.
Interchangeability tiers (decide before designing the factory flow)
- Tier A (fully interchangeable): any probe/cable meets the accuracy target without pairing.
- Tier B (family/batch interchangeable): limited interchangeability with controlled probe family or batch constraints.
- Tier C (paired): probe carries ID/coefficients or must be paired; swapping without data causes offset.
2-point vs 3-point calibration (practical boundary)
- 2-point: best when dominant errors look like offset + gain and the curve shape is already controlled by linearization.
- 3-point: best when curve shape variation matters across the temperature range, or when higher interchangeability is required.
- Reality check: extra points do not help if the temperature is not stable. Stability criteria matters more than point count.
Factory calibration checklist (repeatable and auditable)
- Prepare: confirm probe type/range and interchangeability tier; read existing calibration version and CRC.
- Apply temperature point: set target temperature and start a stabilization timer.
- Stability criteria: require low variation over a time window and a bounded temperature trend before capturing samples.
- Capture samples: collect a defined window, reject outliers, store mean and scatter as evidence.
- Compute coefficients: generate 2-point or 3-point parameters; include metadata (tier, probe type, range).
- Write atomically: write coefficients + version + CRC; then read back and verify integrity.
- Verify: re-check at one or more points; decide pass/fail with defined limits.
- Lock: enter locked state; allow recalibration only via a controlled service mode.
Probe ID & coefficient ownership (avoid silent “meaning changes”)
- Device-stored coefficients: simpler, but probe swaps may require re-pairing or re-calibration.
- Probe-carried coefficients (ID + data): stronger for interchangeability, but must validate version, range, and CRC before use.
- Minimum metadata: probe type, valid range, coefficient version, CRC, and lock state.
Drift tracking (lightweight, temperature-channel only)
- Periodic check: validate offset/gain using a known substitute reference or known internal point when available.
- Threshold: declare drift if deviation exceeds the allowed budget (do not “auto-correct” without a controlled mode).
- Action: flag, hold a stable output policy, and enter service recalibration state if required.
H2-11 · Multi-channel integration: multi-point skin/core, multiplexing, power and thermal constraints
Multi-channel temperature is not limited by “ADC bits”. It is limited by channel-to-channel memory (charge/leakage), settling-time discipline after every switch, and board thermal self-heating that quietly shifts offsets.
1) Choose the multi-channel architecture first (3 practical options)
- A. Per-channel conversion: strongest isolation between channels, simplest debug, higher BOM/power.
- B. Shared ADC with scanned MUX: most common; requires strict “switch → settle → sample” timing and leakage control.
- C. Integrated multi-sensor temperature front-end: fastest to productize; often includes sensor drive, linearization, diagnostics.
2) Multiplexing creates 4 deterministic errors (treat them as budget items)
| Mechanism | What it looks like | How to bound it | Mitigation |
|---|---|---|---|
| Charge injection | First sample after switch shifts (step-like) | Measure “first vs settled” delta per channel | Discard first sample; add pre-charge/dummy slot; pick low-injection MUX |
| Leakage | Slow drift; humidity/temperature sensitive | Swap resistor values and watch error scale with R | Lower node impedance; select low-leakage parts; keep the sense node short/clean |
| Parasitic C + RC settle | Different channels need different settle time | Step response after switch; define residual error limit | Explicit settling window; reduce source impedance; optional buffer near ADC |
| Cross-channel memory | Channel A event contaminates B/C briefly | Reorder scan and observe “who affects who” | Group channels by impedance; insert dummy channel between “far apart” nodes |
3) Build a timing budget (so “settling time” is engineered, not guessed)
- Define per-channel update target: core vs skin channels do not need the same update rate or latency.
- Fix the sequence: Switch → Settling window → Sample window → report.
- Make transients disposable: discard the first sample after each switch unless proven settled.
- Use a “dummy slot” when needed: pre-charge the ADC input to a mid-level to reduce memory effects.
- Scan order is a parameter: keep similar impedances adjacent; protect critical channels with longer settle.
4) Low-power and thermal constraints (temperature-chain only)
- Duty-cycled excitation: enable sensor drive only before sampling; confirm thermal equilibrium is not distorted by pulsing.
- Lower front-end bias: high-impedance channels are dominated by leakage/bias; reduce impedance where feasible.
- Board self-heating: keep analog front-end, reference/resistors, and connectors away from hot components and copper heat highways.
- Thermal placement rule: never let the “board heat map” become the temperature signal—physically separate heat sources and sense nodes.
Example parts (reference BOM options)
These are common, practical choices that map to the architectures above (select by accuracy, channel count, and power budget):
- Scanned multi-channel ΣΔ ADC: TI ADS124S08, ADI AD7124-8
- Precision MUX for measurement paths: TI TMUX1108, ADI ADG1208
- Integrated temperature measurement system: ADI LTC2983
- RTD-to-digital (single/critical channel): Maxim MAX31865
- Sensor-interface ADC option: TI ADS1261
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H2-12 · FAQ – Skin / Core Temperature Measurement Chains
These FAQs focus on temperature-only signal chains (RTD/NTC → excitation → AFE → ADC → linearization → filtering → calibration), with practical checks that isolate drift, ripple, slow response, and multiplexing artifacts.
