What this page solves

This page is for AC-DC adapter designs that replace silicon MOSFETs with GaN devices in the power stages. Typical targets include compact USB-C fast chargers and high-density server or CRPS power supplies where switching frequency and power density are pushed aggressively.

• 65–300 W USB-C fast chargers and GaN adapters using PFC plus LLC or active half-bridge stages.
• 300–1000 W server / CRPS power supplies where totem-pole PFC and resonant bridges are often implemented with GaN.
• Designs that already chose a PFC or LLC controller and now need a robust GaN gate driver strategy.

Many designs start by simply swapping silicon MOSFETs for GaN FETs while reusing the existing gate driver and PCB layout. This often leads to unstable gate waveforms, poor efficiency and even device failures because the original driver and layout were never intended for GaN switching speeds and dv/dt.

• Gate drivers that still deliver 10–12 V or limited peak current to GaN devices with much lower gate-voltage limits.
• Long gate and source traces that add shared inductance, causing V_GS ringing and false turn-on at high dv/dt.
• Dead-time values copied from silicon designs, either eating away ZVS and efficiency or increasing shoot-through risk.

The goal of this page is to show how to select and use GaN driver ICs specifically for adapter power stages. It focuses on gate-drive amplitude and current, layout-aware design, dead-time execution and protection behavior around GaN FETs. Frequency modulation, control loops and digital power algorithms are handled on the dedicated pages for LLC resonant control and digital PSU controllers.

System context: where the GaN driver sits in an adapter

In a modern AC-DC adapter, power flows from the AC inlet through EMI filtering and protection into a PFC stage, then onto a regulated high-voltage DC bus. From there, an LLC or active half-bridge or full-bridge converts the bus into an isolated output, followed by secondary rectification and downstream regulation for USB-C or other DC rails.

GaN devices most often appear in:

• Totem-pole PFC legs as high-side and low-side switches handling high dv/dt at the AC front-end.
• LLC half-bridge or full-bridge stages that drive the isolation transformer for high-density adapters.
• Occasional secondary-side synchronous rectification in very high current or ultra-high-efficiency designs.

The controller or digital PSU device decides when each leg should switch by generating PWM signals, managing control loops and supervising operating modes. The GaN driver sits between this controller and each GaN FET, providing the actual gate current and voltage, level shifting or isolation, precise dead-time execution and fast protection.

Generic isolated gate drivers or legacy MOSFET drivers may look pin-compatible, but they are not necessarily designed for GaN gate-voltage limits, dv/dt levels and short-circuit dynamics in adapter power stages. This page focuses on GaN-ready drivers for PFC and LLC stages, while keeping control algorithms and digital telemetry on the dedicated controller pages.

Switching-node stress & parasitics for GaN in adapters

In GaN-based adapter stages, the switching node operates under much harsher conditions than in traditional silicon designs. Switching frequencies often sit in the 100–300 kHz range and edge rates can reach 50–150 V/ns, so every nanohenry of loop inductance becomes a visible voltage error or ringing source.

The high-side device sees its source or Kelvin source bouncing at high frequency with the switching node. Any shared source inductance between the power loop and the gate-return path converts fast di/dt into an additional voltage across that inductance, effectively modulating the real gate-source voltage seen by the GaN FET during turn-on and turn-off.

Three coupled loops dominate the behavior around the switching node:

• A gate loop running from the GaN driver output through the gate terminal and back via the source or Kelvin source.
• A power loop that carries the main bridge current between high-side and low-side devices, the transformer or inductor, and the DC bus rails.
• A source return path that may share inductance with the power loop when the driver ground is not tied to a true Kelvin source.

When the gate loop is long and has significant inductance, the GaN gate voltage develops overshoot and undershoot ringing at each transition. Large shared source inductance pulls the effective gate-source voltage away from the intended drive level, so switching speed and timing are no longer under precise control. Fast dv/dt and di/dt also couple into sense, protection and controller lines, creating false turn-on events and nuisance trips if the design is not hardened.

For GaN adapter stages, the gate driver must therefore be co-designed with the layout and GaN package to keep loop inductances low, use a proper Kelvin source reference and tolerate the dv/dt and di/dt stress at the switching node.

Gate-drive requirements: GaN vs silicon MOSFET

GaN devices do not share the same gate-drive expectations as traditional silicon MOSFETs. The gate-voltage window is narrower, the transfer characteristic is steeper and the target switching speed is higher, so the driver must be selected and configured with GaN-specific limits in mind rather than reused from an older silicon design.

For many enhancement-mode GaN FETs, the recommended gate-drive level is around 5–6 V with a very tight absolute maximum rating. Overshoot that would be benign at 10–12 V for a silicon MOSFET can quickly push a GaN gate beyond its rating. At the same time, the steep transfer curve means that small disturbances in gate-source voltage can move the device between off, linear and fully on states.

Several parameter dimensions define whether a driver is truly GaN-ready:

• Drive voltage range: support for 5–6 V gate levels, optional negative turn-off such as −2 V, and tight control of overshoot and undershoot.
• Peak gate current: ampere-level source and sink capability to charge and discharge GaN gate charge within tens of nanoseconds.
• Propagation delay and matching: low and well-matched delays between high-side and low-side outputs so that dead-time stays within the intended window over operating conditions.
• CMTI capability: high common-mode transient immunity, especially for high-side outputs that ride on fast dv/dt switching nodes in totem-pole PFC and resonant bridges.

Common gate-drive techniques help align the system with these requirements. Separate turn-on and turn-off resistors allow dv/dt and turn-off speed to be tuned independently. Miller clamp functions hold the gate close to reference during fast dv/dt events, limiting false turn-on through C_gd coupling. A true Kelvin source connection for the driver reference keeps the gate loop separate from the high di/dt power return path.

Together, these driver capabilities and connection techniques differentiate a GaN-optimized gate driver from a generic MOSFET driver and are essential to gain the efficiency and density benefits promised by GaN in adapter power stages.

Lead-inductance compensation & co-design with layout and package

Gate-drive quality in GaN adapter stages is set as much by physical geometry as by datasheet parameters. The driver package, GaN package and PCB layout combine into one effective gate loop and source return path. Any extra millimeters of trace length or poorly chosen reference connections add inductance that directly interacts with the high dv/dt and di/dt at the switching node.

Keeping the driver as close as practical to the GaN devices reduces gate-loop inductance and shrinks the area over which switching currents can couple into control signals. Separating gate and power loops prevents high di/dt currents from sharing long segments with the sensitive gate-return path. A true Kelvin source connection for the driver ground further isolates the gate loop from the large, fast-changing power return currents in the half-bridge.

At the IC level, many GaN drivers offer tools to compensate for unavoidable inductance. Programmable gate current or slew-rate control allows edge speed and dv/dt to be adjusted in discrete steps. Internal series resistance or current-source style drivers shape the turn-on and turn-off transitions without relying only on external gate resistors. Pinouts optimized for DFN, QFN, LGA or integrated GaN+driver packages reduce internal loop length and place gate, source and driver pins to support tight external layouts.

During architecture selection, several checkpoints help decide when integration is needed. Compact, high power-density adapters and server supplies with constrained routing often benefit from integrated GaN+driver devices or tightly paired reference layouts. Designs with more PCB freedom and GaN experience can use discrete GaN FETs plus dedicated drivers to optimize cost and flexibility, provided that dv/dt and gate-loop constraints are still respected.

When layout limitations make it hard to control parasitics, selecting drivers with adjustable slew rate, strong Miller clamp capability and Kelvin-friendly pinouts is often more effective than continuing to push generic drivers into unsuitable geometries.

Dead-time tuning for efficiency and reliability

Dead-time is the interval during which both devices in a half-bridge are intentionally held off to prevent shoot-through. In resonant and soft-switching topologies, this interval is also the time budget that allows the resonant or magnetizing current to commutate the switching node voltage and achieve zero-voltage switching for the next transition.

If dead-time is too short, the switching node does not fully complete the transition before the opposite device turns on, so the two devices briefly conduct together and create shoot-through current spikes. If dead-time is too long, the current continues to flow through body-diode or synchronous paths for an extended period, wasting energy and eroding the soft-switching benefit at high frequency.

GaN devices narrow the usable dead-time window. Faster turn-on and turn-off allow shorter optimal dead-times, but also make propagation delay, temperature drift and device-to-device variation a larger fraction of the total budget. At switching frequencies in the 100–300 kHz range, a few nanoseconds of excess or deficit in dead-time can accumulate into measurable efficiency loss or even stability issues in adapter and server supplies.

Adapter designs are particularly sensitive at light load. Resonant and LLC stages rely on load and magnetizing current to bring the switching node fully to the next rail during the dead-time interval. When load current is low, the commutation may stall mid-way, so dead-time values that worked well at high load can lead to incomplete ZVS, distorted waveforms and increased switching loss at light load.

Some controllers and GaN drivers support adaptive dead-time, using voltage or current feedback to trim timing as operating conditions change. This can help maintain ZVS over a wide load range, but still requires careful validation on the bench to confirm behavior across temperature, line and component spread.

Practical tuning relies on observing upper and lower gate signals together with the switching-node waveform. Dead-time that is too short shows overlapping gate conduction and sharp V_sw spikes, while excessive dead-time appears as long diode conduction intervals and non-zero-voltage turn-on. GaN drivers and controllers that expose dead-time pins or configuration registers make it possible to iterate toward a setting that balances safety margin and efficiency for each adapter design.

Gate protection, fault handling and robustness

In GaN-based adapters, the gate driver is responsible not only for fast and precise switching, but also for protecting the devices and the system when operating conditions go out of bounds. Protection and fault-handling functions must react on nanosecond time scales and remain immune to the high dv/dt and di/dt that are present around the switching node.

Core protections for GaN gate drivers

A robust GaN gate driver in an adapter design typically includes several core protection layers:

• Under-voltage lockout (UVLO): when the driver supply falls below a defined threshold, both high-side and low-side outputs are forced off so that the GaN gate never sits in a half-on region during supply brownout or startup transients.
• Short-circuit and over-current detection: detection via source sense resistors, current transformers or DESAT-style drain/collector voltage monitoring must operate within tens of nanoseconds to keep GaN devices within their short-circuit safe operating area.
• Over-temperature protection: on-die temperature monitors can shut down the driver when its junction exceeds a safe limit, and the driver can also participate in system-level derating based on external temperature sensors near hot GaN stages.
• Over-voltage protection: gate-drive stages limit V_GS to within the recommended range for GaN devices, while system-level supervision monitors bus and switch-node voltages to prevent sustained over-stress on V_DS.

Fault response strategies

Once a fault is detected, the GaN driver must shut down the gate quickly and communicate the event to the higher-level controller. Typical response strategies include:

• Latched shutdown: the driver immediately turns off the affected gate outputs and latches the fault state until the system issues a reset command or power is cycled. This approach suits high-reliability supplies where automatic restart after a serious fault is not desirable.
• Current limiting and hiccup restart: for adapter and charger designs, a combination of fast gate turn-off, limited retry duty cycle and hiccup-style restart allows the system to survive repeated output shorts while avoiding excessive average dissipation.
• FAULT and PG signaling to the controller: dedicated pins signal fault and power-good status to a digital controller, which can shut down PWM outputs, log the event and decide whether to attempt recovery based on system policy.

Immunity to dv/dt and layout-induced false trips

Protection circuits in GaN drivers operate in close proximity to switching nodes that move at 50–150 V/ns. High common-mode transient immunity (CMTI) is mandatory, especially for high-side channels in totem-pole PFC and LLC half-bridges. Poor routing of DESAT lines, FAULT/PG traces or ground references can turn dv/dt events into spurious trips that look like intermittent hardware faults.

Clean Kelvin source connections for the driver ground, short and shielded paths for sense signals and careful partitioning of quiet and noisy ground regions all contribute to making real protection thresholds predictable and repeatable, even under worst-case line and load transients.

Example driver and GaN module families with protection features

Several device families illustrate how protection, fault handling and robustness are combined for adapter-class GaN stages. The exact feature set varies by part number, so each design should still be verified against the latest datasheet:

• GaN FET + driver modules: families such as LMG341xR0x and LMG3522R030 integrate a GaN power stage with a dedicated driver, UVLO, over-temperature protection and fault reporting for high-density adapter and server supplies.
• High-side/low-side GaN-capable drivers: half-bridge drivers such as UCC27282, NCP51820 or 1EDxxxx-series devices provide high CMTI, UVLO and fast gate-drive capability suitable for LLC or totem-pole stages, with variants that support DESAT or external over-current sensing.
• Isolated drivers for noisy or high-insulation domains: digital-isolated drivers such as Si827x or 1EDi-EiceDRIVER families combine high isolation ratings with high CMTI and configurable fault-handling behavior for demanding industrial or server PSUs.

These examples are reference points for feature combinations rather than fixed recommendations. Final device selection should match short-circuit withstand time, CMTI and protection timing to the specific GaN FETs and adapter topology in use.

Design checklist & GaN driver IC roles mapping

Selecting a GaN gate driver for an adapter or server supply starts with clarifying the electrical environment and system goals, then mapping those requirements onto the appropriate driver type. A structured checklist reduces the risk of overlooking constraints that later become layout or reliability problems.

System and driver selection checklist

• Bus and switch-node voltage range: what are the nominal and maximum values for the PFC bus and GaN V_DS? These determine insulation requirements, driver voltage ratings and topology limits.
• Switching frequency and efficiency targets: is the design closer to a 65 W phone charger or a 300–1000 W server PSU? Higher frequency and tighter efficiency goals drive higher demands on dead-time control, dv/dt management and driver loss.
• Topology and switching regime: half-bridge, full-bridge, totem-pole PFC or other structures, with hard switching, ZVS or quasi-resonant operation. This defines whether high-side drive is required and how wide the dead-time adjustment range must be.
• Layout space and GaN packaging: does the PCB allow a clean, compact gate loop for discrete GaN FETs and drivers, or is the layout so constrained that integrated GaN modules are a better fit?
• Isolation and safety requirements: which insulation standards and test voltages apply between primary and secondary or between control and power domains? This drives the choice between non-isolated, high-side, isolated or fully integrated gate-driver solutions.
• Short-circuit and fault withstand: what short-circuit I²t and fault duration must the system tolerate before shutdown? Driver short-circuit detection delay, CMTI and protection thresholds must be aligned with the GaN safe operating area.

From these system answers, the GaN driver requirements can be summarized: needed protection functions, peak gate current, adjustable dv/dt, dead-time control, isolation level, CMTI and tolerance to layout parasitics. These requirements form the basis for mapping the design to specific driver roles.

GaN driver IC roles in adapter and PSU architectures

Different GaN driver types address different positions in the powertrain. The mapping below keeps the focus on roles rather than specific vendors.

• Non-isolated low-side GaN driver: used for secondary-side synchronous rectifiers and small single-ended stages. Key dimensions are 5–6 V gate drive, high peak gate current and options such as Miller clamp and split turn-on/turn-off gate resistors.
• Half-bridge or high-side GaN driver (bootstrap or isolated supply): targeted at LLC, AHB, full-bridge and totem-pole PFC stages where both high-side and low-side gates must be driven. High CMTI, matched propagation delay, accurate dead-time and support for over-current sensing are critical.
• Isolated GaN driver: used when insulation and noise immunity requirements dominate, such as in industrial, server or medically rated supplies. Isolation voltage, CMTI, propagation delay and jitter across temperature are primary selection criteria.
• Integrated GaN FET + driver module: combines the GaN power stage with a dedicated driver and internal protection. This option is attractive when PCB area is tight, layout experience with high-speed GaN is limited, or time-to-market is a key driver.

BOM hooks for GaN driver robustness

To prevent apparently pin-compatible but functionally weaker drivers from entering the supply chain, critical GaN-specific requirements should be called out explicitly on the bill of materials and design documentation:

• Integrated or external Miller clamp capability for the intended high-side and low-side gate voltage ranges.
• Adjustable dv/dt or configurable gate-drive strength to match layout parasitics and EMI limits.
• Short-circuit detection and gate turn-off delay no greater than a specified value (for example, tens of nanoseconds for the chosen GaN FETs and bus voltage).
• CMTI rating that meets or exceeds the worst-case dv/dt expected at the switching node, with margin for process and layout variation.

Pin-to-pin compatible drivers that do not meet these conditions can behave correctly in silicon-based designs, yet fail in GaN adapters due to faster edges and narrower protection margins.

Frequently Asked Questions about GaN Driver Selection and Design

When do adapter designs really need a dedicated GaN driver instead of reusing a Si MOSFET driver?

A dedicated GaN driver is necessary when the frequency and switching speed exceed the capabilities of Si MOSFET drivers. GaN devices require faster gate driving and handling higher dv/dt, which Si MOSFET drivers can’t manage effectively.

How much gate-loop inductance is acceptable for high-frequency GaN stages in adapters?

Gate-loop inductance should be kept as low as possible, ideally in the range of a few nano-henries. High inductance can lead to ringing and overshoot in gate voltage, causing inefficient switching and potential damage to GaN devices.

Should GaN gates in offline adapters be driven with negative turn-off voltage?

Yes, driving GaN gates with a negative turn-off voltage can improve efficiency and reduce switching losses. It ensures faster turn-off, minimizes gate voltage overshoot, and prevents excessive ringing.

How do you tune dead-time for a GaN LLC half-bridge without losing ZVS?

To tune dead-time without losing ZVS, adjust it to ensure the switching node voltage reaches the appropriate rail before the next transistor turns on. Fine-tuning dead-time using gate and Vds waveforms ensures ZVS is maintained across all load conditions.

What are the key considerations when selecting a GaN driver for high-power adapters?

When selecting a GaN driver for high-power adapters, consider the following key factors: gate voltage requirements, switching frequency, and efficiency goals. Ensure that the driver can handle high peak gate currents and support fast switching speeds without causing excessive heat.

How do you handle gate-loop parasitics in GaN adapter designs?

To handle gate-loop parasitics in GaN adapter designs, keep the gate-loop trace as short and wide as possible, minimizing parasitic inductance. Use Kelvin source connections and separate the gate loop from the power loop to prevent coupling.

What is the impact of switching frequency on GaN driver selection?

The switching frequency impacts GaN driver selection by requiring faster gate switching and handling of higher peak currents. The driver should maintain efficient switching at these high frequencies, ensuring minimal loss and optimal thermal management.

How do you optimize efficiency in low-load conditions for GaN drivers?

To optimize efficiency in low-load conditions, techniques like adaptive dead-time, frequency modulation, and adjusting gate drive strength can help maintain ZVS and reduce losses when the load is low.

What are the challenges of integrating GaN drivers into server PSUs?

Integrating GaN drivers into server PSUs presents challenges such as high power density, thermal management, and ensuring reliability under varying load conditions. GaN devices have a higher switching speed, which can introduce noise and require careful layout to minimize parasitics.