This page focuses on the design and selection of PFC controllers for CCM, CRM and Totem-Pole stages in AC-DC systems such as adapters, server PSUs, EV on-board chargers and LED drivers. The goal is to translate power-factor and harmonic requirements into a robust controller choice and signal chain, rather than treating PFC as a black box.

Modern AC-DC front ends must comply with harmonic standards such as EN 61000-3-2, limit THD and keep power factor close to unity. A well-designed PFC stage also reduces RMS input current, lightens thermal and wiring stress, and makes EMI compliance easier by shaping the input current waveform instead of letting narrow, high peaks flow from the rectifier into the mains.

The content here concentrates on the PFC controller itself: multiplier, current and voltage sense paths, ZCD or valley-detect networks, gate-drive hooks and protection behavior across CCM, CRM and Totem-Pole architectures. The emphasis is on how these blocks interact with line and load conditions, and how they influence efficiency, THD, start-up and fault handling in real products.

Several closely related topics are intentionally covered in dedicated pages:

• AC input protection, inrush control, X/Y capacitors, common-mode and differential-mode filtering, and the bridge rectifier live in AC Input & EMI Front-End.
• Downstream DC-DC conversion from the high-voltage bus, including primary-side flyback, LLC resonant stages and active-bridge architectures, is treated in Primary-Side Flyback, LLC Resonant Half-Bridge and Active Bridge / Bridgeless.
• Detailed GaN gate-drive behavior, dead-time tuning and high-CMTI isolation for Totem-Pole and other GaN stages is covered in GaN Driver for Adapters.
• Generic current and voltage sensing front-ends, ΣΔ modulators, precision references and bias rails are developed in Current/Voltage Sensing and References & Bias. This page only references the portions that directly feed PFC controller pins.

By keeping these boundaries clear, this page can drill deeply into PFC-specific control and sensing decisions while other pages handle EMI filtering, downstream conversion, gate-driver details and generic analog front-ends.

In a typical universal-input AC-DC system, the PFC stage sits between the rectified output of the EMI and bridge front-end and the high-voltage DC bus that feeds one or more downstream DC-DC stages. The path runs from the AC inlet, through EMI filtering and surge protection, into the bridge rectifier, then through a boost or Totem-Pole PFC stage, and finally into a 380–420 V DC bus that supplies LLC, flyback or active-bridge converters.

Most designs target 90–264 VAC for worldwide operation, with some industrial or commercial supplies extending this range toward 85–305 VAC. Lower line input increases input current and stresses the PFC inductor, switch and current sense path, while high line defines the peak bus voltage and device voltage margins. Against this background, the PFC controller must keep power factor high, THD low and bus voltage within a narrow operating window under both low-line and high-line conditions.

The regulated bus typically sits around 380–420 V to balance downstream converter efficiency, magnetics size and device stress. A lower bus eases switching loss and conduction loss in some topologies but forces higher secondary currents and larger magnetics, while a higher bus improves hold-up time and margin for brown-out but raises voltage stress and insulation requirements. The PFC controller continuously modulates duty cycle or switching frequency so that the average bus voltage tracks its target in the presence of mains and load variations.

Different PFC operating modes align with different power bands and form factors. CRM or transition-mode PFC is common in the tens to a few hundreds of watts where single-switch architectures and valley switching balance cost and efficiency. CCM PFC, often with interleaving, dominates in the hundreds of watts to low kilowatt range found in server and telecom PSUs. Totem-Pole PFC with fast silicon or GaN switches becomes attractive for high-efficiency, high-density kilowatt-class supplies such as server PSUs and EV on-board chargers.

At the interface level, the PFC block draws rectified current from the EMI and bridge front-end, shapes it according to the mains waveform, and delivers controlled power into the DC bus capacitors. The controller senses the rectified line, bus voltage and inductor current, then drives the PFC switch or switches through local or external gate drivers. Status and protection signals such as PFC_OK, OVP, brown-in/brown-out and over-current flags can be exported to a digital PSU controller or system MCU, which coordinates PFC start-up, downstream DC-DC enable and fault logging.

By treating the PFC stage as a well-defined block between rectified AC and the high-voltage DC bus, the design process can allocate realistic voltage, current and thermal budgets to the EMI front-end, PFC magnetics and downstream converters, and select a controller whose sensing, drive and protection features match the intended power level and mode of operation.

PFC stages in adapters, server PSUs, telecom rectifiers and EV on-board chargers are usually implemented in continuous-conduction mode (CCM) boost, transition-mode CRM/TM, or Totem-Pole architectures. Each approach shapes the inductor current, switching loss and EMI spectrum in a different way, and therefore drives specific requirements on the controller and gate-drive scheme.

In CCM PFC, the inductor current remains continuous over the switching cycle, with ripple superimposed on a relatively high average level. This mode is favored at higher power levels because it reduces peak current, enables interleaving and maintains low input current distortion. The price is higher switching loss, more demanding loop compensation and tighter EMI control, especially when several phases operate in parallel to reach kilowatt power levels.

CRM or transition-mode PFC forces the inductor current to return to zero every switching cycle. Zero-current or valley turn-on can significantly reduce turn-on loss and allow high efficiency in the 50–300 W range and above, which fits LED drivers and small to medium adapters well. However, the variable switching frequency spreads the EMI spectrum and shifts with line and load, and the design becomes very sensitive to accurate zero-current detection and to noise on the auxiliary winding or sense network used for ZCD and valley-detect functions.

Totem-Pole PFC replaces the traditional diode bridge with an active bridge built from two or four FETs. In high-efficiency server PSUs and EV on-board chargers, this architecture avoids the bridge rectifier loss, unlocks higher system efficiency and supports very high power density. In return, the implementation requires multi-device gate-drive coordination, accurate dead-time control, robust handling of reverse current, and often the use of fast silicon or GaN devices with high dv/dt and strict layout constraints.

When comparing modes, several dimensions matter simultaneously. Efficiency and switching loss favor valley-switched CRM/TM and Totem-Pole PFC at moderate and high power, while CCM PFC remains attractive where mature multi-phase implementations and fixed-frequency EMI optimization are important. EMI behavior differs as well: CRM/TM spreads energy over a wide frequency range because of variable switching frequency, CCM concentrates noise around fixed harmonics, and Totem-Pole magnifies sensitivity to layout and common-mode currents because of fast, high-amplitude switching transitions at the bridge.

Controller complexity also changes across modes. Efficient CCM implementations depend on strong current-mode control, slope compensation and often multi-phase current balancing. CRM controllers must integrate robust zero-current or valley detection, effective light-load strategies and protection against false triggering. Totem-Pole controllers frequently require dual or quad gate drive paths, precise timing control and in many high-end designs, digital co-processing or full digital control to coordinate modulation, dead-time and protection.

Typical application patterns reflect these trade-offs. LED drivers and small adapters in the tens to a few hundreds of watts commonly rely on CRM or transition mode. Server PSUs and telecom rectifiers in the hundreds of watts to low kilowatt range tend to favor interleaved CCM PFC with well-understood EMI and control techniques. Above roughly 3 kW, especially in EV on-board chargers and premium server supplies, Totem-Pole PFC with GaN devices often becomes the preferred choice to meet aggressive efficiency and power-density targets.

A PFC controller can be viewed as a set of functional blocks that translate mains and bus information into gate-drive signals for the power stage. Line and bus voltages are sensed and fed to a multiplier and error amplifier, which produce a current reference that is compared against the sensed inductor current. A PWM or valley detect block then determines when to switch the PFC device on and off, while integrated protection and housekeeping logic supervise brown-in, brown-out, over voltage and over current behavior.

The AC line sense input monitors the rectified mains waveform and often provides feed-forward information to normalize the current reference across line conditions. The bus voltage sense input (VSENSE) monitors the 380–420 V DC bus through a resistor divider, enabling the internal error amplifier and over-voltage protection comparator. Proper selection of divider ratios, filtering and clamping is critical to keep sense pins within their specified ranges and to limit noise coupling from the high-voltage bus into the controller.

Inside the controller, the multiplier combines the bus voltage error information from the error amplifier with the line sense waveform. The result is a current reference that is proportional to the instantaneous line voltage while reflecting the desired power level. Multiplier linearity and dynamic range directly influence power factor and THD, especially at low line or near the edges of the input range where the line voltage is small and the stage must still track the mains shape accurately without clipping or distortion.

The current sense pin (CS) receives a scaled representation of inductor or switch current, typically through a shunt resistor and small RC filter. In CCM controllers, this signal participates both in the inner current loop and in over current protection, with slope compensation added internally or externally to prevent subharmonic oscillation at high duty cycles. In CRM and transition-mode controllers, the CS pin usually senses peak current and cooperates with zero-current or valley detection logic, which decides the next turn-on instant once the inductor current has decayed to zero or to a defined valley.

The error amplifier compares the sensed bus voltage to an internal reference and outputs a control voltage on the COMP pin. This node hosts the compensation network that shapes the outer voltage loop. Appropriate gain and phase margin at twice-line ripple frequencies and under load steps are essential to avoid sluggish bus recovery or oscillation. COMP voltage also acts as a power-command input to the multiplier, so its operating range must fit the multiplier transfer characteristics and the expected power level of the supply.

A PWM or valley detect block then compares the current sense signal against the current reference derived from the multiplier and COMP. In fixed-frequency CCM controllers, the comparison defines the turn-off instant within each cycle while a clock defines turn-on. In CRM controllers, zero-current or valley detection circuitry triggers the next turn-on and the controller supervises that peak current and power limits are respected. Valley-detect behavior, maximum and minimum on-time and any internal blanking intervals therefore become important data-sheet parameters when evaluating a controller for a given topology and power range.

The gate-drive stage converts the control decisions into gate-voltage waveforms for the PFC MOSFETs or GaN devices, either directly or through an external driver. Drive voltage level, peak source and sink current, and dv/dt robustness must be aligned with the target switches and power level. In Totem-Pole and high-power interleaved designs, multi-channel gate-drive capability and tight timing control are often necessary, along with careful consideration of common-mode transients and Miller coupling.

Around this main signal chain, auxiliary blocks supervise brown-in and brown-out thresholds, bus over voltage protection, over current protection, thermal behavior and PFC_OK or VIN_OK status reporting. When reviewing a PFC controller data sheet, particular attention is typically paid to multiplier linearity, error amplifier characteristics, CS pin range and noise immunity, gate-drive capability and the detailed timing and thresholds of the protection functions, because these parameters collectively determine how well the controller will support the intended PFC mode and power level.

Gate-drive capability is a key link between a PFC controller and the power devices that actually shape current. In a single boost PFC stage, the switch is usually a ground-referenced MOSFET that can be driven directly by the controller’s built-in gate driver, as long as gate voltage level, peak source and sink current and Miller-effect immunity are aligned with the device and power level. As output power, switching frequency and device gate charge increase, the internal driver may become the limiting factor for efficiency, switching losses and EMI.

For single-phase boost PFC, designers typically check gate-drive peak current, recommended gate voltage and the data-sheet waveforms before deciding to rely on the internal driver. Adequate drive current is needed to charge and discharge the MOSFET gate charge quickly enough to keep turn-on and turn-off losses under control. Sufficient sink capability and low effective impedance on the off transition help hold the gate low in the presence of Miller current, especially when drain dv/dt is high and layout parasitics are non-ideal. If these conditions are not met, external drivers or split gate resistors are usually required.

Interleaved PFC architectures add further demands. Multiple phases operate with phase-shifted gate signals and overlapping current waveforms, which can push aggregate gate-drive requirements beyond what a monolithic controller can supply. Some controllers integrate two or more gate outputs and manage phase shift and current balancing internally, while others expect a digital controller to generate phase-shifted PWMs and use dedicated multi-channel gate-driver ICs. In either case, each phase must have enough gate-drive strength and clean reference to avoid skewed current sharing or excessive switching overlap that erodes efficiency and thermal margins.

In higher-power or higher-density designs, external gate drivers often become necessary for interleaved PFC stages. External drivers allow higher peak drive currents, better control over turn-on and turn-off speed, and more flexibility in placing drivers physically close to MOSFETs to reduce loop inductance and ringing. They also help isolate the controller IC from the large dv/dt and di/dt present at the switch node, which improves robustness and can reduce spurious triggering of sensitive sensing pins and comparators inside the PFC controller.

Totem-Pole PFC brings the tightest coupling between gate drive and device physics. Replacing the diode bridge with an active FET bridge significantly reduces conduction losses but requires precise timing, dead-time control and strong immunity against high dv/dt and common-mode transients. Many Totem-Pole designs use fast silicon or GaN devices, and therefore rely on half-bridge or full-bridge drivers or on GaN-specialized drivers that provide appropriate gate voltage levels, Miller clamps and high common-mode transient immunity. The PFC controller must therefore provide clean logic-level gate commands, often with dead-time control integrated, and a clear interface to these external drivers.

As a practical rule, external gate drivers are usually required when device gate charge and target switching frequency demand more current than the controller’s gate driver can safely deliver, when gate traces become long or must cross noisy regions, when per-phase turn-on and turn-off speed must be tuned individually, or when Totem-Pole and GaN architectures introduce high dv/dt and strict CMTI requirements. Evaluating gate-drive peak current, drive voltage, Miller immunity features and the thermal impact of gate-charge losses in the controller IC helps avoid underestimating the importance of a dedicated driver stage.

Zero-current detection (ZCD) and valley detection are central to transition-mode and many Totem-Pole PFC controllers. A well-designed ZCD network detects when inductor current has decayed to zero, or when the switch-node voltage reaches a valley, and allows the controller to initiate the next turn-on with reduced switching loss. The same network must also survive high-voltage transients, reject noise and behave predictably at low line, high line and light-load conditions.

In most designs, the ZCD pin is driven by an auxiliary winding or sense network on the PFC inductor or transformer. The auxiliary winding reproduces the switch-node voltage and, through an RCD and divider network, presents a waveform to the ZCD pin that swings around a defined threshold. The internal comparator then detects either the zero-current point, where the inductor current crosses zero, or one of the subsequent valleys in the resonant ringing between the inductor and stray capacitances. Ensuring that this waveform reliably crosses the comparator thresholds without overstressing the pin is the primary design challenge.

Threshold and current conditions at the ZCD pin set the first boundary. The auxiliary winding voltage at low and high line, combined with the winding ratio and the RCD network, determines the peak and valley levels at the pin. The series resistor into the ZCD pin must be large enough to limit pin current under worst-case line and transient conditions, yet small enough that the ZCD waveform still slews quickly across the comparator thresholds. Designers typically calculate the worst case auxiliary voltage at maximum line and apply the series resistor sizing rules given in the controller data sheet to stay within maximum pin current ratings.

Noise filtering and blanking then shape how robustly the ZCD pin behaves in the presence of spikes and ringing. Many controllers include a small internal blanking interval after turn-off to ignore leading-edge spikes, but that interval is usually not sufficient on its own. A small RC filter close to the ZCD pin can tame very fast edges and damp high-frequency noise, but excessive filtering introduces delay and distorts the valley or zero-crossing timing. The goal is to attenuate sharp spikes enough to avoid false triggers, while preserving the underlying waveform amplitude and timing margin across the full range of operating conditions.

At low line, auxiliary amplitude is smaller and the noise and spike content can become a significant fraction of the ZCD signal. If the network is too sensitive, noise can be misinterpreted as a zero-current crossing, causing premature turn-on and pushing the converter toward unintended continuous conduction with rising current levels. At high line, the auxiliary waveform is much larger and slews faster, which increases the risk of pin overcurrent or multiple threshold crossings in a single half-cycle. Both extremes must be considered when choosing the winding ratio, series resistor values, clamp components and RC networks around the ZCD pin.

Light-load and standby conditions deserve particular attention. When active power transfer is low, the energy in the inductor is small and resonant ringing of the switch node often dominates the auxiliary waveform. If the controller continues to rely solely on ZCD and valley detection, random noise or minor ringing may trigger excessive switching at very light load and severely degrade efficiency. Many PFC controllers therefore incorporate special light-load modes or skip-cycle behavior, and the ZCD network must be designed to cooperate with these modes so that unwanted toggling around the ZCD threshold does not keep the converter in a high-frequency regime during standby.

Common mistakes include using a series resistor that is too small, which can expose the ZCD pin to excessive current at high line or during transients, choosing an RC network that damps the waveform so aggressively that valley points are lost, or ignoring how the network behaves at very light load, where ZCD behavior can dominate standby losses. A disciplined design process checks ZCD pin voltage and current across line and load corners, validates noise immunity and blanking against measured waveforms, and confirms that zero-current and valley detection still function correctly under realistic parasitic and layout conditions.

PFC current sensing is more than a single shunt resistor. The topology of the sense element, the shape of the current waveform and the way the CS pin is protected and conditioned together determine protection accuracy, loop stability and EMI behavior. In a typical boost PFC stage, current is sensed either in a low-side shunt between the MOSFET source and ground or in a high-side shunt followed by an amplifier. The CS pin then receives a filtered, scaled representation of the inductor or switch current that feeds the inner current loop and over-current protection comparators.

A low-side shunt is the most common choice for PFC stages because it is ground referenced and simple to connect to a current-mode controller. The CS pin sees a waveform consisting of the inductor current plus switching spikes, with continuous triangular ripple in CCM and more pulse-like ramps in CRM or transition mode. This topology is cost-effective and easy to route, but ground bounce and switching noise couple directly into the sense signal, so layout and RC filtering must be treated carefully. High-side shunt schemes instead rely on a differential amplifier or current-sense IC and present a cleaner, level-shifted waveform to the CS pin at the cost of additional delay and complexity, which must be taken into account when assessing protection response and slope compensation accuracy.

The distinction between CCM and CRM waveforms is important for CS network design. In CCM, the inductor current never returns fully to zero during normal operation, and the CS pin observes a nearly continuous triangular waveform plus leading-edge spikes. This encourages fixed-frequency EMI behavior but raises peak current at high duty cycles and requires proper slope compensation to avoid subharmonic oscillations. In CRM or transition-mode PFC, each switching cycle starts at zero and ramps up to a peak current before returning to zero, producing distinct pulses whose height and repetition rate vary with line voltage and load. In this case, the CS network must preserve the narrow peak information while still filtering switching spikes, which limits how aggressive RC filtering can be.

Around the CS pin, three mechanisms work together to protect the controller and maintain accurate current information: leading-edge blanking, external RC filtering and slope compensation. Leading-edge blanking inside the controller masks the first tens of nanoseconds after the MOSFET turns on, preventing the current comparator from reacting to gate-charge and diode-recovery spikes. An external series resistor and small capacitor to ground then form a simple low-pass filter that attenuates high-frequency components while limiting CS pin current. The RC time constant must be chosen so the useful portion of the current waveform remains largely intact; over-filtering will distort CCM triangular peaks and can flatten CRM pulses into unusable shapes.

In CCM designs, slope compensation is added to the CS path or internally to the current comparator. This artificial ramp counteracts the tendency of current-mode control to oscillate at duty cycles above 50 % and allows stable operation over the full line and load range. Data sheets typically state the internal slope magnitude or provide equations for setting an external slope, along with recommended inductance and duty-cycle ranges. Ensuring that the slope is sufficient for the chosen inductance and maximum duty cycle is an important step when reviewing a PFC controller for high-power CCM operation.

Protection functions build on these sensing and conditioning circuits. Over-current protection (OCP) commonly uses a separate comparator at the CS pin with a fixed threshold, while over-power protection (OPP) combines CS, line sense and multiplier outputs to limit average power over a line cycle. Bus over-voltage protection (OVP) relies on the bus sense input detecting when the 380–420 V DC bus exceeds a defined threshold, reducing duty cycle or shutting down the PFC as needed. Brown-in and brown-out thresholds on line sense or HV pins ensure that the PFC starts only when the input voltage has risen above a safe level and shuts down gracefully before the line droops so low that the stage has to draw excessive current to maintain output power.

Line-cycle power limiting extends these protections to the time scale of the mains period. At low line, the RMS input current required to deliver rated output power increases significantly. If the PFC stage simply attempts to maintain constant output power, input components, magnetics and wiring may be overstressed. Many PFC controllers therefore implement line-cycle power limiting by shaping multiplier behavior or clamping the COMP voltage based on line sense, such that maximum power is reduced at very low line. A robust implementation verifies CS pin levels, protection thresholds and line-cycle limiting under low-line, high-line, overload and start-up transients, while leaving detailed device selection and precision sensing to the dedicated Current/Voltage Sensing subpage.

The interface between a PFC controller and a digital PSU controller determines how observability and programmability are implemented at the front end of an AC-DC system. Many designs use a purely analog PFC controller that regulates bus voltage and current locally, while a supervisory digital controller with PMBus or SMBus support monitors bus voltage, currents and temperatures and manages system-level functions. Other architectures adopt deeper digital co-processing where the PFC controller exposes internal multipliers, thresholds and loop parameters over UART, I²C, SPI or a dedicated serial interface, allowing an MCU to tune PFC behavior dynamically in the field.

In a classic analog PFC plus digital monitor arrangement, the PFC controller is responsible for all fast analog tasks: current-mode control, multiplier operation, zero-current detection, slope compensation and protection reactions. The digital PSU controller samples the 380–420 V bus, input and output currents and key temperatures through ADC inputs or dedicated sensing ICs and exposes this information via PMBus for system management. It can sequence rails, command fans, log faults and coordinate multiple PSUs in a shelf without directly modifying the inner PFC control law. The PFC controller, in turn, only needs to provide power-good and fault signals plus stable bus behavior, keeping the front end simple and robust.

Digital co-processing adds a second layer of flexibility. In this approach, the PFC controller offers a programmable interface so that parameters such as bus voltage setpoint, line-cycle power limit, current limit, soft-start ramp, or even multiplier gain and compensation coefficients can be adjusted by firmware. Some devices implement a register map accessible over I²C or SPI, while others act as fast analog front ends with comparators and drivers, leaving the modulation and loop calculations entirely to a digital controller. This allows a single hardware design to support multiple operating modes or power ratings by loading different parameter tables at production or in the field.

From a bill-of-materials perspective, fully programmable PFC behavior is most justified when multiple operating modes, remote updates or complex redundancy schemes are needed. Data center and telecom PSUs often need to switch between high-efficiency and high-power modes, derate individual units, and coordinate parallel modules under digital control. In such cases, the ability to adjust PFC bus voltage, maximum input power and recovery behavior via firmware can simplify hardware variants and enable field optimization. Likewise, designs that must evolve over time to meet new grid codes or efficiency regulations benefit from a PFC front end that can be retuned without changing the PCB.

For simpler adapters, LED drivers and many industrial supplies, a mature analog PFC controller with basic telemetry hooks is often sufficient. If the application does not require remote parameter changes, firmware updates or detailed PFC event logs, the additional cost and complexity of a digital co-processor can outweigh its benefits. In this case, it is usually adequate to select a PFC controller that exposes PFC_OK and FAULT signals and rely on the digital PSU controller only for coarse bus and current monitoring. More detailed discussion of PMBus command sets, multi-PWM generation and system-level telemetry is handled in the Digital PSU Controller (PMBus) subpage, while this section focuses on the interface expectations at the PFC stage itself.

1. Input conditions and regulatory targets

A PFC controller cannot be evaluated in isolation from its boundary conditions. Before comparing data sheets, the design should pin down line voltage range, frequency, power level, efficiency target and applicable harmonic standards. Typical single-phase systems operate from 90–264 VAC or 85–305 VAC at 47–63 Hz, while some industrial or three-phase inputs are derived from 400 VAC lines. The chosen topology and controller must support the lowest and highest line points without overstressing MOSFETs, inductors and input components.

Output power segments such as <150 W, 150–500 W, 500–1500 W and >3 kW guide whether CRM, interleaved CCM or Totem-Pole PFC is more appropriate. Efficiency objectives, for example 80 PLUS Gold, Platinum or Titanium for data-center supplies, further refine controller selection by driving the need for interleaving, Totem-Pole structures or GaN-optimized gate drives. Harmonic limits from EN/IEC 61000-3-2 and similar standards set a minimum power-factor and THD performance that the current loop and multiplier blocks must achieve with margin.

2. Topology decision: CCM, CRM or Totem-Pole

With input conditions defined, the next step is to decide whether the PFC stage will run in CRM/TM, CCM or a Totem-Pole architecture. CRM or transition-mode controllers are attractive for 50–300 W notebook adapters and LED drivers because valley switching reduces turn-on losses and allows compact magnetics, at the cost of variable switching frequency and a stronger dependency on accurate ZCD networks. Interleaved CCM controllers, typically used from several hundred watts up to about 2 kW, offer fixed-frequency behavior, simpler EMI filtering and straightforward phase-current sharing for server and telecom rectifiers.

At higher power and density levels, Totem-Pole PFC with SiC or GaN devices removes the input diode bridge and dramatically cuts conduction losses. Here the controller must natively support Totem-Pole gating schemes, dead-time control and high dv/dt immunity while still providing high-quality current shaping. A practical checklist therefore links power range, form-factor pressure and efficiency targets to a preferred topology and then filters controller options to those whose operating modes and protection structures are designed for that class of PFC stage.

3. Controller feature checklist

Once topology is chosen, the controller can be screened using a function-by-function checklist:

• Interleaving support: number of phases, internal phase-shift generation and current-sharing mechanisms for multi-kW CCM designs.
• Gate driver capability: integrated gate drivers must deliver enough source/sink current for the chosen MOSFET or GaN FET gate charge at the intended switching frequency; otherwise an external driver IC is needed.
• ZCD & valley detect quality: CRM controllers should specify ZCD thresholds, hysteresis and blanking times, and indicate whether multi-valley detection is available to support frequency-foldback strategies.
• Reference and sensing accuracy: internal reference tolerance and temperature drift directly influence bus regulation and harmonic performance, especially in high-end PSUs.
• Protection behavior: the data sheet should detail OCP/OPP, bus OVP and brown-in/brown-out thresholds, response times and whether faults trigger latch-off, hiccup or soft recovery.
• Frequency range and jitter options: supported switching-frequency span, availability of spread-spectrum or jittered operation and any constraints when pairing with EMI filter designs.

4. System integration with EMI front-end, DC/DC and digital control

A practical checklist also considers how the PFC controller connects to surrounding blocks. On the AC side, some controllers provide inrush relay drivers or bridge and X-cap discharge hooks and must be coordinated with the AC Input & EMI Front-End. On the DC side, PFC_OK or BUS_OK signals gate the downstream LLC or flyback stages so that DC/DC converters only start when the high-voltage bus is stable, and coordinated shutdown avoids stress on bulk capacitors and transformers during faults.

At the system level, digital PSU controllers or MCUs monitor bus voltage, currents and temperatures, implement PMBus communication and log events. The PFC controller should expose clear FAULT, WARN, remote enable and, when applicable, simple telemetry interfaces that can be isolated and routed cleanly on the PCB. Taking these signal hooks into account during selection prevents later compromises in sequencing, redundancy control and firmware-based derating strategies.

5. IC role mapping (role-based, brand agnostic)

Finally, candidate controllers can be grouped into recurring role types. An analog CCM PFC controller with integrated gate driver typically serves 500 W–2 kW interleaved boost stages in server and telecom PSUs, offering strong gate drive, slope compensation and line-cycle power limiting. A CRM controller with enhanced ZCD & valley detect targets 65–300 W adapters and LED drivers, where accurate ZCD behavior and valley switching are key to efficiency and acoustic performance.

A third role, the Totem-Pole PFC controller with GaN-optimized drivers, is oriented toward 1–3 kW high-density PSUs and EV on-board chargers. Such devices emphasize Totem-Pole-specific gating, precise dead-time control and robust protection around high-dv/dt nodes. In some architectures the PFC function is implemented as a digital PFC co-processor block inside a digital PSU controller, where a microcontroller or digital power controller generates PWM signals, reads currents and voltages and exposes PMBus registers. This role mapping allows designers to quickly shortlist analog and digital PFC options that match the chosen topology and system integration strategy.