What This Page Solves

This page explains how primary-side flyback controllers enable compact offline AC/DC power supplies in the roughly 5–75 W range, and how their operating modes, feedback options and standby techniques impact efficiency, no-load power, EMI and overall bill of materials.

Engineers comparing current-mode versus quasi-resonant (QR) flyback, deciding between primary-side regulation (PSR) and secondary-side regulation (SSR), or struggling to meet standby and EMI limits can use this page as a capability map for primary controllers rather than a generic flyback tutorial.

• Clarifies where primary-side flyback is the natural choice for offline adapters and auxiliary supplies.
• Shows how controller operating mode (current-mode, DCM, QR/valley switching) affects efficiency and EMI.
• Compares PSR and SSR feedback in terms of accuracy, cost and standby performance.
• Highlights controller features such as spread-spectrum, burst/skip-cycle and integrated HV startup that help pass modern energy-efficiency and EMI regulations.

What is not covered on this page

To keep the scope clear and avoid overlapping with sibling pages in the Power Supplies & Adapters tree, this page intentionally does not dive into:

• Synchronous rectification control — detailed gate timing, body-diode relief and light-load exit behavior belong to the Synchronous Rectification Controller page.
• LLC resonant half-bridge converters — medium-to-high power PFC + LLC stacks and their dedicated controllers are covered on the LLC Resonant Half-Bridge page.
• USB-C PD/QC/PPS protocol and cable management — PDO/AVS negotiation, cable authentication and sink/source roles live on the USB-C PD/QC/PPS Controller page.
• Secondary-side DC/DC and indicator rails — post-regulation LDOs, buck converters and I/O indicators are described on the Adapter Secondary Power page.
• PFC stages — front-end boost PFC (CCM/CRM/totem-pole), current shaping and power-factor requirements are covered on the PFC (CCM/CRM/Totem-Pole) page.

Layout, creepage/clearance and safety-standard details are handled by dedicated EMI, surge and safety pages. The focus here is squarely on choosing and applying primary-side flyback controllers.

Primary-Side Flyback Scope, Interfaces & Constraints

Scope: where primary flyback fits

Primary-side flyback controllers are typically used in offline AC/DC supplies from about 5 W up to roughly 75 W, with occasional designs extending toward 100 W when thermal and efficiency targets still allow a single-switch topology. Typical applications include phone and tablet adapters, router and set-top box supplies, small industrial control supplies and auxiliary rails inside larger systems.

• Input range is usually wide — 85–265 Vac for global mains compatibility.
• Outputs are often a single regulated DC rail (5 V, 9 V, 12 V or 24 V) plus a few small auxiliary rails.
• Target systems must meet modern energy-efficiency and no-load requirements without large, costly magnetics.

Multi-hundred-watt front ends, PFC + LLC stages for 80 PLUS server supplies, and multi-kilowatt motor drives fall outside this scope and are covered by dedicated high-power converter pages.

Key controller interfaces in the power train

A primary-side flyback controller sits at the heart of the offline stage and connects to a small set of critical nodes that define protection, regulation and EMI behavior:

• GATE — drives the high-voltage MOSFET that chops the rectified DC link. Drive strength, rise/fall times and gate voltage capability determine switching losses and usable MOSFET options.
• CS (current sense) — monitors the primary peak current through a small sense resistor at the MOSFET source. This pin enforces cycle-by-cycle over-current protection and enables current-mode control with slope compensation where supported.
• VDD / VCC — supplies controller bias. Start-up often uses a high-value resistor or integrated high-voltage startup cell, after which the controller transitions to auxiliary winding power for higher efficiency.
• Auxiliary winding input — provides both running bias and, in PSR schemes, a scaled image of output voltage for regulation and brown-out/brown-in decisions.
• FB / COMP — receives primary-side feedback in PSR modes or the optocoupler signal in SSR designs. This node sets the regulation point and loop dynamics.
• ZCD / demagnetization — in QR and DCM controllers, detects when the transformer has fully demagnetized so the MOSFET can turn on near a valley in the drain waveform.

Detailed gate timing for synchronous rectifiers, secondary-side current sensing and post-regulation DC/DC converters are handled on the Synchronous Rectification Controller and Adapter Secondary Power pages to avoid overlap.

Design constraints the controller must respect

• No-load and light-load power — many adapters must meet no-load limits in the 30–50 mW range. Controllers with deep burst or skip-cycle modes, very low VDD quiescent current and integrated HV startup help meet these figures without oversizing magnetics.
• EMI profile — switching edges, operating frequency and jitter behavior shape conducted EMI before the input filter. QR operation and spread-spectrum options reduce peak emissions, while fixed-frequency current-mode designs may target more aggressive filtering instead.
• MOSFET V_DS margin — reflected voltage, mains tolerance, load transients and leakage-induced spikes combine to stress the primary MOSFET. Maximum duty-cycle limits and frequency foldback features in the controller help keep worst-case V_DS within the chosen device rating.
• Auxiliary winding bias window — the reflected auxiliary voltage must keep VDD safely between UVLO(on) and UVLO(off) thresholds across line, load and tolerance while also providing a clean signal for PSR controllers. Poorly chosen aux ratios can cause dropout, mis-regulation or noisy feedback.

Concrete EMI filter schematics, surge protection and safety creepage design are treated on AC input and protection pages; the emphasis here is on how primary-side flyback controllers interact with those constraints through their pins and operating modes.

Operating Modes: Current-Mode vs QR / Valley Switching

Primary-side flyback controllers typically operate either in fixed-frequency current-mode control or in quasi-resonant (QR) valley-switching modes. The choice affects transfer-function shape, switch stress, EMI spectrum and light-load efficiency.

Fixed-frequency current-mode control

In current-mode operation, the controller shapes an internal current ramp using the CS pin and compares it to a voltage error signal each cycle. The switching frequency is nearly constant, while the duty cycle and primary peak current follow load and line conditions.

• Cycle-by-cycle peak current limiting is inherent through the CS threshold.
• The inner current loop simplifies voltage-loop compensation and improves transient behavior.
• Controller cost is usually lower because logic and sensing are straightforward.

The trade-off is sharper EMI peaks at the switching frequency and its harmonics and higher switching losses at light load. Without additional burst or skip modes, light-load efficiency often lags QR and valley-switching designs by a few percentage points.

QR and valley-switching control

Quasi-resonant controllers use the ZCD or demagnetization pin to detect when the transformer current reaches zero and the drain node begins to ring. The MOSFET turns on near a valley of the drain voltage waveform, reducing turn-on loss and dv/dt stress.

• Switching frequency varies with load; heavy load runs closer to the nominal design frequency, while light load moves to lower frequencies.
• Valley selection (first, second or later valley) trades switching loss against peak current and frequency.
• Turn-on in a drain-voltage valley softens EMI and often delivers a 2–3 % or better efficiency gain at light and mid load.

Variable-frequency behavior spreads conducted EMI energy across a wider band and can introduce audible-noise risks near the 20–30 kHz range if not managed with burst and frequency-management features.

Choosing between current-mode and QR / valley operation

• Current-mode flyback suits cost-driven, lower-power adapters where a fixed switching frequency simplifies EMI filter design and efficiency targets are moderate.
• QR / valley-switching flyback suits designs that must pass tight energy-efficiency regulations, reduce switching loss and gain margin on EMI without oversizing the input filter.
• Controllers that combine current-mode behavior at heavier load with valley switching or skip modes at lighter load can provide a balanced compromise.

Only primary-side valley switching is described here. Synchronous rectifier gate timing, secondary-side valley detection and light-load exit behavior are handled on the Synchronous Rectification Controller page.

PSR vs SSR Options

Primary-side flyback controllers can regulate output using primary-side regulation (PSR) or by accepting a secondary-side regulation (SSR) signal through an optocoupler. The choice directly influences voltage accuracy, multi-output behavior, standby power and bill of materials.

Primary-side regulation (PSR)

PSR schemes sample the auxiliary transformer winding during a defined interval, using it as a scaled image of the output voltage. The controller compares this sampled waveform against an internal reference to adjust duty cycle or frequency.

• Auxiliary winding design and sampling timing strongly influence regulation accuracy and load dependency.
• Controller algorithms must handle startup transients where the auxiliary waveform is still settling.
• Typical regulation accuracy is in the ±3–5 % range for well-designed single-output adapters.

The main advantages are lower cost and improved standby performance because the optocoupler and TL431-style error amplifier are eliminated. PSR is well suited to cost-sensitive, single-output adapters where protocol layers or downstream regulators can tolerate small voltage shifts.

Secondary-side regulation (SSR)

SSR uses a dedicated error amplifier, often TL431-class, and an optocoupler on the secondary side to sense the actual output voltage directly. The primary-side controller sees an isolated feedback signal on its FB or COMP pin and adjusts drive accordingly.

• Loop compensation can be tailored around real output capacitors and loads, improving phase and gain margins.
• Voltage accuracy of about ±1 % is achievable with suitable references and resistor networks.
• Multiple outputs and post-regulated rails can be supported with better cross-regulation than PSR alone.

The trade-offs include higher component count, permanent bias current for the optocoupler and error amplifier, and more attention to PCB layout. Light-load efficiency is often weaker than PSR because secondary circuitry continues to draw current.

When to choose PSR and when SSR is required

• Choose PSR for single-output, cost-driven adapters where ±3–5 % regulation is acceptable and low standby power is critical.
• Choose SSR when tight voltage accuracy, demanding load transients or multiple regulated outputs must be supported.
• SSR becomes essential where the primary controller must coexist with precise downstream rails feeding ADCs, precision analog or digital interfaces.

Secondary-side synchronous-rectifier gate control and interaction between SSR loops and SR timing are discussed in detail on the Synchronous Rectification Controller page. This section focuses only on the primary controller side of PSR and SSR choices.

Spread-Spectrum & EMI Shaping

Primary-side flyback controllers can include spread-spectrum or frequency jitter features to reshape conducted EMI. Instead of concentrating energy at a single switching frequency and its harmonics, a small frequency modulation spreads the spectrum and lowers the quasi-peak level that EMI receivers report.

Fixed-frequency switching as an EMI target

In fixed-frequency current-mode designs, the drain current and voltage waveforms repeat every cycle. Harmonic energy is concentrated at the switching frequency and its multiples, creating pronounced peaks in the 150 kHz to several megahertz band where conducted-EMI limits apply. The input filter must be strong enough to attenuate these discrete peaks.

Frequency jitter: typical ranges and behavior

Spread-spectrum controllers modulate the switching frequency around a nominal center value, for example 100 kHz ±2–4 % or ±5–8 %. The modulation can be pseudo-random or periodic, but the effect is similar: harmonic energy that would appear as a narrow spike is redistributed over a small band of frequencies.

• Typical jitter ranges between about 2 % and 8 %, depending on the controller family.
• The modulation rate influences both EMI measurements and audible-noise behavior.
• Total noise energy does not disappear; it is spread so that individual EMI bins see lower peaks.

On a conducted-EMI plot, enabling a 2–8 % jitter function typically reduces quasi-peak readings by a few decibels around critical harmonics, which can be enough to avoid adding another LC stage in the input filter.

Impact on differential-mode EMI and QR compatibility

Frequency jitter is most effective on differential-mode EMI in the 150 kHz to 5 MHz band, where the LISN and receiver measure current flowing through the line filter. Common-mode noise from parasitic capacitances, transformer coupling and layout still requires careful Y-capacitor selection, common-mode chokes and PCB optimization.

In QR and valley-switching controllers, the switching frequency already varies with load. Some devices further randomize valley selection or add small jitter to avoid creating new narrow-band peaks. This combination softens EMI signatures but also increases the need to manage audible noise and low-frequency modulation carefully.

The spread-spectrum and jitter features described here work alongside, not instead of, the AC input and EMI-front-end filter. Detailed X/Y capacitor, common-mode choke and surge protection design is handled on the AC Input & EMI Front-End page.

Ultra-Low Standby, Burst and Skip-Cycle Modes

Offline adapters increasingly need no-load power levels in the 30–50 mW range while remaining ready to wake the system quickly. Primary-side flyback controllers contribute through burst, skip-cycle and valley-only operating modes, combined with low-bias architectures that reduce internal consumption.

Burst mode: deep power savings with Vout ripple

In deep light-load or no-load conditions, burst mode disables continuous switching. The controller waits until the output voltage droops to a lower threshold, then delivers a short burst of pulses to recharge the output capacitor before returning to an idle state.

• Switching and gate-drive losses drop sharply because active pulses occur only in short groups.
• Controller bias current can be reduced between bursts, further lowering standby power.
• Output voltage follows a controlled sawtooth window, for example a few percent above and below the nominal setpoint.

Burst mode can introduce audible noise if the burst repetition rate falls within the audio band or if magnetic components mechanically respond to the modulation. Burst-entry and exit thresholds, along with minimum-load recommendations, are therefore important design considerations.

Skip-cycle and valley-only operation

Skip-cycle modes reduce average switching frequency by omitting some cycles rather than fully grouping activity into long idle periods. In QR controllers, valley-only techniques can be combined with cycle skipping so that switching occurs only on selected valleys at light load.

• Output ripple is usually smaller than in deep burst mode because refresh events are more frequent and uniform.
• Audible noise is easier to manage when frequency changes are bounded and valley selection avoids sensitive ranges.
• Standby loss still improves significantly, though not as aggressively as in the deepest burst modes.

Controllers often combine skip-cycle or valley-only operation in a light-load band with burst at extreme low load so that standby targets are met without compromising mid-load behavior.

VDD bias foldback and HV startup interaction

Ultra-low standby power also depends on how the controller biases itself. Many offline flyback ICs use a high-voltage startup cell to charge VDD at power-up and then hand over to an auxiliary winding. During light-load modes, internal bias circuits enter reduced-current states so that VDD power draw remains small even when switching slows down.

• Efficient HV startup avoids continuous leakage through large-value resistors once normal operation begins.
• Foldback bias modes keep the controller above UVLO(off) while minimizing quiescent current.
• Designers must ensure that burst and skip behavior does not repeatedly force VDD through UVLO thresholds.

Any active discharge of X-capacitors, line-disconnect functions and compliance with discharge time requirements are handled in the AC Input & EMI Front-End section. USB-C PD and DRP low-power protocol states are covered on the USB-C PD/QC/PPS Controller page; this section focuses on the flyback controller’s own standby behavior.

Protections in Primary-Side Flyback Controllers

Primary-side flyback controllers implement a core set of protections around the switch, power stage and their own supply. These on-chip safeguards define how the converter reacts to overload, short-circuit, brown-out and over-temperature events, while system-level devices such as eFuses and hot-swap controllers protect the wider power path.

Cycle-by-cycle OCP and primary peak current limit

The current-sense resistor at the CS pin allows the controller to monitor primary peak current every switching cycle. A fast comparator enforces a peak limit so that each pulse terminates when the CS voltage reaches an internal threshold. This mechanism provides cycle-by-cycle overcurrent protection and bounds transformer and MOSFET stress under overload.

Foldback current limiting and maximum duty-cycle clamps often complement the basic peak limit, ensuring that at low line or during overload the converter cannot exceed its designed power envelope. Sense resistor selection must allow headroom for ringing and leading-edge blanking while ensuring that fault currents trip the OCP threshold reliably.

Brown-in / brown-out line monitoring

Brown-in and brown-out functions monitor the rectified input or a dedicated sense pin so that the controller only operates in a valid line-voltage window. The supply remains off until the line exceeds a brown-in threshold, preventing unstable operation during slow ramp-up or undervoltage conditions, and shuts down gracefully when the line falls below the brown-out level.

Correct brown-in/out settings reduce stress on magnetics and switches during low-line operation and prevent repeated restarts when the mains voltage hovers around the minimum operating point.

VDD UVLO and supply supervision

Undervoltage lockout thresholds on VDD define when the controller is allowed to start and when it must stop. The UVLO(on) threshold ensures that internal drivers and gate buffers receive sufficient supply before enabling switching, while UVLO(off) prevents erratic behavior as VDD decays.

UVLO works together with the high-voltage startup cell and auxiliary winding bias. Proper coordination avoids repeated VDD crossings of the UVLO thresholds during light-load burst and skip modes so that the converter does not chatter between on and off states.

Short-circuit protection and Hiccup mode

Under severe overload or output short-circuit conditions, persistent cycle-by-cycle current limiting alone is not sufficient. Many controllers accumulate overcurrent detections or monitor a sustained low feedback signal to decide that a short circuit is present, then enter Hiccup mode.

In Hiccup mode the controller alternates brief restart attempts with longer off periods. Average dissipation in the transformer, MOSFET, rectifier and sense resistor falls dramatically, allowing the power supply to withstand faults indefinitely without excessive thermal stress while still attempting periodic auto-recovery.

Over-temperature protection

On-chip over-temperature protection monitors the controller’s junction temperature and shuts down or derates operation when a defined threshold is exceeded. This mechanism protects the controller and, indirectly, limits the time spent in high-loss states such as continuous overload or abnormal ambient conditions.

Internal OTP does not replace system-level thermal design. Additional temperature sensors on transformers, heat sinks or output devices may still be required in high-power or tightly enclosed adapters.

Soft-start, leading-edge blanking and slope compensation

A controlled soft-start ramp limits duty cycle and peak current as the converter starts up. By increasing the permissible current gradually, soft-start reduces stress on input rectifiers, bulk capacitors, transformers and secondary diodes and helps maintain control-loop stability during the first milliseconds after power-up.

Leading-edge blanking masks the first tens or hundreds of nanoseconds of the CS signal in each cycle, preventing transformer leakage spikes and diode reverse-recovery noise from causing false OCP trips. Slope compensation adds an artificial ramp to the sensed current in peak current-mode controllers, preventing subharmonic oscillation at higher duty cycles and improving stability.

These protections secure the controller and primary power switch. Safe operating area enforcement, hot-plug control, reverse blocking and bus-level fault isolation are handled by dedicated devices on the eFuse & Hot-Swap page, while secondary-side OVP and regulation schemes are covered under Adapter Secondary Power and SSR-related sections.

IC Role Mapping and Example Part Families

This section maps the main IC roles used around a primary-side flyback controller and illustrates each role with example devices from seven major vendors. The examples are provided as starting points for selection and cross-comparison rather than as exhaustive recommendations.

Current-mode and QR flyback controllers

• Texas Instruments — UCC28C43 / UCC28C4x family: Fixed-frequency peak current-mode PWM controllers that support flyback topologies, with UVLO, duty-cycle limiting and flexible primary- or secondary-side feedback options.
• onsemi — NCP1207A: Quasi-resonant current-mode controller with demagnetization detection and inherent skip-cycle capability that allows borderline conduction and minimum drain-voltage switching at light load.
• Infineon Technologies — ICE3BR0665J CoolSET: Integrated PWM controller and 650 V MOSFET for fixed-frequency flyback, providing current-mode control, protection features and a compact offline SMPS solution.
• STMicroelectronics — L6565 / HVLED00x family: Quasi-resonant flyback controllers that can operate with optocoupler-based secondary regulation and, in some variants, support primary-side techniques for high power-factor LED and adapter supplies.

PSR and integrated primary-side switchers

• Power Integrations — LNK364 (LinkSwitch-XT family): Energy-efficient low-power off-line switcher IC with integrated MOSFET and tight output regulation, implementing primary-side regulation and protection features with very low external component count.
• STMicroelectronics — VIPer converters: High-voltage monolithic converters that integrate a PWM controller and 700 V MOSFET, targeting compact low- to mid-power AC/DC adapters and auxiliary supplies.

SSR-capable flyback and combination controllers

• NXP Semiconductors — TEA1755T: GreenChip combination controller with DCM/QR PFC and flyback stages, designed to work with optocoupler-based secondary regulation and valley-switching for efficient multi-output adapters and chargers.
• Texas Instruments — UCC28C4x-Q1 family: Automotive-qualified current-mode PWM controllers that support both auxiliary-winding primary-side regulation and traditional SSR with optocouplers and TL431-style error amplifiers.

Spread-spectrum and low-standby controllers

• Infineon Technologies — CoolSET / ICE5QR / ICC80QSG families: Quasi-resonant flyback controllers and integrated switchers with valley-switching, frequency reduction and, in some variants, jitter features to reduce EMI and improve light-load efficiency.
• onsemi — NCP1207A and related NCP12xx families: Controllers that combine QR operation with skip-cycle behavior and tailored burst modes to achieve low no-load consumption without introducing audible noise.
• Power Integrations — newer LinkSwitch-XT2 devices (e.g. LNK36xx): Primary-side switchers that add line overvoltage protection, output overvoltage auto-restart and optimized burst management for very low standby power in compact adapters.

High-voltage startup helpers and depletion-mode devices

• Microchip Technology — DN2540 depletion-mode MOSFET: 400 V depletion-mode MOSFET commonly used in efficient startup circuits to charge controller VDD from the high-voltage bus and then self-bias off, reducing standby losses compared to simple resistor-based schemes.
• Various vendors — auxiliary HV startup and linear-regulator helpers: Application notes from controller suppliers illustrate how depletion-mode devices or dedicated startup ICs can offload the high-voltage biasing function and help meet aggressive standby-power budgets.

Primary MOSFET gate drivers (non-GaN)

In higher-power designs, an external primary-side gate driver can buffer the flyback controller output when switching larger silicon MOSFETs or when layout constraints require a stronger drive. Suitable devices include non-isolated and isolated drivers from vendors such as Texas Instruments, Infineon, onsemi and Microchip, often with Miller-clamp and precise UVLO thresholds to keep hard-switching behavior under control.

Gate drivers dedicated to GaN switches, including those optimized for high dv/dt immunity and tailored gate-voltage profiles, are covered in the GaN Driver for Adapters section so that silicon MOSFET and GaN designs remain clearly separated.

Application Mini-Stories for Primary-Side Flyback Controllers

The following mini-stories show how primary-side flyback controllers are used in real products. Each example focuses on the controller, its operating mode and protection behavior, without crossing into USB-C PD, LLC, ATX, PoE or medical-isolation topics that are covered on dedicated pages.

Story 1 · 5 V / 2.4 A USB-A Adapter (PSR Flyback with QR Behavior)

Consider a 5 V, 2.4 A USB-A wall adapter in the 10–15 W range. The target is a compact, cost-sensitive supply that meets typical standby requirements (for example <50 mW at no load) and provides stable 5 V output for phones and small devices, without any USB-C PD or fast-charging negotiation.

Topology and control choice

A single-output off-line flyback converter is used with a primary-side flyback controller that supports valley-switching or quasi-resonant behavior at medium load and primary-side regulation (PSR) from the auxiliary winding. PSR removes the optocoupler and TL431 from the bill of materials and eliminates their bias losses, helping the adapter meet aggressive no-load power limits.

Under heavier load the controller operates in discontinuous or quasi-resonant mode, using a demagnetization or ZCD pin to detect the end of transformer demagnetization and to trigger switch turn-on near the drain-voltage valley. At lighter load, frequency foldback and valley-only operation reduce switching losses while keeping the output ripple within the 5 V tolerance band.

Example controller choices and supporting devices

A typical implementation may use an integrated off-line switcher with primary-side regulation and quasi-resonant switching behavior. Devices from families such as Power Integrations LinkSwitch or TinySwitch, STMicroelectronics VIPer converters, or similar PSR-capable QR controllers from other vendors are commonly chosen in this power range.

• The controller integrates a high-voltage MOSFET, primary current-mode control, PSR algorithm and protections such as OCP, brown-in/out, UVLO and Hiccup.
• The transformer uses a single secondary for 5 V output and an auxiliary winding that powers the controller and feeds the PSR feedback pin.
• The secondary-side rectifier is a Schottky diode sized for about 2.4 A peak, without synchronous rectification or secondary controllers to keep the design focused on the primary flyback IC.

How operating modes, EMI shaping and standby features are used

The current-sense resistor and CS pin set the primary peak current limit so that overloads and short circuits are handled by cycle-by-cycle OCP. When repeated OCP events occur, the controller enters a Hiccup cycle, protecting the transformer and MOSFET without the need for external latching circuitry.

At medium load, quasi-resonant or valley-switching operation minimizes switching losses and DV/DT stress, supporting efficiency targets and easing EMI filter design. Where available, a 2–4 % switching-frequency jitter feature spreads differential-mode EMI energy in the 150 kHz to a few megahertz range, reducing quasi-peak readings so that the AC input filter can remain compact.

At very light load the adapter relies on burst-mode or skip-cycle operation combined with VDD bias foldback. The integrated high-voltage startup cell is active during initial power-up, then hands over to the auxiliary winding so that no-load consumption stays within tens of milliwatts while the 5 V output remains within the allowed voltage window.

Scope notes for this story

This example focuses on the primary-side flyback controller, its PSR algorithm, protection behavior and standby modes. USB-C PD, PPS or other protocol engines, synchronous rectification controllers, eFuse devices on the output port and USB connector ESD protection are covered separately in the USB-C Power, Synchronous Rectification Controller and eFuse & Hot-Swap sections of the Power Supplies & Adapters tree.

Story 2 · 12 V / 1 A Industrial Control Rail (SSR, Current-Mode Flyback)

A second example is a 12 V, 1 A auxiliary supply for an industrial control board. This rail powers digital logic, I/O modules and relays from a universal AC input. The design emphasizes tight output regulation, predictable start-up behavior and robustness in harsh environments rather than extreme adapter-style cost optimization.

Topology and control choice

A traditional fixed-frequency, peak current-mode flyback controller is selected and combined with secondary-side regulation (SSR) using a TL431-type precision shunt reference and an optocoupler. The controller operates at a constant switching frequency, simplifying small-signal modeling and compensation, while the secondary loop provides tight 12 V regulation and good cross-regulation when other rails are derived from the same transformer.

The SSR architecture decouples primary control from exact output voltage sensing. The TL431 error amplifier maintains the 12 V output within a narrow window, and the optocoupler transfers the control signal to the primary-side FB/COMP pin, where the flyback controller adjusts duty cycle accordingly.

Example IC set and role mapping

One implementation pairs a current-mode PWM flyback controller from families such as the Texas Instruments UCC28C4x or similar devices from other vendors with a TL431 and an optocoupler such as PC817.

• The primary controller provides a gate-drive output for a 600–700 V MOSFET, a CS pin for current sensing, UVLO, brown-in/out and Hiccup protection, along with FB/COMP pins that interface naturally to an optocoupler.
• The TL431 monitors the 12 V output via a resistor divider and drives the optocoupler LED so that the controller’s COMP node receives an error signal proportional to load and output voltage.
• An auxiliary winding powers the controller’s VDD once start-up is complete, and also provides a basis for fault-detection schemes such as output overvoltage sensing on the secondary side.

Use of protections, standby control and EMI tools

The sense resistor and cycle-by-cycle current limit protect the transformer and MOSFET during overloads, while the Hiccup mechanism restricts average dissipation during hard shorts on the 12 V rail. Brown-in/out thresholds ensure that the board does not attempt to start at marginal line voltages that would leave logic devices repeatedly resetting.

For conducted EMI compliance, the fixed switching frequency concentrates differential-mode noise into discrete harmonics in the 150 kHz to 30 MHz band. If the chosen controller family offers a few percent of spread-spectrum jitter, that feature can be enabled to flatten quasi-peak measurements and ease filter sizing at the AC input, while common-mode filtering and surge design are handled in the AC Input & EMI Front-End and surge-protection pages.

Idle or light-load operation in this industrial supply may not target ultra-aggressive no-load power, but skip-cycle or mild burst behavior still reduces standby dissipation and transformer heating during long idle periods, without introducing the larger output-voltage windows sometimes associated with deep burst modes.

Scope notes for this story

This industrial 12 V example remains focused on the primary-side flyback controller, its SSR interface and built-in protections. System-level topics such as complete industrial power-tree design, 24 V distribution, PoE sourcing, ATX or server supplies and medical isolation requirements are handled in other sections of the Power Supplies & Adapters and Industrial Power application trees.

Primary-Side Flyback FAQ

This FAQ summarizes how to choose PSR vs SSR, configure current-mode or QR operation, and tune protections, standby and sensing details for primary-side flyback designs. Each answer is written from a practical design perspective and maps back to the sections above on scope, operating modes, regulation methods and protection behavior.

1. When should I choose PSR instead of SSR in a flyback design?

PSR is attractive for single-output adapters in roughly the 5–24 V range where ±3–5 % regulation is acceptable, cost and size are tight, and very low standby power is required. It removes the optocoupler and TL431 bias losses. SSR becomes preferable when multiple outputs, tighter accuracy, demanding load transients or complex sequencing are required.

2. Why does QR improve light-load efficiency compared to CM?

In fixed-frequency current-mode flyback converters, switching, core and gate-drive losses remain significant even when load current is low. Quasi-resonant operation allows the controller to reduce frequency and switch near drain-voltage valleys at light load. Lower dv/dt, reduced capacitive losses and fewer cycles per second typically deliver a few percentage points of extra light-load efficiency.

3. How does spread-spectrum specifically reduce EMI peak energy?

Without spread-spectrum, differential-mode noise concentrates at the switching frequency and its harmonics, creating narrow, tall peaks in the EMI plot. Modulating the frequency by a few percent spreads the same total noise energy over a wider band. Each measurement bin sees lower quasi-peak amplitude, often cutting a few decibels from critical test points.

4. Why is valley switching sensitive to leakage inductance and snubber choice?

Valley switching relies on a clean drain-voltage ringing waveform after demagnetization so that the controller can detect minima reliably. Excessive leakage inductance or an overdamped snubber distorts or flattens the valleys, while very underdamped ringing and high dv/dt can create spurious edges at the ZCD pin. Both extremes complicate accurate valley detection.

5. How can a design meet very low standby power with PSR controllers?

Achieving very low standby typically combines a PSR controller with deep burst or skip modes, low internal bias currents and an efficient high-voltage startup scheme that turns off after start-up. The auxiliary winding must support VDD with minimal losses, and any dummy loads or secondary bias networks should be removed or heavily optimized to avoid unnecessary consumption.

6. What compensation challenges occur in PSR at heavy load?

PSR derives feedback from the auxiliary winding, whose relationship to the output depends on transformer coupling, rectifier drops and load conditions. At heavy load, increased diode conduction, leakage and parasitic effects distort the auxiliary waveform. The effective loop gain and phase can shift with input voltage and load, making compensation less straightforward than with a classic SSR TL431 loop.

7. When should a high-voltage startup helper IC be added?

A dedicated high-voltage startup IC or depletion-mode MOSFET helper is useful when the primary controller lacks an integrated startup cell or when standby requirements are too strict for simple resistor charging. It can provide fast, well-controlled VDD ramp-up and then disconnect from the high-voltage bus, cutting leakage and improving start-up consistency over input and temperature.

8. What faults typically trigger hiccup versus latched shutdown in flyback controllers?

Hiccup mode usually responds to recoverable faults such as persistent overload, output short circuits or repeated start-up failures. The controller alternates brief restart attempts with off periods. Latched shutdown is often reserved for more serious events, including output overvoltage, internal over-temperature or pin faults, where a manual input-cycle or control reset is desirable for safety.

9. How can audible noise in burst and skip-cycle operation be prevented?

Audible noise arises when burst or skip-cycle patterns modulate magnetics and components in the few hundred hertz to several kilohertz range. Setting minimum and maximum burst rates, limiting output voltage swing and favoring skip-only modes can keep modulation outside the most sensitive audio band. Magnetic design, impregnation and mechanical mounting further reduce vibration and audible noise.

10. How should the CS resistor be sized for both OCP accuracy and noise immunity?

A good starting point is to compute the ideal sense resistor from the desired peak current and the controller’s OCP threshold, then add margin for ringing and tolerances. Short RC filtering and appropriate leading-edge blanking help suppress turn-on spikes. The final value should trip reliably under genuine overload while remaining clear of noise in normal operating conditions.

11. Why do some QR controllers mis-detect ZCD at high dv/dt?

High dv/dt on the drain and auxiliary winding can inject noise into the ZCD network, especially if the trace is long or poorly referenced. Underdamped leakage ringing and inadequate snubbing create false zero crossings or multiple edges. The controller may then prematurely initiate a new cycle, disturbing valley timing and causing extra losses or unstable behavior.

12. What is the correct way to bias the auxiliary winding for stable VDD?

The auxiliary winding turns ratio and rectifier network should keep VDD between the controller’s UVLO(on) and maximum rating across input range and load conditions. A clamp device, such as a Zener, can limit VDD under high-line and light-load conditions. Tight, low-inductance routing and adequate filtering help avoid jitter or unintended UVLO crossings during steady-state operation.