Many AC/DC supplies with 5–20 V outputs and a few to tens of amperes still rely on diode or Schottky rectifiers. At these currents, a fixed forward drop of 0.4–0.7 V turns into several watts of pure loss on the secondary side, forcing larger heat sinks, heavier copper and uncomfortable case temperatures.

Replacing diodes with synchronous MOSFETs drastically reduces conduction loss and improves efficiency, directly easing thermal design and enabling higher power density in adapter, charger and server PSU form factors. However, simply dropping in a MOSFET without proper control does not guarantee better performance.

Poorly implemented synchronous rectification can cause negative current, excessive ringing on the secondary, MOSFET overvoltage stress and localized heating. When the primary controller enters DCM, skip, burst or PSR modes, an SR stage that fails to exit cleanly may keep switching into resonant noise instead of real energy transfer, corrupting waveforms and eroding efficiency gains.

This page focuses on the secondary-side synchronous rectification controller itself: how it senses current or V_DS, decides when to turn the MOSFET on and off, handles light-load and burst conditions, and provides protection features so designers can realize the expected efficiency and thermal benefits without introducing new failure modes.

Synchronous rectification is widely used wherever secondary-side currents are high enough for diode loss to dominate the efficiency budget. In low-to-medium power AC/DC flyback adapters and chargers, a single MOSFET synchronous rectifier can significantly reduce loss on a 5–20 V output, improving thermal performance in USB adapters, phone chargers and set-top box supplies.

In higher power stacks with PFC plus LLC stages, synchronous rectification is almost mandatory on the secondary side. Server PSUs, ATX and CRPS supplies, and large TV or display power modules rely on SR MOSFETs to meet stringent efficiency and power density targets. Here, the synchronous rectification controller must accommodate higher switching frequencies, larger output currents and multi-device arrangements.

Bridgeless or active-bridge AC/DC front ends and high-power adapter stages also employ synchronous rectification on their secondary or DC/DC legs. These topologies push switching transitions and current levels, and the SR controller is expected to track phase, sense direction correctly and avoid shoot-through or negative conduction even under fast load transients.

Across these platforms, the primary-side controller sets PWM, operating mode and overall energy transfer, while the synchronous rectification controller focuses on acting as an intelligent replacement for secondary diodes: it observes waveforms at the MOSFET or secondary node, drives the gate only when current should flow forward, and exits gracefully in light-load or burst conditions so the primary control strategy is not disturbed.

A synchronous rectification controller must decide, at every switching cycle, when the secondary-side MOSFET should take over from the diode and when it must be turned off again. In practice this decision is based on sensing whether current is still flowing from the transformer to the output, and whether the energy transfer phase in the cycle has finished. The most common detection methods rely on V_DS, the secondary or rectifier node voltage, or a current-sense signal from a CT or shunt.

V_DS sensing monitors the MOSFET drain-source voltage and uses a small negative threshold to infer that current is flowing through the body diode. When V_DS stays below a negative threshold such as −30 mV to −80 mV for longer than a leading-edge blanking time, the controller turns the device fully on to reduce loss. As current decays and V_DS rises back toward zero or positive values, the controller turns the MOSFET off before current reverses, using turn-off thresholds and trailing-edge blanking to avoid reacting to spikes and ringing.

Some controllers watch the secondary winding or rectifier node voltage instead of V_DS directly. In these schemes, the zero-crossing of the secondary voltage and the transition into a ringing or flyback phase indicate that usable energy has been delivered. The controller interprets these node voltage changes to decide when to stop synchronous conduction, and may combine node sensing with V_DS thresholds to improve robustness in noisy layouts or at high dv/dt.

Current-sense-based conduction criteria use a CT or shunt in the secondary path to observe the current waveform directly. When the measured current crosses zero or falls below a programmable limit, the controller turns the MOSFET off even if V_DS still shows some residual ringing. This approach can provide more deterministic control at higher power levels, where large currents and parasitics make pure V_DS sensing less reliable, at the cost of extra sense components and careful design of burden and filtering networks.

In continuous conduction mode, the secondary current remains above zero for a significant portion of each cycle, so conduction intervals are relatively long and zero-crossings are well separated from noise. In discontinuous conduction mode the energy packet is smaller, current returns to zero early and the remaining part of the period is dominated by resonant ringing. In this regime, any conduction criterion that reacts too aggressively to small negative V_DS or node voltage excursions can trigger unwanted turn-on and negative current. Many modern controllers therefore add adaptive turn-on and turn-off behavior on top of basic thresholds and blanking, so that conduction decisions stay aligned with real energy transfer rather than with high-frequency artifacts.

Light-load and no-load conditions are often where synchronous rectification becomes most challenging. As the output current falls, the primary controller shifts into DCM, skip or burst modes, and the transformer secondary spends a larger fraction of each cycle in resonant ringing rather than in clean energy transfer. If the SR controller continues to apply its full conduction criteria, especially when based only on V_DS, it can misinterpret ringing as useful negative voltage and turn the MOSFET on into reverse current.

Typical symptoms of inadequate light-load handling include strange low-load efficiency curves, unexpected output ripple, audible noise and MOSFET case temperatures that remain high even when the load is small. In severe cases, repeated mis-triggered conduction into ringing can overstress the MOSFET and secondary rectifier network, especially during standby testing that runs for many hours at elevated ambient temperature.

To avoid these behaviours, many synchronous rectifier controllers implement explicit light-load exit or green modes. When the sensed conduction time, switching frequency or current amplitude falls below internal thresholds, the controller disables synchronous turn-on and lets the diode or body diode conduct on its own. This behaviour effectively reverts the converter to simple diode rectification at very low load, trading a small loss of efficiency for stable waveforms and predictable thermal behaviour in standby conditions.

Minimum off-time and additional blanking logic are also used to keep the SR from chattering on and off during ringing. By enforcing a minimum off interval and requiring that conduction criteria be met for a defined time before re-enabling the MOSFET, the controller avoids responding to every small negative excursion that appears after the real energy packet has ended. These timing parameters must align with the transformer, leakage inductance and output filter characteristics of the actual design.

In burst-mode capable systems, more advanced controllers monitor multiple cycles for the absence of genuine energy transfer. When several consecutive cycles contain only ringing and no substantial current, the synchronous rectifier logic enters a deeper sleep state until a true burst of energy returns. Some primary controllers also export mode or burst information on a dedicated pin, and companion SR controllers may use this signal to adjust thresholds or disable operation. During selection, it is important to review the sections on burst or skip compatibility in both the primary and SR controller datasheets and to verify, in hardware, that the SR stage enters and exits light-load modes cleanly across all operating conditions.

A synchronous rectifier controller protects the secondary-side MOSFET from a set of failure modes that are specific to SR operation. Negative current protection limits reverse conduction when turn-off is late or conduction criteria are misaligned with the true current direction. Over-voltage protection aims to contain V_DS stress caused by leakage inductance and abrupt turn-off, while over-temperature shutdown protects the controller itself when local heating or sustained overload raises junction temperature beyond safe limits.

In configurations with dual MOSFETs or half-bridge style synchronous rectification, shoot-through prevention becomes critical. Dedicated SR controllers enforce non-overlap between complementary gate drives and implement hardware interlocks so that both MOSFETs cannot turn on simultaneously. These mechanisms work together with reverse current limits to avoid situations where the SR path briefly behaves as a low-resistance short across the secondary or output rails during switching transients or control glitches.

The SR MOSFET safe operating area remains the ultimate reference for what the device can withstand. Repetitive inrush currents, short-duration overloads and abrupt load steps all push the device toward the limits of its current–voltage–time envelope. High-temperature operation further shrinks the effective SOA, because R_DS(on) rises with junction temperature and turns a fixed conduction interval into a larger power impulse. If gate drive strength or dead-time settings cause frequent hard switching, switching losses stack on top of conduction loss and can create local hot spots that are not obvious from average current calculations.

Some protections reside entirely inside the SR controller, such as reverse current detection, internal V_DS monitoring and over-temperature shutdown. Others require external circuitry to be effective. RC snubbers, RCD clamps and TVS diodes are often necessary to absorb the energy behind voltage spikes and to keep the actual V_DS waveform inside the MOSFET rating, even when the controller turns off correctly. PCB layout and copper planes determine how effectively heat is spread from the SR devices into the rest of the board and the enclosure, directly influencing long-term reliability.

Practical validation combines functional tests with stress and thermal measurements. Dynamic load steps and fault simulations reveal whether reverse current limiters and shutdown mechanisms behave as expected. Short-circuit and overload tests show how close the design operates to the MOSFET SOA boundaries. Infrared imaging highlights local hot spots around the SR MOSFET and controller, allowing designers to tune clamp networks, gate timing and copper distribution before the product is exposed to long-duration field stress.

Timing parameters in a synchronous rectifier controller determine both efficiency and safety. Turn-on delay and propagation delay define how much of the useful conduction interval is actually handled by the MOSFET instead of the diode, while turn-off delay determines how close the design operates to the onset of reverse current. A conservative starting point is to keep turn-off timing slightly early and turn-on timing slightly late, then refine settings based on measured waveforms and device margins rather than pushing immediately for maximum conduction time.

Datasheets usually provide V_DS thresholds, minimum on and off times, and propagation delays from sense pins to the gate driver. These values can be combined with measured secondary current and V_DS waveforms to estimate the real turn-on and turn-off instants relative to the current zero-crossing. This approach helps to build explicit safety margins instead of relying on approximate visual alignment between gate and V_DS on an oscilloscope screen, especially when parasitics and transformer leakage shift the apparent waveforms.

Layout has a strong influence on both the accuracy of sensing and the stress on the SR MOSFET. The gate-drive loop between the controller and MOSFET should be short and compact to minimise inductance and reduce overshoot. Where a Kelvin source terminal is available, sense returns and gate reference connections should use this node instead of the main power source pad, improving V_DS sensing accuracy and reducing errors caused by source lead inductance. Current-sense and V_DS sense traces should avoid long parallel runs with noisy switching nodes and should be routed with clear references to quiet ground regions.

Synchronous rectification reshapes dv/dt and di/dt at the secondary side, which in turn affects conducted and radiated EMI. A strong, fast gate drive reduces conduction loss but can raise high-frequency components and aggravate ringing on the rectifier node. Increasing gate resistance and adding RC dampers or snubbers on the SR node slows transitions and damps resonances at the cost of some efficiency. The best trade-off is normally found by iterating between efficiency measurements, thermal imaging and EMI pre-compliance scans rather than optimising any single metric in isolation.

A practical workflow starts from the controller vendor’s reference layout and recommended component values, then refines timing, gate resistance and snubber components during lab evaluation. Heavy-load and light-load waveforms confirm that conduction windows are centred on real energy flow and that SR operation exits cleanly in burst or standby modes. Thermal and EMI observations guide final adjustments, ensuring that the synchronous rectifier stage contributes to overall efficiency targets without compromising reliability or emissions performance.

Generic selection checklist for synchronous rectifier controllers

Before shortlisting part numbers, it is useful to verify that the basic attributes of the SR controller overlap with the intended topology, power level and control scheme of the power stage. The following checklist helps build that baseline.

• Supported topologies: confirm whether the device is flyback-only, LLC-only or supports multiple rectifier configurations (single-ended, center-tap, full-bridge) required by the design.
• Voltage and frequency range: verify that the secondary voltage window and switching-frequency range of the converter sit comfortably inside the recommended operating region of the SR controller.
• Conduction detection method: identify whether the controller relies on V_DS-only sensing, current-sense assistance (CT or shunt) or a hybrid scheme, and match this to the expected noise and parasitic environment.
• Light-load and burst behaviour: check for green mode, light-load disable and explicit burst-mode compatibility, especially when the primary controller uses skip or valley-skipping modes.
• Protection set: ensure the presence of reverse current limiting, V_DS stress detection and over-temperature shutdown that align with the SOA of the chosen MOSFETs.
• Gate-drive strength and MOSFET count: compare peak gate current capability and recommended total gate charge against the number and size of MOSFETs used, particularly in high-power or parallel configurations.
• Package and layout impact: choose packages whose pinout supports short gate loops and Kelvin source routing in the available PCB area.

Role mapping by application class

Different application classes call for different SR controller roles. The following mapping illustrates how the same design principles scale from compact USB chargers up to higher power server and telecom supplies.

20–30 W USB charger and small wall adapter (flyback SR)

In this range, simplicity and standby compliance dominate. Controllers typically target flyback-only operation with V_DS-based detection, minimal external components and strong light-load disable behaviour. Green mode and burst compatibility are essential to prevent unnecessary SR switching during standby.

• Target role: low-pin-count, flyback-focused SR controller with robust light-load exit and basic reverse current protection.
• Typical design focus: improve efficiency at 5–9 V output without compromising standby power or increasing BOM complexity.

65–120 W notebook adapter and mid-power adapter (QR flyback SR)

For notebook and similar adapters, controllers must track a wide frequency range in QR operation and provide stronger protection and timing options. Adjustable blanking, refined turn-off behaviour and documented compatibility with popular QR primary controllers become important.

• Target role: QR-capable SR controller with configurable timing, more complete fault handling and good synergy with burst and valley-skipping modes.
• Typical design focus: reduce adapter case temperature and transformer losses while maintaining clean waveforms across line and load.

500–1000 W server and telecom supplies (LLC SR, multi-MOSFET)

High-power LLC-based supplies often use multiple MOSFETs per leg and operate at higher currents and dv/dt. SR controllers in this class typically support dual or multi-channel control, current-sense-assisted conduction criteria and detailed protection features aimed at maintaining safe operating area margins in demanding thermal environments.

• Target role: multi-channel SR controller with current-sense or hybrid detection and explicit support for parallel MOSFETs.
• Typical design focus: balance efficiency, thermal distribution, SOA margin and EMI performance at high output power.

Example SR controller families from seven major vendors

The following devices illustrate how commercial SR controller families map into the roles described above. Part numbers are shown as examples to guide searches and comparisons; designers should always consult the latest datasheets for detailed specifications.

65 W QR flyback notebook adapter: reducing case temperature with SR

A 19 V, 65 W notebook adapter using a QR flyback stage originally relied on a Schottky rectifier. In a 40 °C environment and near full load, measurements showed adapter case temperatures approaching limits and secondary heatsink temperatures well above desirable levels. Efficiency in the high-load region plateaued in the high eighties, and thermal headroom for tighter enclosures or higher ambient was limited.

Replacing the Schottky with a synchronous rectifier MOSFET and a QR-capable SR controller allowed the designer to shift most conduction from the diode into a low R_DS(on) path. Conduction criteria were tuned as described earlier: V_DS thresholds and blanking times were adjusted so that turn-on aligned with the real energy packet, while turn-off always preceded the current zero-crossing by a safe margin. Light-load and green mode were enabled so that, in standby, the SR controller disabled itself and let only very brief diode conduction occur.

After optimisation, the efficiency curve at 230 VAC improved by several percentage points in the 40–65 W band and case temperatures dropped by several degrees under continuous operation. Thermal images showed the former hotspot on the secondary shrunk significantly, with the transformer and primary devices becoming the new dominant heat sources. Standby power remained compliant, because the SR controller exited cleanly to a low-power state at light load and did not chase secondary ringing.

For this class of adapter, key SR controller requirements include: explicit QR support over the expected frequency range, robust V_DS sensing with configurable blanking, green mode or light-load disable, and protection features such as reverse current limit and V_DS stress handling. These criteria can be used as a checklist when comparing candidate ICs for future notebook or mid-power adapter designs.

350 W LLC telecom/server supply: secondary-side SR pitfalls

A 48 V input, 12 V output, 350 W telecom module used a PFC plus LLC front-end with multiple parallel MOSFETs on the secondary. The initial SR implementation relied on a single-channel V_DS-sensing controller driving several MOSFETs. Under heavy load and certain line conditions, thermal imaging revealed one device running significantly hotter than its neighbours, and oscilloscope traces showed occasional negative current and high V_DS ringing on the secondary node.

Root-cause analysis traced the issues to a combination of unequal gate-drive paths, limited visibility of actual secondary current and aggressive timing tuned for efficiency rather than SOA margin. The design was updated to use a multi-channel SR controller with current-sense-assisted conduction criteria. Current transformers were added to provide clearer zero-crossing information, and gate and sense routing were reworked to make parallel MOSFET paths symmetrical with shorter loops and Kelvin source connections.

After retuning turn-off thresholds, dead-time and gate resistors, the negative current events disappeared, V_DS overshoot fell inside the MOSFET rating with margin and the thermal profile across the secondary devices became noticeably more uniform. EMI pre-scans improved at the frequencies previously dominated by secondary-side ringing. This example highlights the importance of multi-channel control, hybrid sensing and careful layout for higher power LLC secondaries where SR devices operate close to their SOA limits.

Fast-charge USB-C adapter: balancing SR efficiency and cost

A compact multi-port fast-charge adapter delivering up to 100 W over USB-C PD and PPS needed higher efficiency at elevated output voltages without sacrificing form factor or cost. The original design already used careful primary control and low-loss magnetics, but Schottky rectifiers at the secondary limited efficiency in 15–20 V modes and forced more volume to be dedicated to heatsinking and airflow paths.

Transitioning to a synchronous rectifier controller and MOSFET pair improved efficiency in the higher voltage PDOs and allowed a modest reduction in thermal management hardware. However, PD and PPS operation introduced a wide range of output voltages and dynamic load steps. The SR controller therefore needed reliable operation across varying secondary voltages and strong compatibility with the primary controller’s burst and skip modes used at light load and during transitions between PDOs.

After tuning conduction thresholds, light-load exit and gate-drive strength, the design achieved noticeable efficiency gains in the 9–20 V, mid-to-high load region while keeping low-voltage, low-current performance within regulation and thermal targets. A final cost comparison showed that the added SR components were offset by savings in heatsink and mechanical complexity, while the higher efficiency supported a more competitive feature set. For fast-charge adapters of this type, SR controllers should be shortlisted based on wide secondary voltage compatibility, well-documented burst-mode behaviour and compact packages that fit tight layouts.

1) Topology, power level and frequency range match

The first step is to confirm that the selected synchronous rectifier controller is fundamentally compatible with the converter topology, output power and switching-frequency envelope. A mismatch at this level is difficult to fix later with tuning alone.

• Topology fit: verify that the SR controller explicitly supports the intended configuration (flyback, LLC, active-bridge or similar) and the rectifier structure used (single-ended, center-tap or full-bridge).
• Power level and MOSFET count: check that gate-drive capability and recommended total gate charge cover the number and size of MOSFETs, especially when devices are paralleled on high-current rails.
• Frequency range overlap: compare the controller’s specified operating frequency window with the actual range of the primary controller from light load to full load. Both the highest QR or LLC frequency and the lowest burst or skip frequency should remain inside the SR controller limits with margin.

2) Mode mapping between primary controller and SR functions

A robust design aligns every operating mode of the primary controller with a clearly defined behaviour on the SR side. Each combination of load and line condition should be mapped to “SR actively conducting”, “degraded operation” or “SR completely disabled”.

• List primary modes: enumerate CCM, DCM, QR, skip, burst and standby modes used by the primary controller across load and line conditions.
• Map SR behaviour: for each mode, document how the SR controller detects conduction, when it turns on and off, and whether any light-load or green mode thresholds are expected to activate.
• Check coverage: ensure that no primary mode exists where SR behaviour is undefined, such as aggressive burst operation without corresponding SR disable or reduced activity.

3) Light-load and no-load behaviour: verified SR exit

Light-load and standby conditions are where synchronous rectifiers often misbehave, chasing transformer ringing or turning on into very small energy packets. A dedicated set of tests is required to confirm that the SR controller exits gracefully.

• Sweep from full load to no load: gradually reduce load while observing SR gate, secondary current and V_DS waveforms. Document the point where SR conduction starts to shorten and where it fully disables.
• Check for false triggering: confirm that, near no load, the controller does not repeatedly turn on in response to secondary ringing, which would increase standby losses and local heating.
• Verify standby power: ensure that the combination of primary and SR behaviour meets standby and efficiency regulations with safe thermal margins around the SR MOSFET.

4) Thermal performance and SOA margin

Thermal behaviour is a direct indicator of how close the SR MOSFET operates to its safe operating area. Local hot spots and uneven temperatures between paralleled devices often signal timing, sensing or layout issues that must be corrected before volume production.

• Run thermal tests at key points: perform extended operation at low, nominal and high line under full load and typical mid-load conditions, then record SR MOSFET and controller temperatures.
• Inspect thermal images: look for local hot spots on SR MOSFETs, especially when devices are paralleled. A single device significantly hotter than its peers usually points to unequal conduction or asymmetric gate drive.
• Compare with SOA: ensure that the combination of peak current, V_DS stress and junction temperature stays comfortably inside the MOSFET safe operating area for repetitive operation, not only for single pulses.

5) Fault and stress behaviour: short, overload and hot-plug

Short circuits, overloads, load transients and power interruptions stress the SR stage differently from normal regulation. The controller must react in a way that pulls the MOSFET out of harm’s way while the primary protections take over.

• Output short and heavy overload: inject controlled shorts and overloads at different input voltages. Confirm that SR gate drive turns off quickly, avoids participating in the short-circuit current and keeps V_DS within its rating.
• Operation near current limit: hold the supply just inside current limit and monitor SR device temperature and waveforms for signs of repeated operation near SOA boundaries.
• Hot-plug and load insertion: test rapid connection and disconnection of loads with significant output capacitance. SR behaviour should prevent reverse energy flow and avoid negative current surges when cables are plugged or unplugged.
• Coordination with primary protections: verify that when the primary controller enters hiccup, latch-off or restart, the SR controller quickly disables gate drive instead of continuing to react to residual waveforms.

6) EMI pre-scan correlation with SR switching edges

Synchronous rectification alters dv/dt and di/dt on the secondary, which can create or move EMI peaks. Relating problem frequency bands back to SR switching edges avoids over-designing filters while still respecting emissions limits.

• Identify EMI peaks: use pre-compliance scans to mark the dominant conducted and radiated emission frequencies at representative line and load conditions.
• Capture SR waveforms at those points: measure SR gate, V_DS and rectifier-node waveforms at the same operating conditions. Look for fast edges and ringing that align with the identified frequencies.
• Adjust SR parameters: experiment with gate resistance, snubber components, dead-time and conduction thresholds. Observe whether EMI peaks move or shrink in response, confirming how much of the problem is driven by the SR stage.

When these checks are documented and closed, the synchronous rectifier controller is usually well integrated into the power supply, with predictable behaviour from heavy load down to standby and from normal operation through fault conditions and emissions testing.