What this page solves in a DFIG wind turbine

This page explains the role of the DFIG grid-side converter as the interface between the DC link and the utility grid. It focuses on how the grid-side converter maintains DC-link voltage, regulates active and reactive power, meets grid code requirements and shapes fault behaviour during LVRT/FRT and other disturbances at the point of common coupling.

The emphasis is not on DFIG electromechanical modelling or rotor-side control loops, but on the measurement, PLL and protection infrastructure that make the grid-side converter behave predictably in real networks. The content shows how grid-tied PLL, synchronized sampling, isolated current and voltage measurement, and fast protection paths work together to keep the converter within grid code envelopes while protecting power switches and transformers.

• Maintain DC-link voltage and active power flow from the rotor-side converter into the grid.
• Provide reactive power and power factor control to satisfy grid code targets at the point of connection.
• Shape LVRT/FRT behaviour, including current limiting and voltage support during sags and faults.
• Supply a grid-tied PLL time base and synchronized sampling clock for inner current loops and higher-level turbine control.
• Capture fault events and operational logs with time stamps so SCADA and service teams can reconstruct field incidents.

On the IC level, this page concentrates on:

• Voltage and current AFEs feeding isolated sigma-delta modulators or ADCs for grid and DC-link sensing.
• Grid-tied PLL implementations and the way ADC resolution, sampling jitter and filter delay affect phase tracking accuracy.
• Fast protection paths using comparators, desaturation detection and gate-driver features to limit fault current.
• Relay and contactor drivers that execute trip and interlock commands towards breakers and contactors at the point of connection.
• Event logging and time stamping using RTCs, synchronized clocks and non-volatile memory inside the converter control platform.

Several closely related topics are intentionally delegated to sibling pages to keep this content focused:

• DFIG rotor-side converter control and electromechanical modelling are covered by the “DFIG Rotor-Side Converter” page.
• PMSG rectifiers and grid interfaces are discussed in “PMSG Rectifier & Grid Interface”.
• Wind farm–level dispatch and microgrid EMS coordination are treated in “Renewables in Microgrid EMS” and smart grid–oriented pages.

Scope, interfaces and grid code constraints

The grid-side converter sits between the DC-link supplied by the rotor-side converter and the point of common coupling to the grid. It must exchange both power and information with several neighbouring subsystems: the rotor-side converter, LCL filter and transformer, grid protection and interlock panels, and nacelle or wind farm controllers and SCADA gateways.

Electrical and control interfaces

• Upstream (DC-link from rotor-side converter) – provides DC voltage and current into the grid-side converter. The grid-side converter must measure VDC and sometimes IDC, regulate DC-link voltage, and honour power or current limits signalled by the rotor-side control.
• Downstream (filter, breaker and transformer) – includes LCL filter currents and voltages, point-of-connection voltage, and breaker or contactor coils. Measurement AFEs and isolated ADCs tap into these nodes, while driver ICs energize breakers, contactors and grounding switches in response to control and protection decisions.
• Side interfaces to nacelle controller and SCADA gateway – carry active and reactive power setpoints, mode commands, measurements, status and event logs. The grid-side converter often acts as the source of grid-tied phase angle and frequency information for higher-level controllers.
• Side interfaces to grid protection and interlock panels – exchange trip requests and “permission to connect” signals. Utility protection relays may demand opening of the breaker, while severe converter faults can send their own trip signals back to the panel.

Typical grid code constraints at the point of connection

• Voltage and frequency deviation tolerance – the converter must continue operating within defined voltage and frequency windows, while keeping active power and power factor within allowed limits. This demands accurate voltage measurement and a robust grid-tied PLL.
• Reactive power and power-factor capability – grid codes specify how much reactive power or power-factor adjustment the turbine must provide as grid voltage or active power changes. This translates into requirements on the d/q current control loops and the resolution and bandwidth of current sensing.
• Low-voltage ride-through (LVRT/FRT) behaviour – during voltage dips, the grid-side converter is expected to remain connected for a specified time and inject a defined reactive current profile, without exceeding current limits or losing control. Measurement chains, PLL and fast protection must work together under distorted waveforms.
• Current and harmonic limits – maximum RMS and peak currents, as well as harmonic distortion limits, constrain filter design and control bandwidth. They also define the dynamic range and noise requirements for current and voltage ADCs.
• Reverse power and unbalanced conditions – some grid codes restrict reverse power flow or unbalanced currents. Detection of these conditions relies on accurate, synchronized sampling of phase voltages and currents and robust real-time calculations.

How grid codes map into IC and subsystem requirements

• PLL accuracy and stability – phase-angle and frequency error limits dictate the required resolution, sampling rate and jitter performance of voltage measurement channels. Isolated sigma-delta modulators and their digital filters must be chosen with delay, bandwidth and noise in mind.
• Fast overcurrent detection during LVRT/FRT – current limits in fault regions require dedicated comparators and protection features inside gate drivers, rather than relying only on software. Blanking times, thresholds and response times must be programmable to match grid code envelopes.
• ADC performance for current and voltage sensing – harmonic and dynamic requirements lead to minimum effective number of bits, sampling rates and synchronization strategies for phase voltages, filter currents and DC-link voltage.
• Event time stamping and logging – grid faults, ride-through events, trips and reconnect attempts must be logged with time stamps that can be aligned with substation and SCADA records. This drives the choice of RTC or synchronized clock, non-volatile memory type and logging architecture in the converter controller.
• Interface robustness to protection and interlock panels – the signalling path between grid-side converter and external protection panels must handle noise, isolation and fail-safe behaviour. Driver ICs and digital isolators need to support the required voltage ratings and safety categories.

Detailed coordination of substation protection functions, line protection zones and scheme selection is discussed in grid-protection-oriented pages. Likewise, monitoring of export and array cables, including partial-discharge and dielectric-loss analysis, is handled by the “Array/Export Cable Monitoring” page. This section keeps the scope centred on the converter’s own interfaces and obligations at the point of connection.

Converter topology and control loop structure

The DFIG grid-side converter is typically implemented as a voltage-source converter with a two-level or three-level power stage followed by an LCL filter and a breaker at the point of common coupling. This section outlines how the power topology, current and voltage measurement, d/q control loops and the grid-tied PLL fit together, without going into modulation pattern details.

In most installations the grid-side converter operates as a controlled voltage source at the AC terminals, fed by the DC link shared with the rotor-side converter. A two-level topology offers simplicity and mature design practices, while three-level structures help reduce switching losses and filter sizes at higher voltages. In both cases, the LCL filter defines where currents and voltages are sampled for the control system and protection circuits.

d/q control loops and DC-link voltage control

The grid-side converter is usually controlled in a synchronous rotating d/q frame provided by the grid-tied PLL. Phase currents and voltages are transformed into Id and Iq components, where Id primarily sets active power and Iq handles reactive power or power factor. Inner d/q current loops run at the highest bandwidth, closing the loop from current references to measured currents through PI controllers and PWM generation.

• A DC-link voltage outer loop adjusts the Id reference so that VDC remains within its target band under varying rotor-side power and grid voltage conditions.
• Inner d/q current loops regulate Id and Iq using measurements from isolated current sensors, coordinating active and reactive power delivery while respecting current limits.
• The grid-tied PLL supplies the angle and frequency for the Park transform, so PLL dynamics directly influence current loop stability and the interpretation of Id and Iq.

The exact modulation scheme, SVPWM pattern selection and dead-time compensation strongly affect switching losses and harmonic spectra, but these topics are treated in generic power-driver and multi-level converter pages. Here the focus stays on how the grid-side converter topology, measurement points and control loops interact to meet grid code and protection requirements.

IC touch points in the control structure

• PWM controller and digital control platform – MCU, DSP, SoC or FPGA resources implement d/q current loops, the DC-link voltage loop, Park and Clarke transforms, fault handling logic and PWM generation for two-level or three-level stages.
• Gate drivers – drive IGBTs or MOSFETs in the power stage and expose desaturation and overcurrent protection signals into the control and protection layers.
• Current and voltage measurement chains – AFEs and isolated ADC or sigma-delta modulators feed synchronized current and voltage samples into the control platform for Id/Iq and VDC control.
• Comparators and protection logic – provide fast hardware paths for overcurrent and overvoltage actions, which complement software-based control limits.

Isolated ΣΔ ADCs and the I/V measurement chain

Accurate, synchronized current and voltage measurement is essential for grid-side control, PLL operation and protection. This section describes how isolated sigma-delta channels are commonly used to sense converter-side and grid-side currents, DC-link voltage and phase or PCC voltages, and how their timing characteristics influence the design of control loops.

Current measurement with isolated sigma-delta channels

Grid-side converters typically measure phase currents close to the power module and sometimes at the grid or filter output. These measurements support inner d/q current loops, protection functions and power-quality monitoring. Isolated sigma-delta modulators combine high common-mode transient immunity with compact digital links, simplifying routing between noisy power boards and sensitive control electronics.

• Shunts or current sensors feed AFEs and sigma-delta modulators located near the power stage, where dv/dt and common-mode voltages are highest.
• Bitstreams cross the isolation barrier into the control platform, where digital filters reconstruct synchronized current samples for d/q transformation.
• Shared clocks for multiple sigma-delta channels help guarantee phase alignment between the measured currents, which is critical for Id/Iq accuracy and harmonic analysis.

DC-link and grid voltage measurement

The DC-link voltage is monitored through resistor dividers and AFEs that drive ADCs or sigma-delta modulators. This measurement closes the DC-link voltage loop and underpins overvoltage and undervoltage protection. At the AC side, phase or PCC voltages are acquired via PTs or high-voltage dividers and often share the same isolated sigma-delta architecture used for current sensing.

• DC-link voltage channels must balance input impedance, filtering and insulation ratings while delivering sufficient bandwidth for control and protection actions.
• Phase or PCC voltage measurements provide PLL inputs, support dq transforms and supply data for grid code compliance checks at the point of connection.
• Using a common sigma-delta front end for both current and voltage channels helps align delays and simplifies timing analysis in the control design.

Synchronized sampling, group delay and control impact

Grid-tied control requires that current and voltage samples be synchronized with PWM updates and with each other. Sigma-delta modulators operate at high oversampling rates, and digital decimation filters introduce a finite group delay between the physical signal and the reconstructed samples. This delay must be included in control models to keep d/q current loops and PLLs stable with adequate phase margin.

• Current and voltage channels share clocks and decimation settings so that reconstructed samples correspond to the same effective instant in time.
• Control design treats sigma-delta channels and filters as a known delay element, adjusting loop bandwidths and compensators accordingly.
• Alternative options such as Hall sensors with SAR ADCs or isolated amplifiers offer different trade-offs in delay, noise and layout complexity and are discussed in dedicated current-sensing content.

Grid-tied PLL and synchronized sampling strategy

The grid-side phase-locked loop (PLL) is the reference for the synchronous rotating d/q frame used by the DFIG grid-side converter. It tracks the phase and frequency of the PCC voltage so that current controllers can regulate active and reactive power through Id and Iq components, even during grid disturbances and low-voltage ride-through events.

When the PLL aligns the d-axis with the grid voltage phasor, the Id component primarily reflects active power and the Iq component reactive power or power factor. The quality of this alignment depends on the accuracy, bandwidth and noise performance of the voltage measurement chain, as well as on how well sampling instants are synchronized with PWM updates and with current measurements.

Role of the PLL in grid-side control

• Provide a synchronous rotating frame that allows Id and Iq currents to be controlled independently for active power tracking and reactive power or voltage support.
• Maintain stable operation during grid voltage deviations, frequency offsets and unbalanced conditions so that grid code requirements for power factor and LVRT/FRT behaviour can be met.
• Supply a phase and frequency reference that is consistent with measurements used for current control, protection thresholds and event logging.

Measurement and IC requirements for a grid-tied PLL

The PLL depends on clean, synchronized samples of phase or PCC voltages. Voltage AFEs, isolated sigma-delta modulators or ADCs and the digital filters around them must provide adequate bandwidth and resolution, while keeping group delay and jitter predictable. These constraints directly shape PLL stability and the achievable tracking bandwidth.

• Voltage sensing bandwidth and resolution must support accurate phase estimation in the presence of dips, unbalance and harmonics, without saturating during overvoltage events.
• Synchronous sampling across voltage and current channels is required so that Id/Iq components are computed from samples representing the same instant in time.
• Timing alignment with PWM ensures that control algorithms see currents and voltages that reflect the converter output rather than transient switching edges.
• AFEs and comparators used in the PLL path must tolerate high common-mode voltages and dv/dt while preserving waveform fidelity for phase detection.

PLL implementation options and timing references

Grid-side PLLs can be implemented as software routines on MCUs or DSPs, as dedicated blocks in FPGAs or co-processors, or in combination with external timing references. The choice depends on control complexity, required bandwidth and the need to coordinate multiple turbines or substation-level synchrophasors.

• Software PLLs in MCUs or SoCs suit many grid-side converters and provide flexibility to adapt algorithms and grid code profiles over time.
• FPGA or co-processor based PLLs are used when very high bandwidth, multiple PLL instances or tight integration with fast protection logic is required.
• External synchronized clocks and PTP/TSN timing can provide a common time base for multiple converters and substation devices. Detailed time-synchronization architectures and TSN deployment are addressed in the nacelle controller and SCADA gateway content.

Synchrophasor-grade PMU functions and full power system phasor measurements are outside the scope of this section and are covered in dedicated PMU and grid monitoring topics. Here the PLL is treated as a grid-tied control element that must remain robust across the converter's operating envelope.

Protection, relay and interlock signals at the grid-side converter

The grid-side converter participates in a multilayer protection and interlock chain. Fast electronic protection at the power stage prevents device damage, while relay and contactor drivers operate breakers, contactors and earthing switches. Interlock signals from grid protection devices, rotor-side converters and pitch/yaw safety chains coordinate when and how the grid-side converter may export power or must disconnect.

Fast electronic protection inside the converter

Fast protection layers act within microseconds to milliseconds, starting at the gate drivers and extending through board-level comparators and control firmware. These layers enforce current and voltage limits and provide the first response to faults detected by the measurement chains.

• Gate-driver level protection uses desaturation detection, overcurrent comparators and soft turn-off paths to protect IGBTs or MOSFETs and generate fault signals.
• Board-level comparators and logic monitor shunt, CT and DC-link voltages and currents, issuing hardware gate block or trip signals independently of software.
• Control firmware supervises temperatures, LVRT transitions, energy limits and repeated trip events, updates fault states, manages restart policies and records events in non-volatile memory.

Relay and contactor drive towards breakers and switches

When faults require mechanical isolation, the grid-side converter drives breakers, contactors and earthing switches via dedicated driver ICs and interfaces. These act on command from internal protection logic or from external grid protection and interlock panels.

• Breaker and contactor drivers energize trip coils and contactor coils, monitor coil currents and accept feedback on mechanical position or auxiliary contacts.
• Earthing and grounding switch control interfaces ensure that grounding actions are coordinated with converter shutdown and interlock states.
• The protection chain typically follows a sequence in which internal electronic protection limits current, then relay or contactor drivers open the connection and finally the event is reported to higher-level protection and SCADA systems.

Interlock signals from grid, rotor-side and safety chains

The grid-side converter both issues and receives interlock signals. It must respond to trip and block commands from external grid protection devices, from rotor-side converter alarms and from pitch/yaw safety chains, and it must provide clear status and trip outputs back to those systems.

• Grid protection and interlock panels send trip or block-close commands when upstream protection schemes detect faults or out-of-tolerance conditions. The grid-side converter must immediately stop exporting power and, where required, initiate breaker opening.
• Rotor-side converter alarms indicate conditions such as rotor overcurrent or excitation faults. These alarms drive derating, DC-link protection actions and, if necessary, disconnection from the grid.
• Pitch and yaw safety chains trigger emergency stop conditions. Grid-side control must rapidly reduce active power and coordinate safe disconnection, ensuring that mechanical protection actions are not undermined by continuing power export.

Detailed coordination of substation protection zones, IEC 61850 IED logic and full pitch/yaw safety chain architectures is covered in smart-grid and safety-chain content. This section focuses on the IC-level and board-level roles of the DFIG grid-side converter in the overall protection and interlock chain.

Fault detection, ride-through behavior and event logs

Grid-side converters are required to remain connected and support the grid during low-voltage ride-through and fault ride-through events, while keeping currents within defined limits. Fault detection and ride-through behavior therefore combine fast hardware protection, LVRT/FRT state machines and structured event logging so that both compliance and long-term maintainability are achieved.

LVRT/FRT behavior and current limiting strategies

During voltage dips the grid code usually requires the turbine to remain connected for a defined interval and to provide reactive support instead of immediately tripping. The grid-side converter must shape its current envelope according to LVRT/FRT curves, prioritizing reactive current while keeping the magnitude within equipment and grid limits.

• LVRT state machines detect PCC voltage dips and switch the control into a ride-through mode where current references are constrained by predefined envelopes.
• Current limiters and priority selectors constrain the magnitude of the vector |I| and assign higher priority to reactive current Iq, while Id may be reduced or reversed as required by the grid code.
• Hardware comparators and gate-driver protection still enforce instantaneous overcurrent limits so that no control or firmware error can damage power devices.

A practical design treats LVRT/FRT operation as coordinated layers: fast analog and driver protection for microsecond-scale actions and digital LVRT logic for shaping currents over the full ride-through interval.

Measurement stress and PLL robustness during ride-through

Voltage dips, unbalance and distorted fault waveforms stress the voltage measurement chain and the PLL. The quality of ride-through depends on how well the PLL maintains a meaningful angle reference and how accurately voltage and current channels represent low-voltage conditions within their dynamic range.

• Voltage AFEs and isolated ADC or sigma-delta channels must offer enough resolution and bandwidth at low voltage levels to support phase estimation without excessive quantization noise.
• Sigma-delta decimation filters and ADC sampling paths introduce fixed group delays that must be included in control and PLL models to preserve phase margin when the grid is disturbed.
• PLL algorithms often include ride-through modes that limit bandwidth or freeze the angle when the voltage waveform becomes too distorted to track safely.

Fault management and structured event logging

Fault management links detection, ride-through state machines and event logging into a single framework. Event logs capture what happened before, during and after faults so that certification tests and field issues can be analysed without relying only on SCADA snapshots. This requires appropriate timestamping and non-volatile storage on the converter itself.

• Timestamps derive from RTCs or synchronized clocks, typically with millisecond resolution so that events align with other devices in the turbine or substation.
• Each event record includes an ID, event type, time, source, selected electrical quantities (PCC voltage, currents, DC-link voltage, PLL status, mode flags) and trip or interlock results.
• Local non-volatile memory such as Flash, FRAM or MRAM implements a ring buffer so that the most recent events survive power loss and can be read during maintenance.

From an IC perspective, ride-through logging depends on the combination of a stable time reference, reliable NVRAM, a safe MCU or control SoC and communication interfaces capable of exporting events when requested. Detailed SCADA integration, databases and dashboards are described in nacelle controller and SCADA gateway topics rather than in this converter-focused section.

Mini design stories from DFIG grid-side projects

Short design stories illustrate how converter-level IC choices influence LVRT performance, PLL behaviour and post-fault analysis. Each example ties practical issues in field tests or commissioning back to measurement chains, time bases, non-volatile logging and protection interfaces on the grid-side converter.

Story 1: LVRT test overshoot traced to sampling delay and PLL design

During LVRT certification a grid-side converter passed basic functional tests but repeatedly failed the current envelope requirement. As the programmable grid simulator applied a deep voltage sag, PCC currents showed significant overshoot and oscillation, even though LVRT current limits appeared correctly configured in the controller.

Detailed analysis revealed that the voltage measurement path used isolated sigma-delta modulators with digital decimation filters. The control design had not modelled the full group delay of the voltage and current channels in the PLL and d/q current loops. Under severe voltage distortion the PLL became sensitive to this delay, causing angle jitter and poor Id/Iq decoupling just when LVRT current control needed to be most stable.

The design team reworked the control model to include sigma-delta and filter delays explicitly, adjusted PLL and current-loop bandwidths and refined the voltage AFE to improve low-voltage signal-to-noise ratio. After retuning the controller on a suitable MCU or DSP platform, LVRT tests showed smooth PLL behaviour, controlled current envelopes and compliance with the ride-through curve. The change highlighted the impact of ΣΔ ADC timing and PLL implementation on apparent LVRT performance.

Story 2: Missing local logs complicate root-cause analysis

In an offshore wind farm, a small number of turbines occasionally disconnected from the grid. SCADA views showed generic trip indications and limited snapshots, but on-site inspections often took place hours later when converters had already powered down and restarted. With no detailed local log, it was difficult to determine whether trips originated from upstream grid disturbances, converter settings or protection coordination issues.

The grid-side converter firmware was updated to maintain a structured local event log in non-volatile memory. Each entry captured a timestamp, key electrical quantities around the fault, PLL status, operating mode, trip source and interlock inputs. A small FRAM device or protected Flash region held a ring buffer of recent events, and an RTC or synchronized time source ensured alignment with nacelle and substation logs.

When similar trips occurred after the upgrade, maintenance teams could retrieve converter-side logs directly, correlate them with SCADA data and identify a specific combination of grid voltage dips and conservative protection settings as the root cause. Adjusting thresholds and coordination eliminated the nuisance trips. The experience underlined the value of integrating RTCs, NVRAM and robust communication interfaces into the grid-side converter design.

Design checklist and IC role mapping for the grid-side converter

This checklist supports a final design review of the DFIG grid-side converter board before layout freeze or prototype release. It focuses on DC-link and phase-current sensing, PLL input design, protection coordination and fault logging. The second half maps these requirements to IC roles so that bill-of-material choices remain consistent with the intended control and protection behaviour.

DC-link voltage sensing and insulation requirements

• Confirm that DC-link measurement covers the maximum operating voltage plus surge margin without exceeding the AFE or ADC input range and without overstressing the divider components.
• Check insulation ratings and creepage/clearance for the DC-link measurement path against the applicable DFIG system voltage class and converter standard (for example, IEC 61800 levels).
• Validate that DC-link voltage resolution and accuracy meet both control needs and overvoltage/undervoltage protection thresholds after calibration and temperature drift are considered.

Phase and filter current measurement with isolated sigma-delta channels

• Verify that the number of isolated sigma-delta channels matches the intended sampling points (phase currents, filter currents and any additional monitoring channels).
• Confirm synchronous sampling across all current and PLL voltage channels with a common modulator clock and aligned decimation timing.
• Include sigma-delta and digital filter group delay in Id/Iq current loop and PLL design models and confirm stability and phase margin under LVRT/FRT conditions.
• Ensure that fast overcurrent protection does not depend solely on ADC paths: board-level comparators and gate-driver desaturation should provide microsecond-range current limiting.

PLL input filtering and grid-code coverage

• Review PLL input AFE and filters to ensure adequate signal-to-noise ratio between deep voltage dips and nominal voltage, including realistic grid harmonics and unbalance.
• Confirm that PLL bandwidth and loop filter design are compatible with current loop dynamics and low-voltage ride-through scenarios defined by the target grid codes.
• Check that PLL algorithms include defined behaviour for highly distorted or weak grids, such as limited bandwidth or angle freeze when voltage quality falls below a threshold.
• If external time synchronisation (PTP/TSN, GPS, IRIG-B) is used, verify that PLL and event timestamps can reference the same time base and that loss of the external time source is handled gracefully.

Protection comparators, gate drivers and interlock coordination

• Validate gate-driver desaturation thresholds, soft turn-off behaviour and propagation delays against the IGBT or SiC device safe-operating-area and expected short-circuit conditions.
• Confirm that board-level overcurrent and overvoltage comparators are set with appropriate thresholds, filtering and blanking times so that they discriminate between switching spikes and actual faults.
• Map incoming interlock and trip signals from grid protection panels, rotor-side converters and pitch/yaw safety chains to clearly defined hardware and firmware actions at the grid-side converter.
• Ensure that breaker and contactor drivers include coil current monitoring and auxiliary contact feedback to confirm that mechanical devices have reached their commanded state.

Fault log capacity, power-loss retention and time synchronisation

• Define a consistent event record structure including event ID, type, timestamp, electrical snapshot, operating mode, PLL status and trip or interlock source.
• Size the local non-volatile memory ring buffer to retain at least the last set of critical LVRT/FRT tests and representative fault events for field diagnostics.
• Verify that the chosen NVRAM, FRAM or Flash device supports the expected write frequency and that event logging strategies avoid corruption during power-down or brownout.
• Confirm that the on-board RTC or synchronised clock provides millisecond-level resolution and that loss-of-time-source states are recorded for later correlation with nacelle and SCADA logs.

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The following IC role mapping links these checklist items to functional device categories on the grid-side converter board. Device families are provided as examples; the intent is to keep roles and interfaces clear rather than to lock in a specific vendor.

Measurement chain and isolated sigma-delta converters

• Isolated sigma-delta modulators for phase and filter currents and PCC voltage sampling (for example, AMC13xx, AD740x or Si89xx families) provide high CMTI and a digital bitstream interface.
• Isolated amplifiers and voltage-sense devices (such as AMC12xx or ADuM-based solutions) support DC-link voltage measurement and auxiliary sensing channels.
• Current-sense amplifiers and shunt interfaces condition low-side or high-side shunts so that sigma-delta modulators or ADCs operate within their optimal input ranges.

Gate drivers, fast protection and interlock interfaces

• Isolated gate drivers with desaturation detection, soft turn-off and fault reporting form the first protection layer for IGBTs or SiC devices in two-level or three-level converter legs.
• Board-level comparators and logic devices implement overcurrent, overvoltage and undervoltage thresholds that are independent of firmware and can trigger hardware gate-block signals.
• Relay and contactor driver ICs provide high-side or low-side coil drive, inrush control and diagnostics for grid breakers, contactors and grounding switches.
• Digital isolators and I/O expanders support isolated trip inputs, interlock chains and auxiliary contact feedback paths linking the grid-side converter to upstream protection devices.

Time base, synchronisation and security elements

• Real-time clock devices with backup power sources maintain absolute time across power cycles and provide timestamps for local event logs.
• PTP-capable Ethernet PHYs or TSN switches can be used as time synchronisation endpoints when grid-side logs must align with substation-level measurements.
• Secure elements or hardware security modules can protect configuration and event-log integrity where tamper evidence or signed records are required.

Non-volatile memory, control MCU and optional FPGA

• FRAM, MRAM or robust EEPROM devices store structured event logs in a ring buffer, offering fast writes and high endurance for frequent fault and state transitions.
• Flash memory in the main MCU or as an external device provides additional storage for extended history and configuration, using wear-levelling where needed.
• Control MCUs or DSP/SoC devices implement PLL algorithms, current and voltage controllers, LVRT/FRT state machines, logging logic and communication stacks.
• FPGA or CPLD devices may consolidate fast trip logic, capture timestamps and provide deterministic interfaces between analog comparators, gate drivers and the control MCU.

FAQs about the DFIG grid-side converter

These questions highlight typical design and commissioning concerns around the DFIG grid-side converter. Each answer focuses on measurement chains, PLL behaviour, protection and logging, and where necessary points back to the relevant sections of this page for deeper technical discussion and implementation details.

1. What is the role of the DFIG grid-side converter compared with the rotor-side converter in the overall system?

The rotor-side converter mainly controls torque and rotor currents, shaping mechanical power and reactive support seen from the stator. The grid-side converter regulates DC-link voltage, enforces grid codes at the point of common coupling and manages active and reactive power exchange with the grid, including LVRT/FRT behaviour, protection interfaces and event logging.

See: system role, scope & interfaces.

2. Why is PLL design on a DFIG grid-side converter often more sensitive than on a generic grid-tied inverter?

In a DFIG system the grid-side PLL does not just align a single converter; it also interacts with rotor-side control, mechanical dynamics and grid code LVRT requirements. Poor PLL tuning can destabilise d/q current control, distort reactive support during faults and create compliance issues, so bandwidth, filtering and timing margins are more critical than in simpler inverters.

See: PLL & synchronised sampling.

3. Why do many modern DFIG grid-side designs prefer isolated sigma-delta converters over traditional analog isolation amplifiers?

Isolated sigma-delta converters offer high common-mode transient immunity, precise linearity and a simple digital interface compatible with synchronised sampling across many channels. They avoid drift and offset errors common to analog isolation amplifiers and integrate smoothly into digital control and protection architectures, which improves current and voltage measurement accuracy during dynamic grid and LVRT events.

See: isolated ΣΔ measurement chain.

4. How should measurement delay and control-loop timing be modelled when validating LVRT and FRT behaviour of the grid-side converter?

All significant delays in the sensing and actuation chain—sigma-delta modulation, digital decimation, anti-alias filtering, ADC conversions, CPU execution and PWM updates—should be included in control models. LVRT and FRT simulations need these delays to be represented as discrete-time blocks so that PLL, current loops and LVRT state machines can be tuned with realistic phase margins.

See: control loops, measurement delay, PLL timing.

5. In fault scenarios, how do grid-side converter protection and interlocks coordinate with substation protection relays?

Grid-side protection covers device-level safety, LVRT obligations and immediate converter clearing, while substation relays enforce network-level selectivity and coordination. Converter hardware comparators and gate-driver functions act within microseconds, followed by firmware trips and interlock outputs. Substation relays may send external trips that override converter preferences, so clear prioritisation and feedback paths are essential in both directions.

See: interfaces & grid codes, protection & interlocks.

6. Which faults and events should always be logged both locally in the grid-side converter and centrally in SCADA?

Events that affect safety, grid-code compliance or repeated downtime should have both local and central records. Typical examples include LVRT and FRT entries and exits, overcurrent or overvoltage trips, protection coordination issues, PLL loss-of-lock, breaker misoperations and firmware restarts. Dual logging allows local detail to be correlated with fleet-level patterns in SCADA and asset analytics tools.

See: event logs, design stories.

7. What should be considered when selecting relay and contactor drivers for the grid-side converter?

Driver selection should match coil voltage and inrush current requirements while providing diagnostics, thermal protection and isolation where needed. Integrated high-side switches can reduce EMI and wiring complexity compared with discrete solutions if dV/dt ratings and surge behaviour are verified. Auxiliary contact feedback, fault reporting and compatibility with interlock logic are important for reliable breaker and contactor control.

See: protection & drivers, IC role mapping.

8. What are the trade-offs between implementing the PLL entirely in the main control SoC versus using an FPGA or coprocessor?

Implementing the PLL in the main SoC simplifies software integration and maintenance but shares CPU and memory with other tasks, which can limit complexity or bandwidth in demanding LVRT scenarios. Offloading parts of the PLL to an FPGA or coprocessor enables deterministic timing and advanced algorithms, at the cost of additional devices, toolchains and partitioning effort between domains.

See: PLL strategy, MCU vs FPGA roles.

9. In multi-turbine operation, how tightly must sampling, PLL and control clocks be synchronised between grid-side converters?

Synchronisation requirements depend on grid-code constraints and farm control strategies. Within each converter, sampling and PWM clocks need tight alignment to maintain control performance. Between turbines, phase and time alignment through PTP, TSN or similar mechanisms simplifies fault analysis, coordinated LVRT studies and power-quality assessment, even if hard real-time synchronisation is not always mandated for every application.

See: synchronised sampling, time-stamped logs.

10. When upgrading a DFIG turbine to a newer grid code, which aspects of the existing grid-side hardware typically limit compliance first?

Tighter LVRT/FRT curves, extended reactive support ranges and stricter power-quality requirements often expose limitations in DC-link and PCC voltage measurement accuracy, current sensing bandwidth, PLL robustness and protection thresholds. Logging and time synchronisation capabilities may also prove insufficient for new compliance tests, highlighting the need for upgraded measurement chains, processing headroom and event storage on the grid-side converter.

See: grid-code constraints, measurement chain, design checklist.

11. How can the event log structure make later root-cause analysis of occasional LVRT failures easier?

A useful event log combines consistent record formats, precise timestamps and selected snapshots of key variables. Each LVRT-related event should store voltage, currents, PLL status, operating mode and trip origins, along with sequence numbers and time-source state. A non-volatile ring buffer ensures that several events can be retrieved years later, even after power interruptions.

See: fault logs, logging stories.

12. Before project acceptance, which tests should validate sampling, PLL behaviour and protection logic of the grid-side converter?

Acceptance testing typically includes step and frequency-response measurements of current and DC-link control loops, PLL performance under voltage dips, unbalance and harmonics, and full LVRT/FRT sequences against the target grid code. Protection tests cover overcurrent, overvoltage, desaturation response, breaker and contactor operation and verification that event logs capture sufficient detail for later investigation.

See: control loops, sampling, PLL, protection, design checklist.