HV Isolation & Sensing Building Blocks for the Smart Grid
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This page explains how to turn high-voltage isolation and sensing requirements into practical signal chains that meet safety standards, performance targets and lifetime constraints. It links insulation levels, isolation technologies, sensing and gate-drive architectures, design checklists and examples so that system specifications can be written clearly and implemented with confidence.
What this page solves
High-voltage isolation and sensing form the safety and measurement boundary between harsh primary equipment and sensitive control electronics. This page organizes the role of digital isolators, isolated gate drivers, isolated amplifiers or sigma-delta modulators, and precision references in that boundary.
In a smart grid environment, bus voltages, switchgear and power converters operate at kilovolt levels, while protection logic, metering, automation and communications rely on low-voltage ADCs, MCUs and FPGAs. Properly designed isolation ensures that faults, dv/dt transients and common-mode noise stay on the high-voltage side, while accurate current and voltage information crosses the barrier without distortion.
The focus here is on the hardware building blocks that let signals and control cross that barrier safely: digital isolators for GPIO and high-speed interfaces, isolated gate drivers for IGBT, SiC and GaN switches, isolated shunt and CT front-ends, sigma-delta modulators, and precision reference rails for the measurement domain. Protection algorithms, power-quality DSP and communication stacks are covered on their respective pages and treated here as upstream or downstream consumers of isolated data.
After reading this page, system designers can list all isolation points in a smart grid node, decide which isolation technology and ratings are appropriate, and prepare a clear requirement set for IC and module vendors describing insulation levels, dv/dt immunity, measurement bandwidth and safety standards.
Typical application scenarios
High-voltage isolation and sensing appear in almost every smart grid node, but the stress conditions and signal paths look very different in a protection relay, a SiC-based grid-tied converter and a microgrid controller. The following scenarios highlight where isolation blocks sit in each system and which signals must cross the boundary.
Substation protection and IEDs
In a substation IED, current and voltage are taken from CTs and VTs connected to high-voltage busbars and feeders. Burden resistors and anti-alias filters sit close to the primary equipment, while isolated amplifiers or sigma-delta modulators transfer precise analog or bitstream information into the low-voltage ADC and FPGA domain. Separate isolated channels carry breaker trip commands, coil status and interlocking signals back toward switchgear. dv/dt transients, surge events and ground potential differences around the switchyard make isolation ratings, common-mode rejection and long-term insulation reliability critical.
PCS, SVG and grid-tied inverters
Grid-tied converters, STATCOMs and battery PCS stages use IGBT, SiC or GaN devices switching at high dv/dt and elevated DC-link voltages. Isolated gate drivers bridge the gap between PWM logic in a controller and the floating gates of upper and lower switches, while shunt or CT-based phase and DC-link measurements feed isolated sigma-delta modulators or isolated amplifiers. These blocks must tolerate fast edge rates, high CMTI and strong magnetic and electric fields without corrupting duty cycles or current feedback. Fault signals such as DESAT, overcurrent or overtemperature return through isolated digital channels to let the controller react before devices are damaged.
Microgrids and distributed energy resources
In a microgrid or feeder with multiple DER nodes, each inverter, storage interface and coupling switch sits at a different electrical location, but the microgrid controller needs a coherent picture of power flow, voltages and currents across the whole system. Isolated sensing at each node delivers local measurements into safe low-voltage domains, where data is time-aligned and aggregated. Digital isolators and isolated transceivers protect communication links between DER controllers and the central coordinator. Proper isolation planning prevents a single insulation failure or ground fault at one node from propagating through measurement and control wiring into the rest of the microgrid.
Isolation technology comparison: optocoupler, CMOS and magnetic
Smart grid equipment inherits optocouplers from earlier designs while newer nodes adopt CMOS and magnetic isolation. Optocouplers use LED and phototransistor pairs and are attractive where cost and simplicity dominate, but suffer from LED aging, CTR drift, limited bandwidth and modest dv/dt immunity. CMOS and magnetic isolators integrate transmit and receive functions on-chip, using capacitive or transformer coupling to achieve higher data rates, stable characteristics and tighter channel matching.
In high-voltage protection relays, PCS and SVG stages, and microgrid controllers, the choice of isolation technology directly affects measurement accuracy, protection reliability, thermal budget and long-term lifetime. Each technology occupies a different point in the trade-off between bandwidth, CMTI, aging, power and cost. Optocouplers can still serve slow discrete I/O or legacy field retrofits, while CMOS and magnetic isolation are preferred for high-speed data, sigma-delta bitstreams and fast gate-drive paths exposed to severe dv/dt stress.
The table below compares optocoupler, CMOS and magnetic isolation along the dimensions that matter most in smart grid nodes: data rate, CMTI, stability over time, power and density, safety and lifetime, and typical deployment points. It is intended as a practical mapping tool when deciding how to isolate measurement, control and gate-drive interfaces in metering, IEDs, substation gateways and grid-tied converters.
| Technology | Typical data rate | CMTI & EMC robustness | Aging & drift | Power & channel density | Safety & lifetime | Typical smart grid uses |
|---|---|---|---|---|---|---|
| Optocoupler | kHz to low hundreds of kHz for linear use; higher with tuning but at increased cost and complexity. | Moderate CMTI; susceptible to high dv/dt in fast switching stages and long wiring with large common-mode transients. | LED aging and CTR drift over time, temperature and current stress; long-term accuracy difficult to guarantee. | Requires LED drive current; multi-channel use increases power and heat. Larger footprints for the same channel count. | Can meet basic insulation standards, but lifetime and parametric stability often limit usage in long-life protection gear. | Legacy I/O, simple status inputs and outputs, slow interlocks, retrofits in older panels where bandwidth is low. |
| CMOS digital isolation | Up to tens of Mbps; suited for SPI, PWM, sigma-delta bitstreams and fast GPIO in protection and control nodes. | High CMTI ratings available; designed to tolerate fast switching edges and common-mode disturbances in SiC/GaN stages. | No LED wear-out; stable transfer characteristics over time and temperature when used within rated limits. | Low signal power with compact multi-channel packages; eases thermal design in dense IED and converter control boards. | Certified basic and reinforced insulation options; VIORM and lifetime ratings fit long-service grid equipment. | Protection relay GPIO, ADC and sigma-delta links, SPI and control buses, isolated logic in PCS and STATCOM controllers. |
| Magnetic / transformer isolation | High data rates comparable to CMOS; often combined with isolated power transfer in a single device family. | Very strong CMTI and robustness; well suited for harsh dv/dt at power-switch nodes and noisy substation wiring. | Transformer-based structures with stable parameters; suitable for long-life, high-reliability installations. | Efficient at delivering both data and power; supports compact, high-channel-count designs with integrated isolation. | Can meet stringent insulation and surge requirements; attractive where safety margins and uptime are critical. | Isolated gate drivers, isolated dc-dc power and data paths in PCS, SVG, HVDC auxiliary controls and robust IED links. |
Key isolation parameters: CMTI, RISO, VIORM and switching timing
Isolation datasheets quote many parameters, but a small set dominates smart grid design decisions. Common-mode transient immunity (CMTI) describes how much dv/dt an isolator can tolerate without corrupting its output. RISO summarizes the insulation resistance between primary and secondary sides, affecting leakage current and long-term insulation integrity. VIORM defines the maximum repetitive peak insulation voltage the device can withstand over its lifetime, and switching or propagation timing parameters influence controller stability, channel matching and protection decision latency.
In a protection relay, these parameters underpin differential and distance algorithms and the safe operation of breaker outputs under surge and temporary overvoltage conditions. In PCS and SVG stages, CMTI and timing skew determine whether isolated PWM and feedback paths remain accurate when SiC or GaN devices switch at tens to hundreds of kilovolts per microsecond. For metering, concentrators and microgrid controllers, insulation resistance and VIORM contribute to low leakage currents and predictable behavior over years of operation in harsh environments.
Typical roles of the key parameters in smart grid isolation design include:
- CMTI: ensures isolation channels remain stable when high-side nodes experience rapid dv/dt, such as in SiC bridge legs, long feeders and substation bus switching events.
- RISO: limits leakage current across the barrier, supports safety requirements and indicates the health of insulation materials over humidity, contamination and temperature cycles.
- VIORM: links equipment system voltage to the rated isolation structure and accounts for repetitive peak stress rather than only short-term hipot tests.
- Propagation delay and switching timing: control loop stability, phase alignment between channels and coordination across protection and control decisions.
Designers benefit from treating these isolation parameters as part of the overall system budget: dv/dt capability matched to real switching conditions, insulation resistance and VIORM aligned with grid voltage class and service life, and timing behavior compatible with ADC sampling, PWM updates and relay coordination. The figure below illustrates the CMTI concept by relating a high-side voltage edge to the isolator output stability.
Isolated current and voltage sensing chain design
Isolated current and voltage sensing chains convert primary-side signals at high voltage into accurate, low-voltage measurements for protection and control. Each chain combines a sensor element, analog front-end, isolation stage and digital processing. The optimal topology depends on whether the application is a SiC-based PCS, a protection relay fed from CT/VT, or a bus-voltage monitor in a microgrid or distribution feeder.
For fast current control in inverters and STATCOMs, a shunt and isolated sigma-delta modulator on the high side feed a digital bitstream across the barrier into a decimation filter and FOC controller. In protection and IED designs, CT or VT secondary currents pass through burden and anti-alias networks before reaching an isolated amplifier or isolated ADC that delivers samples to an FPGA or metering MCU. Bus and line voltage measurements rely on carefully designed divider and protection networks followed by isolated voltage AFEs, ensuring that overvoltage and surge conditions do not compromise the isolation barrier or the downstream ADC.
Every chain must balance bandwidth, linearity, common-mode range, insulation ratings and thermal behavior. Smart grid equipment typically operates for many years in harsh environments, so leakage paths, long-term gain drift and saturation behavior under faults need to be considered alongside nominal accuracy. The figure below summarizes three representative isolated sensing chains for PCS current, CT/VT-based protection and high-voltage bus monitoring.
Isolated gate driving for SiC and GaN power stages
SiC and GaN power switches enable higher efficiency and switching speeds in grid-tied converters, STATCOMs and auxiliary HVDC controls, but they demand robust isolated gate driving. The gate drive path must transfer PWM and enable signals across a high dv/dt barrier, source enough current to charge and discharge small, sensitive gate capacitances and provide negative gate bias where needed. It must also detect overcurrent or desaturation events and feed fault status back to the controller through isolated channels.
Two broad approaches are used in smart grid designs. Integrated isolated gate drivers combine the isolation barrier, gate-output stage and protection blocks in a single device, simplifying design and guaranteeing matched CMTI, timing and fault-handling behavior. Discrete approaches use a digital isolator in front of a local gate driver and a separate isolated dc-dc converter, giving flexibility to tailor driver strength, layout and bias rails for specific SiC or GaN modules. In both cases, careful attention to CMTI, loop inductance, Miller clamp strategy and propagation delay matching between upper and lower switches is essential.
The figure below shows an isolated gate drive architecture for a half-bridge phase leg. A controller on the safe side generates PWM and protection commands, isolated channels feed high-side and low-side gate drivers, and isolated power supplies provide the required positive and negative gate voltages. Fault outputs return through isolated paths to allow rapid, coordinated shutdown when desaturation or short-circuit conditions occur on the high-voltage side.
Precision reference and biasing for high-side AFEs
High-side AFEs for shunt-based current sensing, CT/VT interfaces and bus-voltage measurement operate on floating supply islands referenced to high-voltage nodes. A dedicated isolation dc-dc converter feeds a local analog supply tree, typically followed by linear regulators and precision references that define the usable range, noise floor and long-term stability of the measurement chain. Layout choices around these supplies and references determine how much switching noise, dv/dt coupling and temperature rise reach the AFE and converter.
A common structure uses an isolated dc-dc converter to deliver a rough high-side rail, a low-noise LDO to power the AFE or sigma-delta converter core and a precision reference that sets ADC full-scale, bias currents or amplifier reference nodes. The high-side power island must be placed close enough to the sensor and AFE to keep loops short, while remaining physically separated from high dv/dt switch nodes and gate-drive current loops. Poor partitioning often leads to reference ripple, offset drift or sporadic misreadings during switching events, particularly in SiC-based converters and compact protection relays.
Robust designs treat the high-side reference and bias network as a dedicated quiet zone. The isolated dc-dc and gate drivers stay in a noisy power region, decoupling networks and LDOs form an intermediate filter band, and the reference and AFE sit in a compact, thermally managed island. Startup and fault behavior are also important: downstream logic should ignore measurements until high-side supplies and references are within tolerance, and faulted reference or supply conditions should cause the isolated link to present a safe, obvious failure state rather than plausible but incorrect data. The layout below illustrates a recommended partitioning for a high-side AFE reference and bias network.
IC selection guide for isolated sensing, driving and biasing
Component choices for high-side AFEs, isolated gate drivers, digital isolators and precision references are driven by a small set of parameters that recur across smart grid designs. Rather than pointing to specific part numbers, this guide groups parameters by function and explains how each one impacts accuracy, robustness and lifetime. The tables below can be used as a checklist when screening data converters, isolation devices and bias circuits for metering, protection, PCS and microgrid controllers.
For each device category, the first column names a parameter, the second explains why it matters in high-voltage isolation and sensing, and the third suggests typical targets or design notes. Values must be adapted to the system voltage class, insulation standard, control bandwidth and expected service life of the equipment.
Isolated sensing AFE / sigma-delta / ADC
| Parameter | Why it matters in HV sensing | Typical target / notes |
|---|---|---|
| Input type and range | Determines compatibility with shunt voltages, CT burden voltages or scaled bus voltages and defines the usable common-mode window under fault and surge conditions. | Match to maximum expected signal including overload; ensure headroom at temperature and account for CT/VT saturation or bus overvoltage margins. |
| Gain error and INL | Limits metering and PQ accuracy and influences how much calibration effort is required to meet energy or protection standards over the full dynamic range. | For revenue-grade metering, aim for low gain error and INL consistent with targeted class; protection chains can accept higher error if dynamic response is prioritized. |
| Offset and drift | Affects low-current and near-zero voltage measurements, inrush detection and residual current monitoring, especially after years of operation and temperature cycling. | Specify offset and drift so that trip thresholds and billing thresholds remain stable without frequent recalibration over the planned service life. |
| Bandwidth and small-signal response | Determines the ability to capture fault transients, harmonics and fast current changes for protection and control loops such as FOC and STATCOM regulators. | Protection and FOC often require tens of kilohertz of usable bandwidth; metering may accept lower bandwidth but needs predictable phase response for power factor and harmonics. |
| CMTI rating | High dv/dt on switch nodes and long cables can corrupt signals if the isolation path cannot tolerate fast common-mode transients without output glitches or bit errors. | For SiC PCS and STATCOM legs, look for CMTI ratings that exceed worst-case dv/dt with margin; for CT/VT nodes, focus on surge and switching event immunity. |
| Isolation rating and VIORM | Links device insulation capabilities to system voltage class, pollution degree and required lifetime under repetitive peak stress, not just one-time hipot tests. | Choose working insulation and surge ratings consistent with equipment category and installation location, with margin for future uprates or extended service. |
| RISO and leakage current | High insulation resistance and low leakage support safety limits, reduce parasitic ground currents and help preserve long-term dielectric strength in harsh conditions. | Evaluate RISO together with conformal coating, creepage and clearance; avoid devices that rely on marginal insulation resistance to meet safety targets. |
| Supply range, power and temperature | Sets compatibility with high-side supply trees and thermal budgets in crowded substation cabinets and converter modules exposed to elevated ambient temperatures. | Prefer parts that operate over the full expected temperature range with comfortable supply margins and power dissipation that fits within high-side thermal constraints. |
Isolated gate drivers and driver+isolator devices (SiC / GaN)
| Parameter | Why it matters for SiC / GaN stages | Typical target / notes |
|---|---|---|
| CMTI rating | Fast dv/dt on SiC and GaN switch nodes can induce error pulses in gate commands if the isolator and driver cannot reject large common-mode transients. | Seek CMTI ratings that comfortably exceed worst-case dv/dt for the chosen switching frequency and bus voltage, including abnormal operating conditions. |
| Gate drive current (source / sink) | Controls rise and fall times, switching loss, EMI and robustness against Miller-induced false turn-on, especially with high gate charge devices or parallel switches. | Size current capability and external gate resistance to meet switching speed targets while keeping device stress and EMI within acceptable limits. |
| Output voltage range and negative bias | Determines whether the gate can be driven to the recommended positive and negative voltages to avoid spurious turn-on and ensure reliable blocking at high dv/dt. | Verify support for the intended +VG / –VG range and ensure UVLO thresholds prevent operation with marginal gate voltages. |
| Propagation delay and skew | Influences dead-time settings between upper and lower switches, current sharing and timing alignment between phases in multi-leg converters. | Account for worst-case delay and skew when calculating dead-time and inter-phase timing budgets; avoid drivers with poorly specified timing variation. |
| DESAT / overcurrent detection | Enables fast detection of short-circuits or desaturation events at the device, supporting controlled soft turn-off and protecting expensive SiC or GaN modules. | Check DESAT threshold, blanking time and fault propagation path to confirm that protection meets short-circuit withstand time requirements for the switch and topology. |
| Isolation rating, creepage and thermal limits | Gate drivers sit close to hot power modules and high potential differences; insulation and package limits must match creepage, clearance and temperature constraints. | Choose devices with insulation ratings and package geometries aligned with bus voltage, pollution degree and expected ambient and case temperatures near the power stage. |
Digital isolators for data, control and fault links
| Parameter | Why it matters in smart grid nodes | Typical target / notes |
|---|---|---|
| Channel count and direction | Affects PCB routing complexity, pin usage and the ability to group forward and reverse signals for control, data and fault paths. | Select devices with channel configurations that match PWM, SPI, GPIO and fault requirements to avoid excess devices and unnecessary crossings of the isolation barrier. |
| Maximum data rate and pulse width | Limits support for high-speed SPI, sigma-delta bitstreams and short PWM pulses used for fine duty-cycle control and modulation schemes. | Ensure rated data rate and minimum pulse width meet worst-case interface requirements with margin, including future firmware or modulation upgrades. |
| CMTI and EMC robustness | Isolation links must tolerate switching events, surge tests and noise on long substation cabling without introducing bit errors or metastable states. | For links near high dv/dt nodes, favor isolators with high CMTI and proven EMC performance; for low-noise control rooms, requirements may be more relaxed. |
| Propagation delay, skew and jitter | Timing parameters influence relay coordination, synchronized sampling, PTP time distribution and dead-time or phase alignment in drives and converters. | Incorporate worst-case delay and jitter into timing budgets; use low-jitter channels for clocks, timestamps and protection trips that rely on precise timing. |
| Isolation rating and failsafe features | Determines whether the isolator can withstand system overvoltages and defines how outputs behave during power-up, power-down and fault conditions. | Choose insulation levels consistent with equipment category and prefer devices that default to known safe output states when either side is unpowered or faulted. |
High-side LDOs and precision references for biasing
| Parameter | Impact on high-side AFE accuracy and life | Typical target / notes |
|---|---|---|
| Output voltage and tolerance | Sets the supply and reference levels feeding AFEs and ADCs, directly influencing full-scale range, headroom and linear region margins over temperature. | Choose nominal voltages that align with AFE data sheets and allow comfortable headroom above UVLO for all temperature and loading conditions. |
| Temperature coefficient and long-term drift | Governs how measurement gain and offset shift with cabinet temperature and over years of service, which is critical for metering and PQ accuracy. | For revenue-grade metering, aim for low ppm/°C and documented multi-year drift; for protection AFEs, emphasize robustness at high temperature and predictable behavior. |
| Noise and PSRR | Reference and LDO noise contribute directly to low-frequency noise floor and dynamic range, especially in slowly varying signals and RMS computations. | Balance noise targets against bandwidth and quiescent current; ensure combined PSRR and filtering are adequate to clean up noise from the isolation dc-dc converter. |
| Dropout voltage, supply range and quiescent current | Constrains how much margin exists between dc-dc output and regulated rails and affects thermal budget and efficiency in the high-side island. | Select regulators that operate over the dc-dc variation range with sufficient dropout margin and keep quiescent plus load current compatible with high-side temperature limits. |
| Operating temperature and package thermal behavior | High-side bias circuits often sit near hot power components; package thermal resistance and rating influence reliability and drift in this environment. | Favor packages and ratings that accommodate worst-case ambient and self-heating, with mounting and copper areas planned to keep junction temperatures within comfortable limits. |
System safety and insulation levels (IEC / UL)
High-voltage isolation and sensing are not only about CMTI, ADC resolution or bandwidth. Each isolation barrier must also satisfy the system-level safety and insulation requirements defined by IEC and UL standards for measurement, protection and control equipment. The correct target level depends on where the board sits in the power system, which standards apply and whether the barrier is intended to protect people, protect circuitry or just separate noisy domains.
Typical smart grid designs reference a combination of insulation coordination and application standards such as IEC 60664 for creepage and clearance, IEC 61010-2-030 for measurement circuits, IEC 60255 for protection relays and VDE / UL component standards for digital isolators and isolated amplifiers. These documents define working voltage, overvoltage category, pollution degree and test levels that translate into minimum creepage, clearance and insulation types between the high-voltage primary, the low-voltage electronics and user-accessible interfaces. Chip-level “reinforced” ratings cannot be used in isolation; the overall system insulation level is always constrained by the weakest link across devices, PCB layout, connectors and enclosure.
From a system perspective, insulation is categorized as functional, basic, supplementary and reinforced. Functional insulation maintains correct operation but is not intended to provide shock protection. Basic insulation provides a single level of protection between hazardous voltage and accessible parts. Supplementary insulation adds a second independent layer to basic insulation, while reinforced insulation is a single insulation system that offers protection equivalent to basic plus supplementary. For high-voltage primary to low-voltage user interfaces, the target is usually basic plus supplementary, or reinforced. Internal boundaries between two high-voltage domains or between non-accessible logic boards may only require functional or basic insulation, depending on the standard and installation.
Design checklist for HV isolation and sensing requirements
This checklist turns the concepts on this page into concrete requirements that can be shared with IC vendors, module suppliers or internal hardware teams. Each row names a design item that should be documented and gives a short example or guidance. The fields can be copied into a specification or RFQ document and filled with the actual values, topologies and standards for a specific project.
Completing the checklist helps align isolation level, measurement performance, gate drive behavior, power and thermal limits, diagnostics and test expectations from the beginning, reducing the risk of late changes when safety reviews or type tests reveal gaps.
| Item | Example / guidance |
|---|---|
| System voltage class and connection | Describe the grid level and how the equipment connects, for example “11 kV grounded wye feeder, metal-clad switchgear cubicle” or “400 V AC TN-S low-voltage panel for building distribution.” |
| Applicable standards and target categories | List the key safety and performance standards, such as “IEC 61010-2-030 measurement circuits, IEC 60664 insulation coordination, IEC 60255 for protection relays” and any utility-specific specifications. |
| Overvoltage category, pollution degree and altitude | Define insulation environment, for example “OVC III, pollution degree 2, altitude ≤ 2000 m” or adjust creepage and clearance for higher altitude or harsher pollution conditions. |
| Ambient, cabinet and hotspot temperatures | Document worst-case temperatures around isolation components, such as “cabinet ambient up to 70 °C, local hot spots near power modules up to 90 °C, required lifetime at these conditions.” |
| Isolation roles and insulation levels | |
| Isolated measurement channels and insulation type | Enumerate the isolated sensing channels, for example “3 × phase currents, 1 × DC-link current, 3 × phase voltages; each requires reinforced insulation between HV primary and LV controller.” |
| Isolation working voltage and surge target | State the required working insulation and surge withstand, e.g. “working voltage ≥ 800 Vrms with surge capability aligned to system test levels and IEC 60664 requirements.” |
| Internal domains with functional or basic insulation only | Identify boundaries that do not provide user shock protection, for example “insulation between PCS power stage and auxiliary supply board treated as functional; no user access to either side.” |
| Measurement ranges, accuracy and bandwidth | |
| Measurement points and operating ranges | Specify all sensed quantities and limits, such as “phase currents up to 400 A peak, DC-link current up to 600 A, line voltage up to 800 V rms, fault currents up to 20 kA for 50 ms.” |
| Accuracy and linearity targets | Define metering and protection requirements, for example “energy channels class 0.2S equivalent; protection channels error < 5 % from 1–20 × nominal current and within specified phase limits.” |
| Bandwidth and transient response | State required bandwidth, such as “at least 20 kHz for protection transients and harmonics; control loops need X kHz of usable bandwidth with specified phase shift.” |
| Sampling synchronization and latency | Quantify timing constraints, for example “three-phase currents and voltages sampled synchronously within ±100 ns; end-to-end latency from sensor to controller input < 5 μs for PCS current loops.” |
| Gate driving, dv/dt and protection (if power stage is included) | |
| Switch technology and switching frequency | Describe the power stage, e.g. “three-phase 1200 V SiC MOSFET bridge, switching at 40 kHz, expected dv/dt up to 50 kV/μs on phase nodes under worst-case loading.” |
| Gate voltage, dead-time and driver topology | Specify gate levels and requirements, such as “±18 V / –3 V gate drive, integrated isolated drivers preferred, dead-time accuracy ±20 ns and matched propagation delays between legs.” |
| Short-circuit detection and reaction time | Define fault-handling timing, for example “DESAT or overcurrent detection and controlled soft turn-off to complete within 2–3 μs from fault onset for SiC devices.” |
| Power, reference and thermal constraints | |
| High-side supply tree and power budget | Describe isolated supplies and limits, for example “each high-side AFE island fed from X V / Y mA dc-dc; total consumption of AFE + reference + isolator must not exceed Z mA at full temperature.” |
| Reference accuracy, drift and noise requirements | State targets such as “reference drift within ±0.05 % over full temperature range and 10-year life for metering channels; noise compatible with required dynamic range.” |
| Thermal limits for isolation and sensing components | Provide maximum allowable junction and case temperatures and any derating rules for isolators, gate drivers, AFEs and references in the intended mounting locations. |
| Diagnostics, fail-safe behavior and monitoring | |
| Behavior on loss of high-side power or reference | Define expected behavior, for example “on loss of high-side supply or reference, isolated link outputs a clearly invalid or clamped code; no stale but plausible data is allowed at the controller input.” |
| Link health monitoring and error reporting | Request mechanisms such as “status bits or watchdog timeouts for each isolated channel, with CRC / framing error counters and clear fault codes for supervisory logging.” |
| Tests, certification and documentation | |
| Type test levels and certification expectations | Summarize required tests, such as “insulation tests (工频耐压 and impulse levels), EMC tests (IEC 61000-4-2/-4-4/-4-5) without false trips, and provision of relevant UL/VDE certificates with working voltage, creepage and ageing assumptions.” |
Application examples for HV isolation and sensing (PCS and feeder IED)
The building blocks on this page become concrete when mapped into real systems such as power conversion systems and medium-voltage feeder protection relays. The following examples show how isolated current and voltage sensing, digital isolation, gate driving and reference networks are combined into complete signal chains. Each example is written as a miniature design, with typical component classes and indicative device families that can be adapted to specific vendor ecosystems.
Example A – PCS / battery PCS high-side isolation and sensing chain
Consider a three-phase 100 kW battery PCS with an 800 V DC-link and 400 V AC output. The power stage uses 1200 V SiC MOSFETs in a three-phase bridge, with switching frequencies in the 20–40 kHz range and dv/dt values up to tens of kV/μs on the phase nodes. The isolation and sensing chain must measure DC-link current and voltage, phase currents and, in some designs, phase voltages, while also providing robust isolated gate drive for each SiC device. The controller sits on a low-voltage domain that is galvanically separated from the power stage and any user-accessible interfaces.
On the measurement side, DC-link and phase currents are typically sensed using low-ohmic shunts or magnetic sensors. Shunts with Kelvin connections feed high-side AFEs or sigma-delta modulators, which in turn transmit bitstreams or digital words across an isolation barrier. DC-link voltage and phase voltages are obtained from resistor dividers with surge and overvoltage protection networks, then buffered or level-shifted by isolated amplifiers or ADC inputs. High-side AFEs form a quiet island supplied by isolated dc-dc converters, followed by low-noise LDOs and precision references that define the conversion range and noise floor. This island is kept physically and electrically separated from noisy gate-drive loops, as described in the reference and bias section.
The isolation transport layer uses CMOS or magnetic digital isolators rather than legacy optocouplers. High CMTI ratings are required to guarantee error-free operation under fast dv/dt, especially for sigma-delta bitstreams and narrow PWM pulses used for gate control. Each leg of the SiC bridge is driven by an isolated gate driver that combines high source/sink current capability, programmable gate resistors, DESAT or overcurrent detection, Miller clamp and undervoltage lockout. Working insulation, creepage and clearance for these devices are selected to match the installation’s overvoltage category, pollution degree and working voltage as defined by the relevant IEC and UL standards.
Typical component classes and example device families
- Current sensing and sigma-delta front end – low-ohmic current shunts with Kelvin terminals; isolated sigma-delta modulators in the AMC13xx / AD74xx class with high CMTI and reinforced insulation ratings; isolated dc-dc converters providing 5–15 V rails for AFEs and modulators.
- Voltage sensing path – high-voltage resistor divider networks with coordinated surge arresters and RC filters; isolated amplifiers or dedicated voltage-measurement modulators similar to ISO12xx / ADuM7xxx families feeding multi-channel ADCs on the low-voltage side.
- Digital isolation and data transport – multi-channel digital isolators in the ADuM / ISO77xx class for SPI or bitstreams, with CMTI ratings that exceed worst-case dv/dt on phase nodes and timing specifications compatible with current control loop latency budgets.
- Isolated gate drivers for SiC – gate driver ICs in families such as UCC53xx, Si823x or ADuM41xx, providing reinforced insulation, DESAT protection, integrated Miller clamp and ± gate drive capability (for example +18 V / –3 V) to avoid false turn-on during fast transients.
- High-side power and reference network – reinforced isolated dc-dc converters dedicated to AFE and gate-drive islands; low-noise LDOs for analog rails; precision voltage references with low drift for metering-class channels; thermal design to keep junction temperatures within the specified range for the expected cabinet hot spots.
In such a PCS design, the isolation strategy connects directly to earlier sections. The choice of CMOS or magnetic isolation over optocouplers reflects the technology comparison, CMTI and RISO ratings are selected using the parameter discussion, high-side AFE layout follows the reference and bias guidance, and safety levels are aligned with the insulation classifications and design checklist.
Example B – MV feeder protection IED isolated measurement front end
A medium-voltage feeder protection IED is mounted in a metal-clad switchgear cubicle and monitors currents and voltages from CT and VT secondaries. Typical CT ratings are 1 A or 5 A, and VT secondaries around 100–120 V. The IED must support precise RMS and phasor measurements for protection functions such as overcurrent, earth-fault, differential and distance protection, while also providing accurate energy calculation, power quality indicators and time-synchronized sampling for modern substation automation schemes.
The analog front end converts CT and VT signals into stable, bandwidth-limited voltages for high-resolution ADCs. Each phase current passes through burden resistors and anti-alias filters, while phase voltages from VTs are scaled using resistor networks and surge-limiting components. Designers often choose either a centralized multi-channel AFE and ADC on the high-side measurement domain, followed by digital isolation into the logic domain, or a distributed architecture with isolated sigma-delta modulators on each phase transmitting bitstreams to the low-voltage DSP.
Digital isolators between the measurement domain and DSP carry ADC interfaces, status signals and, in some cases, synchronized sampling clocks. Additional isolated channels may be used for trip commands, breaker position feedback and binary inputs. For CT/VT paths that connect indirectly to hazardous primary circuits, insulation is usually specified as basic or reinforced between the measurement front end and the SELV/PELV logic domain, following IEC 61010 and IEC 60255 requirements. Other internal signals entirely contained within the metal enclosure can be treated as functional insulation, provided the switchgear and system design already guarantee user protection.
Typical component classes and example device families
- Current and voltage analog front end – precision burden resistors for CTs; resistor divider networks for VTs; RC anti-alias filters and surge arresters; multi-channel AFEs and 24-bit sigma-delta or simultaneous-sampling ADCs designed for power and energy measurement.
- Isolated sigma-delta modulators (optional) – per-phase modulators in the AMC13xx / AD740x class, allowing direct bitstream transfer to the DSP side where digital filters implement phasor and power calculations.
- Digital isolation to DSP – multi-channel ADuM / ISO77xx-class isolators for SPI or parallel ADC interfaces and control signals, dimensioned for the bandwidth and timing requirements of the protection algorithms and able to withstand surge and EFT tests defined for substation environments.
- Isolated I/O for breaker and status signals – dedicated digital isolators or opto-input interfaces for breaker auxiliary contacts, trip commands and status bits, with insulation levels chosen according to whether these circuits connect to other hazardous domains or remain inside the protected IED enclosure.
- Measurement-side power and references – isolated dc-dc converters feeding the measurement domain; precision references with drift and noise characteristics compatible with energy-accuracy targets; thermal design that considers cabinet temperature rise and self-heating of ADC, AFE and isolators during continuous operation.
In this feeder IED example, insulation levels and creepage/clearance are chosen by working back from system standards, overvoltage category and pollution degree. Isolation technology, CMTI and timing parameters follow the guidelines established earlier in this page, while the final specification of channels, bandwidths and fault-handling behavior can be written directly using the design checklist section.
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FAQ – High-voltage isolation and sensing
These frequently asked questions focus on practical decisions around isolation technology, insulation levels, parameters such as CMTI and working voltage, and how to translate standards into design requirements for smart grid and power conversion equipment. Each answer is written to support engineers who are specifying or reviewing HV isolation and sensing chains.
1. When do I really need isolated sensing instead of simple dividers or non-isolated measurements?
Isolated sensing becomes mandatory when measurement points sit at hazardous or floating potentials relative to earth, or when they connect to remote equipment, communication ports or user-accessible interfaces. If a fault could put dangerous voltage on a low-voltage domain, galvanic isolation is required rather than simple resistor dividers or direct connections.
2. How do I decide whether an isolation barrier must be functional, basic or reinforced?
Functional insulation is chosen when isolation only separates noisy domains and does not provide shock protection. Basic insulation is used when a single barrier protects users or SELV circuits from hazardous voltage. Reinforced insulation or basic plus supplementary insulation is needed when a single failure must not compromise safety in grid-connected equipment.
3. How should I choose between optocouplers, CMOS digital isolators, magnetic isolators and transformers?
Optocouplers are familiar but suffer from CTR ageing, temperature drift and limited bandwidth. CMOS and magnetic digital isolators give better CMTI, timing and lifetime for high-speed interfaces and sigma-delta bitstreams. Transformer-based isolation suits AC or encoded signals and small isolated power stages. Selection is driven by speed, lifetime, CMTI, insulation rating and cost.
4. How much CMTI do I really need for SiC or GaN stages in PCS or STATCOM designs?
Required CMTI depends on DC-link voltage, switching frequency, edge control and layout. Estimate worst-case dv/dt on phase nodes, include margin for tolerances and EMC tests, then select isolation and gate-driver devices whose guaranteed CMTI comfortably exceeds that level, typically by a factor of 1.5 to 2 for robust operation over life and temperature.
5. How do I interpret VIORM and working voltage ratings versus my system voltage and insulation class?
VIORM and working insulation voltage ratings define the maximum repetitive voltage the barrier can withstand for a given insulation class and lifetime model. To map these ratings to a design, combine them with overvoltage category, pollution degree and altitude, and verify that creepage, clearance and impulse test levels match the applicable IEC or UL standards.
6. How should I use RISO and leakage current specifications when designing HV isolation and sensing stages?
Insulation resistance and leakage current affect both safety and measurement integrity. Low insulation resistance or high leakage may increase touch current, create ground loops and introduce offset errors in low-level sensing. Design should consider end-of-life resistance under temperature and humidity, use appropriate creepage, coatings and test limits, and verify that leakage meets safety and accuracy goals.
7. What are the typical bandwidth and latency trade-offs when using isolated sigma-delta modulators?
Isolated sigma-delta modulators offer excellent dynamic range and isolation but introduce group delay through oversampling, filtering and decimation. Higher oversampling and filter order improve noise and linearity but increase latency. Fast current-control loops and some protection functions need tight latency budgets, so filter configuration and digital processing must be chosen with control dynamics in mind.
8. How critical are high-side reference and bias networks for revenue-grade accuracy and long-term drift?
High-side reference and bias networks set the scale, noise floor and drift for isolated AFEs. For revenue-grade metering, reference temperature coefficient, long-term drift and noise translate directly into gain and offset errors. Even for protection-only channels, unstable references can distort thresholds and timing. Supply sequencing, filtering and thermal design must protect these networks from noise and stress.
9. Can one isolated sensing chain serve both revenue-grade metering and fast protection functions?
A single isolated sensing chain can often serve both metering and protection if it has enough dynamic range, bandwidth and stability. In practice, protection may require shorter latency and different filtering than metering. Many designs share one high-performance chain, then split into separate digital paths, while very fast or safety-critical trips still use dedicated, simpler hardware paths.
10. What fail-safe behavior should an isolated sensing or gate-drive link provide on faults or power loss?
Fail-safe behavior should ensure that loss of power, clock or reference does not leave the system in an unsafe state. Sensing links should output clearly invalid codes or known safe values, not stale but plausible data. Gate-drive links must guarantee a defined off state under undervoltage or communication loss, preventing unintended turn-on or shoot-through events in the power stage.
11. How can I estimate insulation lifetime and degradation instead of relying only on single hipot tests?
Insulation lifetime is better assessed using repetitive stress ratings, partial-discharge limits and ageing models than by a single hipot test. Design should operate the barrier well below its maximum working voltage, follow clearance and creepage guidance, and consider temperature, humidity and contamination. Manufacturer lifetime curves and application notes provide models that relate electric stress to expected service life.
12. What key information should I include when writing a requirements document for HV isolation and sensing ICs or modules?
A useful requirements document describes system voltage levels, overvoltage category, pollution degree, relevant IEC or UL standards, measurement ranges, accuracy and bandwidth targets, insulation type, working voltage and CMTI goals. It should also state high-side power and thermal limits, diagnostics and fail-safe expectations, and required EMC, surge and insulation test levels for the final equipment.
