Smart Switch / Dimmer: Zero-Cross, Phase-Cut & Metering
← Back to: Smart Home & Appliances
Core idea: A smart switch/dimmer is a mains-side control device that must deliver stable phase reference (zero-cross), predictable switching (relay/TRIAC/SSR), and trustworthy metering while surviving EMI/thermal stress and wireless coupling. The practical path to reliability is evidence-first engineering: measure two key signals, isolate the real root cause, and apply the smallest fix without scope creep into cloud or lamp-internal driver details.
Definition & Boundary (What This Page Covers)
A smart switch is a mains-rated terminal device that turns an AC load on/off with wired UI and a wireless SoC. A smart dimmer adds phase-cut control driven by a stable zero-cross / phase reference. Practical design hinges on load-compatibility windows, EMC/thermal margins, and metering robustness under waveform distortion. This page focuses on device-level hardware blocks and evidence-based validation.
The boundary is intentionally device-level: the topic is the in-wall switch/dimmer unit (line/load/neutral presence, mains switch element, phase reference, metering front end, and terminal radio). Content stays on measurable engineering constraints (timing jitter, dv/dt immunity, surge/EFT resilience, and temperature derating) rather than platform or ecosystem descriptions.
CoversDevice-level engineering scope
- Switch vs dimmer boundary: on/off vs phase-cut (leading/trailing edge behavior)
- Line/load/neutral implications (power budget, sensing references, safety constraints)
- Switch element choices: relay / TRIAC / SSR (back-to-back MOSFET)
- Zero-cross/phase reference quality and its impact on flicker and control stability
- Metering chain behavior under phase-cut waveform distortion (sampling + calibration)
- Terminal wireless SoC coupling (power/EMI/timing windows) and device-level OTA safety hooks
Does NOT CoverOut-of-scope topics (avoid cross-page overlap)
- Smart luminaire LED constant-current driver design (fixture-side power stage details)
- Smart plug / power strip outlet architectures and downstream corded protection systems
- HEMS panels, branch switching, distribution-level metering, and gateway aggregation
- Matter gateway / home hub routing and cloud/app ecosystem architecture
- Consumer wiring tutorials or step-by-step installation guides
Design success on this page is judged by four measurable outcomes: (1) phase reference stability, (2) load compatibility window, (3) EMC/surge immunity without false triggers or resets, and (4) metering accuracy under phase-cut distortion.
System Partition (AC-to-Radio Functional Chain)
A smart switch/dimmer is best understood as two coupled paths: an energy path that handles mains power and switching stress, and an information path that establishes phase reference, computes the conduction command, and reports metering. Robust designs control the coupling points where dv/dt and RF transmit bursts can corrupt phase reference or sampling windows.
Key modelTwo-path decomposition
- Energy path: AC input → protection/inrush → PSU → switch element → load
- Information path: zero-cross/phase reference → timing/control → trigger/gate → conduction waveform
- Metering path: shunt/CT → AFE/ADC → MCU → power/energy reports (distortion-aware)
- Coupling points: RF transmit bursts, switch dv/dt edges, and PSU ripple entering the phase/sampling reference
The module list below is intentionally evidence-oriented: each block includes a role, the hardest constraint, and a quick measurement that proves health.
Role: absorb surge/EFT/ESD energy and limit inrush so the switch element and PSU remain inside safe stress envelopes.
Hard constraint: clamping and current limiting must not create false triggers or excessive leakage that causes “ghosting”.
Evidence point: after stress events, verify switch-node leakage (Vsw/Isw) and PSU startup waveform repeatability.
Role: generate stable low-voltage rails for MCU/radio, phase reference circuits, and metering under load switching and RF bursts.
Hard constraint: hold-up and UVLO/brownout margins must prevent resets during relay pull-in, phase triggers, and RF TX peaks.
Evidence point: measure 3V3 ripple/sags during worst-case switching + RF TX; correlate with reset reason/BOR counters.
Role: apply on/off control and (for dimmers) enforce phase-cut conduction with controlled dv/dt and manageable thermal loss.
Hard constraint: load compatibility window (hold current, minimum load, dv/dt immunity) must be stable across temperature.
Evidence point: observe switch-node Vsw waveform and conduction angle stability; verify hotspot temperature under rated load.
Role: provide a low-jitter time reference so phase angle commands map to repeatable conduction windows (especially at low dim levels).
Hard constraint: noise/EFT edges must not inject timing jitter that manifests as flicker or audible modulation.
Evidence point: capture ZCD pulse timing distribution and compare to flicker/noise events; validate under EFT stress.
Role: measure current/voltage under distorted phase-cut waveforms and compute RMS/power with controlled phase error.
Hard constraint: phase reference and sampling windows must stay coherent; dynamic range must prevent saturation at inrush edges.
Evidence point: compare low-level vs high-level dim accuracy; check if errors correlate with phase reference shift or ADC clipping.
Role: close the local control loop (input → target level → phase command → verification) and communicate as a terminal radio node.
Hard constraint: RF transmit bursts and OTA operations must not disturb phase capture or metering sampling windows.
Evidence point: correlate RF TX events with ZCD jitter and metering noise; enforce scheduling that protects capture/sampling windows.
Role: maintain reliable operation under temperature rise, conducted/radiated EMI constraints, and mains safety spacing rules.
Hard constraint: losses in TRIAC/SSR/MOSFET and snubber elements must stay within safe surface temperature and derating limits.
Evidence point: log temperature vs load and dim angle; validate no resets/false triggers during surge/EFT profiles.
Zero-Cross & Phase Reference (Where Dimming Precision Starts)
Phase-cut dimming is a timing problem: the conduction window is defined by a phase reference, then converted into a trigger event. When the zero-cross / phase reference is unstable, the trigger angle becomes unstable; at low dim levels the window is short, so even small timing jitter can translate into visible flicker, audible modulation, and distorted metering results.
Implementation familiesFocus on signal quality, not topology
- Divider + comparator: good for predictable delay, but must control noise injection that creates multi-edge false zero-cross events.
- Opto / isolated detect: adds immunity to ground noise, but output edges still need a clean timing signature (no burst or chatter).
- Isolated sensing front end: helps decouple noisy return paths, but timing stability is still governed by edge integrity and filtering.
The evaluation axis is always the same: jitter (edge-to-edge time variation), delay (consistent offset), and immunity (no false triggers under EFT/dv/dt).
Error sourcesConvert “noise” into diagnosable error types
- Jitter-type: edge timing varies cycle-to-cycle (dominant contributor to low-level flicker).
- Offset-type: a consistent delay exists (often calibratable if it does not drift with stress/temperature).
- False-trigger-type: spikes or EMI create extra edges (produces random steps, bursts, or mode-like instability).
Cause: ZCD output shows edge chatter or multiple pulses around the crossing under dv/dt or EFT events.
Symptom: low-level dim jumps, random buzz bursts, or sporadic changes that do not track the setpoint.
Evidence: ZCD output contains extra edges; MCU capture count or timing histogram shows clusters beyond one crossing per half-cycle.
First fix: enforce edge qualification (filter/hysteresis/guard timing) and reduce noise injection along the ZCD return path.
Cause: phase reference edges drift in time because the input waveform is distorted by EMI or coupling from switching edges.
Symptom: “breathing” flicker at low dim levels where conduction windows are narrow.
Evidence: overlay captures show ZCD edges drifting relative to the mains waveform; jitter band widens when switching activity increases.
First fix: isolate the reference from dv/dt injection (layout/return control) and protect capture windows from noisy events.
Cause: a fixed propagation delay exists from true zero-cross to the digital reference edge.
Symptom: brightness mapping is biased (consistent across cycles) rather than randomly flickering.
Evidence: measured delay is stable across cycles and stress; the trigger angle is consistently offset.
First fix: compensate delay in timing logic and keep the compensation stable across temperature and supply ripple.
First 2 measurementsMinimal evidence to locate the fault domain
- Measure #1:
ZCD outedge integrity (single edge per crossing, no chatter, bounded jitter band). - Measure #2:
MCU capture / triggertiming relative to ZCD (confirm if the instability is created before or after capture).
If ZCD is stable but the trigger timing is unstable, the root cause shifts to timing generation or switch-drive coupling. If ZCD itself is unstable, focus remains on reference integrity and immunity.
Phase-Cut Dimming Modes (Leading vs Trailing, Compatibility Evidence)
Leading-edge and trailing-edge phase-cut define where the waveform is chopped, which shifts dv/dt stress and changes how the load current establishes. The practical outcome is a different compatibility window (minimum load, hold current margin, false trigger risk), as well as different EMI and acoustic artifacts. This section stays device-level: the focus is the switch element and its switching behavior.
Core takeawayWhat users search, expressed as engineering constraints
- Leading-edge is commonly paired with
TRIAC: stability depends on hold current margin and dv/dt immunity near the cut edge. - Trailing-edge is commonly paired with
SSR (MOSFET): stability depends on controlled edges, leakage management, and thermal loss. - Both modes require a coherent phase reference; instability at the reference level amplifies flicker risk at low dim levels.
| Mode | Typical switch element | Edge stress focus | Common field symptom | External network / protection | Fast discriminator (evidence) |
|---|---|---|---|---|---|
| Leading-edge | TRIAC (often with gate network) | dv/dt around the chopped leading edge; risk of false trigger and unstable conduction at low levels | low-level flicker, occasional buzz, sensitivity to minimum load / hold current | snubber selection and placement; gate conditioning; surge/EFT protection that avoids extra ZCD edges | observe Vsw: look for unstable turn-on timing vs stable ZCD; check for spurious conduction when dv/dt events occur |
| Trailing-edge | SSR (back-to-back MOSFET) | controlled turn-off edge; leakage and thermal dissipation become primary design constraints | overheat under higher load, “ghosting” risk if leakage/external networks dominate at light loads | edge shaping / gate resistance strategy; leakage control; snubber that does not create excessive standby current paths | observe Vsw and temperature rise: stable timing but high loss points to thermal path; low-load glow points to leakage paths |
Field discriminatorSame load, same conditions, prove the difference with waveforms
- Step 1: keep the same load and mains conditions, then switch between modes (or compare two builds with different switch elements).
- Step 2: capture
Vswand the trigger angle; check if the conduction edge is clean and repeatable. - Step 3: at low dim levels, confirm that the conduction window is stable (no edge wandering that tracks ZCD jitter).
- Step 4: under dv/dt/EFT stress, verify there are no extra conduction events and no resets that disturb timing windows.
Clean edges with unstable brightness typically indicate reference/timing instability; stable timing with excessive heat typically indicates loss/thermal constraints. Persistent low-load glow typically indicates leakage or an external network dominating the load at near-zero conduction.
Relay / TRIAC / SSR: Hard Constraints That Decide the Switch Element
Choosing the switching element is a constraint-matching exercise: the decision is dominated by acoustic requirements, low-level stability, leakage budget, thermal budget, and fail-safe behavior. “Works on the bench” often fails in the field when these constraints are not explicitly verified with evidence.
3-way decision treePick the element by constraints, then validate by evidence
- Need dimming? If no, Relay is typically preferred for low conduction loss and surge robustness.
- Need silent operation? If yes, prioritize SSR; mechanical noise and wear make Relay less suitable.
- Leading-edge vs trailing-edge requirement? TRIAC aligns with leading-edge behavior; SSR enables controlled trailing-edge behavior.
- Ultra-low brightness / very light load? Validate hold current margin (TRIAC) and leakage budget (SSR).
- Thermal budget tight? Verify conduction loss and temperature rise early; thermal constraints often dominate SSR choices.
Strengths: low conduction loss, strong surge tolerance, clear off-state isolation behavior.
Hard limits: discrete on/off action; frequent transitions introduce wear, contact bounce, and acoustic noise. Not suitable for continuous phase control.
Evidence points: contact voltage/current transient during switching, coil drive margin, and temperature rise at rated current.
Minimum peripheralsField-relevant, not exhaustive
- Surge/inrush management appropriate to the load class (to limit contact stress)
- Arc/transient suppression network as required by switching edge behavior
- Over-temperature cutoff strategy when a stuck-on condition is safety relevant
Why low-level can be unstable: low dim levels shorten the conduction window, and the load current can fall below the hold current threshold. The result is missed conduction cycles or abrupt step-like behavior.
False trigger risk: high dv/dt events at the switch node can cause unintended conduction if the drive and snubber strategy is insufficient.
Evidence points: observe Vsw (switch-node voltage) for unintended conduction; correlate low-level flicker with missing or irregular conduction windows.
Minimum peripheralsTo keep timing and immunity coherent
- Gate network sized for trigger current margin across temperature
- RC snubber strategy (as required by dv/dt stress and load behavior)
- Surge path that protects the TRIAC without injecting extra edges into the phase reference
Why heat dominates: conduction loss accumulates as voltage drop × current. Thermal rise becomes a hard constraint and drives derating decisions.
Why leakage matters: off-state leakage (plus external networks) can create a non-zero load voltage that manifests as “ghosting” at very light loads.
EMI sensitivity: edge control is essential; dv/dt and Miller coupling can create unintended turn-on if gate strategy is weak.
Evidence points: temperature rise at steady load, off-state residual load voltage under light load, and Vgs behavior during dv/dt stress.
Minimum peripheralsGate integrity + leakage discipline
- Gate resistance and strong off-state control to prevent dv/dt-induced turn-on
- Leakage-aware external networks (avoid “standby paths” that dominate light-load behavior)
- Thermal path planning (copper, vias, enclosure conduction) and explicit derating rules
Fail-safe focusStuck-on vs stuck-off must be planned, not discovered
- Fail-ON (stuck conducting): highest safety concern. Plan for over-temperature trip, current-limited fault behavior, and a definitive cut-off path (e.g., fuse strategy).
- Fail-OFF (stuck open): availability impact. Detectability and graceful fallback behavior matter for user experience.
- Protection strategy rule: ensure protection does not create false phase-reference events; immunity and safety must be co-designed.
Gate Drive, Snubber & Protection: The Root of Mis-Trigger and Failures
Many “unstable dimmer” field failures are not caused by the switching element alone; they come from dv/dt-driven false turn-on, surge/inductive kick stress, and power-rail dips that disturb timing. The goal here is to assign each protection part a job, then prove stability using a small set of waveforms.
Protection priorityEach part protects a different failure class
- Fuse: final cut-off for sustained overcurrent or catastrophic faults (fail-ON scenarios).
- MOV: absorbs high-energy surge events; clamps the line-level transient energy path.
- TVS: fast clamping for sharp spikes on vulnerable nodes (protect sensitive rails and interfaces).
- NTC: limits inrush so the switch element and PSU are not over-stressed at startup.
- RC snubber: controls
dv/dtand ringing atVsw, reducing false triggers and EMI.
Protection must be coordinated with the phase reference: a “strong clamp” that injects extra edges or ringing into the reference path can trade safety for instability.
Hard constraint: trigger current margin must hold across temperature and supply ripple; otherwise conduction becomes cycle-dependent.
False trigger mechanism: noise or dv/dt coupling can create unintended gate stimulation or disturb the phase reference.
Evidence: compare the trigger waveform to Vsw. If triggers occur without expected conduction (or conduction occurs without triggers), the drive path is not coherent.
Hard constraint: rapid Vsw transitions can lift Vgs via Miller coupling and create unintended conduction.
Evidence: capture Vgs during high dv/dt events. Any rise toward the threshold when “off” indicates weak off-state control.
First fix direction: strengthen the off-state (gate resistance + pull-down strategy) and minimize the high-current loop that creates dv/dt stress.
Hard constraint: snubber must be placed to minimize loop area; otherwise it cannot effectively control ringing and may add heat or leakage-like paths.
Evidence: observe ringing amplitude/frequency at Vsw and correlate with false trigger, flicker bursts, or EMI issues.
First fix direction: place RC close to the switch node, reduce loop area, and verify dissipation under worst-case switching.
Evidence tableSymptom → first waveforms → discriminator → first fix
- Low-level flicker: measure
ZCD out+Vsw. If ZCD edges wander, fix phase reference immunity; if ZCD stable but Vsw irregular, fix drive or dv/dt control. - Random self turn-on: measure
Vsw+gate/Vgs. Conduction without command indicates dv/dt coupling or insufficient snubber/drive integrity. - Reset during switching: measure
3V3 rail+Vsw. Supply dips correlated with switching events indicate PSU margin or energy injection paths that disturb timing.
The minimum set of test points that resolves most cases is: Vsw, gate/Vgs, and 3V3 (plus ZCD out when phase reference is suspected).
Power Supply & Brownout Immunity: Why Random Resets and Mis-Action Happen
Brownouts are frequently triggered by short, high di/dt events: radio transmission bursts, relay pull-in, and phase-trigger switching transients. When a supply rail crosses the brownout threshold or suffers ground bounce, the system can reset, lose timing coherence, or corrupt metering windows.
Minimal power-tree modelKeep the investigation on rails and branches
- AC → PSU (isolated vs non-isolated is a constraint choice: noise coupling, safety boundaries, and cost)
- PSU → 3V3 (digital domain: MCU + radio)
- PSU → 1V8 / AVDD (metering/ADC domain where present)
- Rule: every field symptom must map to a specific rail crossing a threshold or losing a timing window.
Failure shape: short bursts can produce rail droop and ripple that disturb digital timing and analog references.
Evidence: correlate 3V3 ripple/droop with the TX window marker; verify whether reset reason flags indicate brownout.
Failure shape: coil pull-in is a step-like load that can exceed hold-up margin and cause 3V3 droop.
Evidence: capture 3V3 at the MCU pins during pull-in; compare to coil-drive enable and reset flags.
Failure shape: switching transients can inject energy into rails and reference paths, shifting timing windows.
Evidence: capture 3V3 droop together with a trigger marker; validate that the boot reason is consistent with the event timing.
First two measurementsClose the loop: event → droop → reset reason
- Waveform #1:
3V3ripple/droop measured near the MCU/SoC supply pins. - Waveform #2: an event marker (TX burst enable, relay drive, or phase trigger pulse).
- Discriminator: read reset/boot reason (BOR/UVLO-related flags). A droop without BOR implies timing/noise issues; BOR without droop implies measurement point mismatch or ground bounce.
Brownout immunity is a combination of hold-up margin, UVLO/BOR threshold behavior, and startup sequencing. The target is not “no ripple”, but “no threshold crossing and no window corruption”.
Metering Chain & Calibration: Why Readings Drift Under Phase-Cut Loads
Metering in a dimmer is harder than in a simple on/off switch because phase-cut operation creates non-sinusoidal waveforms, short conduction windows, and sharp edges. Accuracy depends on the sensing method, sampling window alignment to phase reference, and calibration stability across temperature and time.
Sensing choiceShunt vs CT determines error shape
- Shunt: strong linearity and simplicity, but sensitive to common-mode handling and thermal drift.
- CT: isolation-friendly, but low-current accuracy and phase error must be controlled for phase-cut waveforms.
- Rule: the more distorted the waveform, the more phase alignment and dynamic range dominate accuracy.
Sampling windowAlign sampling to phase reference (without repeating H2-3)
- Phase reference → sampling window: sampling must follow the conduction window; drifting alignment turns into power error.
- Dynamic range: sharp edges and peaks can saturate ADC/AFE; saturation often shows as “sudden under-read” or step-like errors.
- Evidence: compare a phase marker to the sampling window timing and verify that sense waveforms are not clipped.
Error → evidence tableFast isolation without theory overload
- Offset drift: non-zero power at near-zero load → check zero-current baseline and offset stability over temperature.
- Phase error: PF/active power varies strongly with dim level → check phase reference timing vs sampling window alignment.
- ADC/AFE saturation: readings jump or under-read at certain dim levels → check sense waveform clipping and headroom.
- Gain error: consistent proportional bias across levels → verify gain calibration point and reference stability.
Minimal calibration flowEngineering steps that survive the field
- Step 1: near-zero baseline (offset) capture and validation.
- Step 2: one nominal load point for gain alignment (stable region).
- Step 3: a low conduction-window verification point (dim-level stress point).
- Step 4: temperature rise re-check to bound drift and decide recalibration triggers.
- Step 5: store calibration version and thresholds for field traceability.
Wireless SoC + Local Control: Prevent TX Noise from Ruining Dimming & Metering
Wireless is simultaneously a power transient source, an EMI/clock interference source, and a timing/scheduling source. Coexistence depends on keeping TX bursts from injecting droop into rails, coupling noise into phase reference/ADC paths, or colliding with time-critical capture and sampling windows.
Wireless as a coupling sourceCompare only what matters to hardware stability
- BLE / Thread / Zigbee: typically bursty TX with moderate peaks; risk is timing collisions and rail ripple coupling into sensitive nodes.
- Wi-Fi: typically higher peak current and denser activity; risk is deeper
3V3droop and broader EMI injection. - Rule: differences are evaluated by TX burst profile, injected rail noise, and window collision risk.
Local control loopInput → setpoint → phase angle → waveform verification
- Input: button/knob/touch sampling and debouncing provide stable commands without timing jitter.
- Setpoint: target brightness maps to a phase angle or conduction window budget.
- Control: phase angle generation must remain locked to the phase reference.
- Verify: the switch waveform (Vsw/conduction window) confirms that control is not blind.
Goal: TX bursts must not shift the rail below BOR/UVLO behavior or disturb analog reference domains.
Evidence: 3V3 ripple/droop increases during TX windows; dimming or metering errors correlate with TX time.
Goal: switching return currents and radio burst currents must not flow through phase-reference/ADC return paths.
Evidence: ZCD jitter or ADC noise changes with TX activity, even when the rail looks “OK”.
Goal: TX and compute bursts (including device-level firmware operations) avoid time-critical windows.
Evidence: periodic flicker aligns with TX cadence; noise spikes align with window collisions.
First evidenceClose correlation before changing hardware
- Evidence class A: TX event timestamps (log or GPIO marker aligned to the TX window).
- Evidence class B: ZCD jitter / metering noise change (waveform or statistics) aligned to the same timeline.
- Discriminator: strong time correlation indicates coupling via rails/returns/scheduling; weak correlation indicates a primary issue elsewhere in the phase/drive/metering chain.
EMC, Safety, and Thermal: Device-Level Constraints That Drive Returns
The most common return drivers for dimmers are EMI non-compliance, excess surface temperature, and event-induced lockups after EFT/surge/ESD exposure. The engineering goal is to control the event path (where energy enters and where it flows), respect isolation boundaries, and keep heat sources within derating limits.
- Constrain high dv/dt loops: minimize loop area around the switching element and snubber path.
- Protect sensitive nodes: phase reference and ADC inputs should avoid shared return paths with switching currents.
- Filter placement: filters must interrupt the coupling path, not just add parts.
- Isolation boundary: keep AC side and SELV side clearly separated in layout and routing intent.
- Creepage/clearance: treat as a layout constraint; avoid routing that erodes spacing margins.
- Protection placement: fuse/MOV/TVS must sit where energy is intercepted before sensitive domains.
- Heat sources: switching elements dominate (conduction loss); hotspots must be identified by location, not guesswork.
- Spreading path: copper area, vias, and enclosure conduction determine time constants and peak temperature.
- Derating: design for worst-case load and ambient; avoid operating near thermal cliffs.
Event pathsEFT / Surge / ESD: where energy flows and who gets hit first
- EFT: fast repetitive spikes often disturb phase reference and MCU state; evidence is reset/lockup counters under EFT exposure.
- Surge: higher energy stresses protection and switching elements; evidence is post-event leakage/short checks and thermal anomalies.
- ESD: local injection risks sensitive inputs; evidence is permanent drift or intermittent failures after contact events.
Evidence pointsMeasure what proves the constraint is satisfied
- Thermal: IR thermography + temperature rise curve at worst-case load.
- EFT robustness: reset/lockup counter trend under EFT; correlate with phase reference jitter.
- Surge aftermath: leakage/short checks of the switching element and protection network.
Field SOP: Symptom → Evidence → Isolate → First Fix
This chapter is a repeatable field method for smart switches and dimmers. Each symptom card enforces: (1) two mandatory measurements, (2) a discriminator that closes the evidence loop, (3) the minimum corrective action, and (4) a short “do not chase” list to prevent wasted time.
Minimal toolsFast evidence without over-instrumentation
- 2-channel scope (or 4-channel preferred) with differential probe for mains-side Vsw/Vload.
- DMM / clamp meter for load current and leakage checks.
- IR camera (optional but high ROI) for thermal hotspots and derating validation.
- Log access for reset reason counters (BOR/WDT/POR) and TX event timestamps.
Decision treeOne page routing to the right chain
Symptom Low-level flicker / “breathing” at dim end
- TP-Vsw (switch node / across switch): verify conduction window stability and edge ringing.
- TP-ZCD → timer capture: verify zero-cross timing jitter and false edges during noise.
- Stable ZCD + unstable conduction window → minimum conduction window / hold-current boundary / trigger margin issue.
- Jittery ZCD or false ZCD edges → phase reference is being corrupted (return path / EFT/EMI injection).
- Enforce a minimum conduction window and add a small “no-trigger” guard zone around ZCD edges.
- Reduce dv/dt stress with snubber placement and tighten the high dv/dt loop return.
- Do not start with cloud/app/Wi-Fi diagnostics.
- Do not tear down the lamp driver topology as a first step.
MPN hints Common parts used in stable phase reference & switching
- AC zero-cross optocoupler: onsemi
H11AA1 - Optotriac driver (random phase): onsemi
MOC3023/ VishayVO2223A - TRIAC (insulated tab examples): ST
BTA16-600B, STBTA24-600B
Symptom Buzzing / audible noise (phase-cut related)
- TP-Vload: compare leading-edge vs trailing-edge waveform edges and ringing severity.
- TP-Iload (shunt/CT waveform): check for sharp current spikes and discontinuous conduction.
- Strong ringing / steep dv/dt aligned with noise → edge control/snubber path dominates.
- Discontinuous conduction at low angles → hold-current/minimum-load boundary dominates.
- Adjust snubber damping and keep the snubber loop physically tight to the switching element.
- Increase minimum conduction window or apply a small preload strategy (device-level, not lamp teardown).
- Do not perform lamp magnetic component material analysis.
- Do not change wireless stack settings without evidence correlation.
MPN hints Switching and isolation options
- Optotriac driver (zero-cross type, for on/off switching only): onsemi
MOC3063 - Solid-state relay (optoMOS example, low current loads): Vishay
VO14642A - Relay example: Omron
G5Q-1A(common mains relay family)
Symptom Off-state glow (ghosting)
- Off-state leakage current (DMM/fixture): quantify microamp/milliamp level leakage.
- TP-Vload (off): observe residual voltage/charging behavior across load over time.
- Residual Vload ramps with a time constant → capacitive coupling / EMI network charging dominates.
- Leakage is dominant and varies with switch technology → SSR/optoTRIAC/MOSFET off-state behavior dominates.
- Add a controlled bleeder path (device-level discharge) and verify it does not break safety constraints.
- Reduce unintended charging paths (review EMI capacitors and their placement relative to the load path).
- Do not blame the lamp first; close the leakage evidence loop.
MPN hints Switch element families that influence leakage
- Optotriac families: onsemi
MOC30xx(varies by zero-cross/random-phase) - TRIAC families: ST
BTAxx-600(insulated tab) - OptoMOS families: Vishay
VO146xx, PanasonicAQHseries (load current dependent)
Symptom Random reboot / wireless drop
- TP-3V3 at SoC pins: capture droop/ripple during TX, relay pull-in, and trigger events.
- Reset reason counters (BOR/WDT/POR) aligned to timestamped events.
- 3V3 droop crosses BOR threshold + BOR flag increments → brownout immunity failure dominates.
- No droop but noise correlates with TX windows → return-path/EMI injection or window scheduling collision dominates.
- Increase hold-up margin on the digital rail, tighten decoupling hierarchy, and isolate burst loads.
- Schedule TX bursts away from ZCD capture and ADC sampling windows.
- Do not start with router/cloud troubleshooting.
- Do not increase retries until droop and scheduling are ruled out.
MPN hints Common wireless SoCs and metering ICs used in this class
- Wi-Fi + BLE SoC: Espressif
ESP32-C3 - Thread/Zigbee SoC: Silicon Labs
EFR32MG21, TICC2652R, NXPJN5189 - Energy metering IC: ADI
ADE7953, MicrochipATM90E26, STSTPM32
Symptom EFT upset: false trigger / frequent reset
- TP-ZCD waveform under EFT: check for false edges and timing jitter growth.
- Reset/lockup counters under EFT exposure: correlate with ZCD anomalies.
- ZCD false edges increase → phase reference path is the primary victim (sensitive node / return path).
- Resets without ZCD anomalies → digital rail or MCU I/O injection is primary.
- Harden the ZCD input path (shorter loop, controlled impedance, minimal shared returns) and add targeted filtering.
- Re-check protection placement so EFT energy is intercepted before sensitive domains.
- Do not “fix” with protocol retries or cloud logic.
MPN hints Protection and isolation building blocks
- AC zero-cross optocoupler: onsemi
H11AA1 - MOV family: TDK/EPCOS
B72214series, BournsMOV-14Dseries - Fuse family: Littelfuse
372series (application-dependent)
Symptom After surge: dead, leakage abnormal, or intermittent lockup
- Off-state leakage / short check of switching element and protection network.
- Thermal spot check at light load: abnormal heating often indicates partially damaged silicon.
- Leakage elevated or partial short → switching element or protection part damage dominates.
- Electrical checks pass but firmware unstable → state/rail boundary damage suspected; verify reset reasons and rails.
- Ensure the energy interception order is correct (fuse/MOV/TVS placement) before replacing logic.
- Replace damaged switch/protection components first; re-run leakage + thermal validation.
- Do not start by tuning phase algorithms after a surge event.
MPN hints Common surge-handling families (examples)
- MOV: TDK/EPCOS
B72214family, BournsMOV-14Dfamily - TRIAC: ST
BTA16-600B/BTA24-600B - Optotriac driver: onsemi
MOC3023(random phase)
Symptom Metering error increases (worse at certain dim angles)
- TP-ADC in (or AFE out): check for clipping/saturation during distorted waveforms.
- Phase reference vs sampling window: verify sampling aligns to the intended conduction region.
- Clipping present → dynamic range is insufficient; readings can “jump low” or become non-linear.
- No clipping but PF/power drifts with angle → phase alignment or window strategy dominates.
- Re-center gain/range to remove clipping, then re-check angle-dependent error.
- Adjust sampling windows to avoid ZCD jitter regions and align with conduction windows.
- Do not expand into power-grid theory or certification texts.
MPN hints Metering IC examples commonly used in smart switches
- ADI:
ADE7953(single-phase energy metering IC) - Microchip:
ATM90E26(energy metering IC family) - ST:
STPM32(metering AFE family)
Symptom Relay chatter / false pull-in
- Coil supply waveform: verify pull-in dip and hold margin during events.
- Relay drive control pin: confirm if chatter is commanded or induced (EMI/reset).
- Coil rail droops while control is stable → power path/drive margin dominates.
- Control toggles with noise/reset signs → MCU state/EMI injection dominates.
- Improve coil supply margin and add proper coil transient suppression path.
- Harden input debounce and state latching; verify reset reasons around the chatter timeline.
- Do not assume “relay quality” first without coil rail evidence.
MPN hints Relay family example
- Relay example: Omron
G5Q-1A(common mains relay family)
Symptom Overheat / derating / “too hot to touch”
- IR thermography hotspot map: locate the dominant heat source (switch element, snubber, copper bottleneck).
- Temperature rise curve: time constant indicates whether heat spreading/enclosure conduction is effective.
- Localized switch hotspot → conduction loss and package thermal path dominate.
- Broad board heating fast → thermal spreading/enclosure path is insufficient or derating thresholds are too aggressive.
- Improve copper spreading and thermal vias at the heat source; reduce loss by selecting a better switch element family.
- Validate derating thresholds with repeatable load and ambient conditions, then log thermal events.
- Do not change wireless configuration unless TX-to-thermal correlation is proven.
MPN hints Switching element examples used in mains dimmers
- TRIAC: ST
BTA16-600B, STBTA24-600B - Optotriac driver: onsemi
MOC3023(random phase) - OptoMOS example (low-current SSR): Vishay
VO14642A
NotesUse chapter mapping to prevent scope creep
- Phase reference anomalies map to H2-3; phase-cut mode/load compatibility maps to H2-4.
- Switch element and snubber/drive maps to H2-5/H2-6; rail droop and scheduling maps to H2-7/H2-9.
- Metering error maps to H2-8; EMC/safety/thermal constraints map to H2-10.
MPNs above are representative examples to anchor BOM thinking; actual selection must match rating, isolation, and thermal constraints.
Request a Quote
Smart Switch / Dimmer FAQs (Evidence-first, no scope creep)
Each answer is constrained to device-level evidence: two mandatory measurements, a discriminator, and the smallest first fix. Cloud/gateway and lamp-internal driver teardown are intentionally excluded.
1) Low-end flicker: ZCD jitter or insufficient hold current? → H2-3 / H2-4
First 2 measurements: capture TP-ZCD timing at the MCU timer input and TP-Vsw across the TRIAC/MOSFET to see conduction-window stability. Typical ZCD: H11AA1
Discriminator: if ZCD shows jitter/false edges, phase reference corruption dominates; if ZCD is stable but the conduction window collapses, hold-current/min-window limits dominate.
First fix: add a zero-cross guard band, enforce a minimum conduction window, and tighten snubber placement/return path.
2) Off-state glow (ghosting): SSR leakage or RC/snubber charging? → H2-5 / H2-6
First 2 measurements: measure off-state leakage current and log Vload(off) over time for a charge/ramp signature.
Discriminator: a clear RC time-constant ramp indicates snubber/EMI-cap charging; a mostly constant leakage that changes with switch technology indicates SSR/optoTRIAC leakage dominance.
First fix: add a controlled bleeder path, reduce unintended charge paths, and select a lower-leakage switch element.
3) Buzzing only with some LED lamps: firing angle or dv/dt? → H2-4 / H2-6
First 2 measurements: capture TP-Vload edge ringing (dv/dt) and TP-Iload spike/discontinuity while sweeping firing angle.
Discriminator: noise that tracks ringing severity points to dv/dt control/snubber; noise that peaks in certain angle bands points to angle mapping, minimum window, or discontinuous conduction.
First fix: tune snubber/edge speed first, then adjust low-end angle strategy—without lamp driver teardown.
4) EFT causes reset: weak hold-up or ZCD false triggers reordering software? → H2-7 / H2-3
First 2 measurements: capture TP-3V3 droop during EFT and record TP-ZCD waveform for false edges; read BOR/WDT reset counters.
Discriminator: droop crossing BOR with BOR count increments indicates hold-up/decoupling failure; clean rails but noisy ZCD edges indicates phase-reference injection and timing disorder.
First fix: increase hold-up margin, isolate burst rails, and harden the ZCD input/return path with targeted filtering.
5) After surge, metering drifts: damaged AFE or shifted phase reference? → H2-8 / H2-3
First 2 measurements: check AFE/ADC baseline and noise at steady load, then measure ZCD timing offset/jitter versus the timer capture reference. Metering IC examples: ADE7953, ATM90E26
Discriminator: abnormal offset/noise or early clipping suggests AFE damage; stable AFE but shifted ZCD timing suggests phase-reference alignment drift.
First fix: inspect clamps/sense path, re-calibrate, and re-validate ZCD filtering/layout if timing shifted.
6) Relay occasionally chatters: rail droop or coil flyback path? → H2-7 / H2-5
First 2 measurements: capture coil rail voltage during pull-in and observe the relay drive pin (command vs induced toggling).
Discriminator: coil rail dips/overshoot with a steady drive pin indicates a power path or flyback suppression problem; a toggling drive pin indicates MCU reset/noise injection or state-machine instability.
First fix: correct flyback suppression, boost coil rail margin, and latch state/debounce inputs to prevent chatter loops.
7) Wi-Fi TX increases brightness noise: ground return or sampling-window collision? → H2-9 / H2-3
First 2 measurements: align a TX marker (timestamp or GPIO) with ZCD capture jitter or metering noise statistics. Wi-Fi SoC example: ESP32-C3
Discriminator: if TX coincides with increased ZCD jitter, ground/EMI coupling dominates; if ZCD stays stable but noise rises, the control/sampling window is being interrupted by scheduling.
First fix: schedule TX away from ZCD/ADC windows and improve rail isolation plus return-path control around sensitive nodes.
8) TRIAC self-turn-on: dv/dt or gate-noise injection first? → H2-6 / H2-5
First 2 measurements: capture TP-Vsw dv/dt and ringing at commutation and observe the gate/driver output reference for unintended pulses. TRIAC example: BTA16-600B
Discriminator: self-trigger aligned with high dv/dt spikes points to commutation immunity/snubber; self-trigger aligned with gate pulses points to gate coupling and return-path contamination.
First fix: place RC snubber tight to the TRIAC, add gate series resistance, and clean the gate return/reference.
9) SSR runs very hot: compute conduction loss or inspect thermal path first? → H2-10 / H2-5
First 2 measurements: estimate loss via Vdrop×I (or I²×R for MOSFET SSR) and map hotspots using IR thermography.
Discriminator: if calculated loss matches measured hotspot rise, the switch element choice dominates; if loss is modest but temperature is high, copper spreading, vias, and enclosure conduction are the bottleneck.
First fix: improve thermal spreading first, then consider lower-loss SSR/MOSFET or alternative switch families plus derating.
10) Metering error is large at low brightness: algorithm vs front-end dynamic range? → H2-8
First 2 measurements: check AFE/ADC clipping on voltage/current channels and compare error vs dim angle using a repeatable load.
Discriminator: clipping or compression indicates insufficient dynamic range; no clipping but systematic angle-dependent bias indicates phase alignment/windowing and chopped-waveform handling dominates.
First fix: re-center gain/range first, then align sampling windows to conduction regions and apply angle-aware metering strategy.
11) Flash at power-on: phase initialization/sync or switch-element false trigger? → H2-4 / H2-6 / H2-7
First 2 measurements: capture the 3V3 ramp + reset line and observe TP-Vsw over the first 1–2 AC half-cycles.
Discriminator: unstable reset/rail suggests missing startup blanking and sync discipline; stable rails but unintended Vsw conduction suggests default GPIO state, dv/dt coupling, or gate injection.
First fix: enforce startup inhibit until rails and ZCD are valid, set safe GPIO defaults, and add gate pull-down/RC where needed.
12) How to set minimum load safely: what test matrix finds the safe operating area fastest? → H2-4 / H2-11
First 2 measurements: build a matrix across load type/power × mode/angle × temperature, and record Vsw conduction stability plus ZCD jitter, ghosting leakage, audible noise, metering error, and hotspot temperature.
Discriminator: the safe area is where all metrics remain bounded and repeatable with RF active and after warm-up.
First fix: publish minimum-load limits, enforce low-end angle floors, and route failures into the H2-11 SOP for root cause closure.
