Enterprise Ethernet Switch (L2/L3, PoE PSE, Thermal Control)
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An enterprise Ethernet switch is a “four-loop system” that must close forwarding/queues, control-to-hardware tables, port PHY links, and PoE power/thermals—most “network bugs” are diagnosed fastest by lining up counters, event logs, power rails, and temperature/fan telemetry.
Stable performance comes from predictable buffer/queue behavior, robust PHY and PoE state machines, clean board power sequencing, and an adaptive fan curve that prevents hidden derating.
H2-1 · What an “Enterprise Ethernet Switch” is (and isn’t)
An enterprise Ethernet switch is an access/aggregation platform built to connect many endpoints (PCs, phones, cameras, Wi-Fi APs, IoT controllers) using 1G/2.5G/5G/10G copper or fiber ports, while enforcing L2/L3 policies (VLANs, ACL/QoS) and often delivering power via PoE (PSE). Its engineering “center of gravity” is port-side reliability: predictable forwarding under bursty traffic, stable PoE power, and quiet thermal behavior in closets or offices.
Boundary rule: evaluate an enterprise switch using endpoint + PoE + thermals + observability criteria, not data-center ToR assumptions (ultra-high-speed PAM4 fabrics, deep ECN/PFC tuning, 32×400G class designs).
| Category | Enterprise Ethernet Switch (this page) | Data Center ToR Switch (not this page) | Core Router / WAN Edge (not this page) | Industrial TSN Switch (not this page) |
|---|---|---|---|---|
| Where it sits | Campus access / closet aggregation | Server racks, leaf/spine fabrics | WAN/metro edge, provider aggregation | Factory floor, motion/control networks |
| What “good” means | Stable port behavior, policy correctness, PoE uptime, quiet thermals | Max fabric throughput, low tail latency, large scale east-west traffic | Routing scale, service features, subscriber/session functions | Determinism, bounded latency/jitter, time-aware scheduling |
| Ports | 1G–10G with many PoE endpoints; moderate uplink | 25G/100G/400G class; no PoE endpoints | 10G–400G WAN interfaces, optics-centric | 1G/2.5G w/ TSN features; rugged PHY/isolation focus |
| Buffers/queues | Queue mapping + burst handling for endpoints; “it feels laggy” is common | Congestion management at scale; deep tuning of loss/latency | Queueing for WAN policies, shaping, large service tables | Scheduling and time-aware shaping are dominant |
| Power & heat | PoE PSE is a first-class subsystem; heat couples to PoE load | High ASIC/optics power; chassis airflow engineering | PSU redundancy & thermal; no PoE port power delivery | Often fanless/rugged; temperature & EMC resilience |
| Time sync | Basic NTP/PTP usage possible, not a timing master design focus | May use PTP for leaf/spine telemetry; not timing master focus | Provider timing can be strict (but this is router scope) | PTP/802.1AS is central (TSN scope) |
Practical implication: most “enterprise switch problems” cluster into four buckets: (1) forwarding/queues, (2) port PHY/link integrity, (3) PoE power behavior, and (4) thermal/fan policy. The next chapter locks these into a single reference architecture so later troubleshooting and IC-selection criteria remain scope-correct.
H2-2 · System reference architecture (4 loops you must close)
A reliable enterprise switch is not “one chip + many ports.” It is a set of closed engineering loops that must remain stable under burst traffic, mixed endpoint behavior, and sustained PoE load. The reference architecture below organizes the design into four loops—each with clear goals, observation points, and common breakpoints. This structure keeps later deep dives scope-tight and troubleshooting-friendly.
| Loop | Goal (what “stable” means) | Observation points (what to measure) | Common breakpoints (where it fails) |
|---|---|---|---|
| 1) Data plane Forwarding + queues |
Bounded latency under bursts; drops happen only when expected (policy/congestion) | Per-port Rx/Tx counters, queue depth, drop reasons, tail latency vs load, buffer utilization | Wrong QoS/queue mapping, microbursts overflowing shared buffers, oversubscription at uplinks |
| 2) Control & mgmt Config → tables → stats |
Policies take effect deterministically; stats reflect the real hardware behavior | Table occupancy (MAC/ACL/QoS), CPU load, event logs, config commit status, counter sanity checks | Table/resource exhaustion, stale programming, control-plane stalls, mismatched policy intent |
| 3) PoE power PSE → PD stability |
PDs stay powered across load steps; no oscillation (detect/classify/inrush/MPS) | Per-port power, class, current limit events, inrush timing, undervoltage/overtemp flags | Bad power budget, cable drop, inrush trips, thermal derating of PSE, protection mis-thresholds |
| 4) Thermal Sensors → fan policy |
Hotspots remain below limits with acceptable acoustic profile | Sensor placement readings, fan PWM/tach, ASIC/PSE temps, airflow obstruction detection, derating triggers | Wrong sensor placement, fan curve lag, hotspot not visible to control loop, clogged airflow paths |
The architecture is most useful when it supports fast “bucketization” of field issues. For example:
- “Users complain about lag, but bandwidth looks fine.” Usually a data-plane queue/buffer mapping problem, not a raw throughput limit.
- “Ports flap or renegotiate under heat.” Often PHY/link integrity coupled to thermal policy or localized hotspots.
- “PoE devices reboot randomly.” Commonly a PSE loop issue (inrush/MPS/derating) that masquerades as a network problem.
- “Config seems correct, behavior disagrees.” Control-plane programming or table resource limits; hardware tables and stats must be verified.
H2-3 · Data plane deep dive: switching pipeline, buffers, and latency
Many enterprise complaints sound like “the network is slow,” even when average link utilization looks modest. The most common cause is not raw bandwidth, but where packets wait: queue mapping, buffer behavior, and how microbursts are absorbed (or spilled). A practical way to debug is to view forwarding as a pipeline and ask two questions: which stage is the bottleneck, and which counter proves it.
1) Ingress: MAC/PHY and the “clean link” baseline
Ingress problems often masquerade as switching issues. A link with rising CRC/FCS errors, frequent renegotiation, or unstable energy-efficient modes can look like random loss or jitter. Before tuning queues, verify link integrity and separate “bad bits” from “congestion.”
Evidence: CRC/FCS error counters, link flap counts, Rx alignment errors, per-port retransmit indicators (if exposed).
2) Lookup: L2 learning, L3 forwarding, and policy ordering
The forwarding decision is typically built from multiple lookups: L2 MAC, L3 routes, and then ACL/QoS classification. A frequent enterprise failure mode is “rules conflict”: a more general ACL entry matches earlier than intended, or a QoS class is overwritten by a later stage.
Evidence: hardware hit counters per ACL rule (if available), MAC table activity, route/neighbor table status.
3) Buffers & queues: why latency explodes without obvious drops
Buffers trade loss for delay. When bursts arrive faster than egress can drain, queue depth increases, raising latency even if packets are still delivered. This “buffer hides loss” effect is why users feel lag first (voice, video calls, interactive apps), while drop counters may remain low until the buffer finally saturates.
- Shared buffer: bursts on one set of ports can consume common memory and impact others.
- Per-port buffer: pain is more localized, but uplink oversubscription still creates hot queues.
- Microburst signature: low average utilization, but sudden queue depth spikes + tail latency jumps.
Evidence: queue depth/occupancy, per-queue drops, buffer utilization snapshots, tail latency vs time.
4) Egress scheduling & dropping: who suffers first
Once classified, traffic is placed into queues and drained by a scheduler. Two common policies are Strict Priority and WRR. Strict Priority can protect voice/video, but may starve lower classes under sustained high-priority load. WRR shares bandwidth, but mis-set weights can cause “always-slightly-behind” latency for critical traffic.
Drop behavior is usually tail drop (drop when full) or “early drop” principles (reduce synchronization of loss). For enterprise troubleshooting, the key is identifying which queue drops and whether it aligns with user-impact time.
Evidence: per-queue drop reason counters, scheduler stats, class-to-queue mapping verification.
A fast validation method is to time-align three signals: (1) user-impact timestamp, (2) queue depth or drop counters, and (3) uplink/egress utilization. If latency spikes precede drops, the bottleneck is typically queueing. If drops rise without queue depth visibility, focus on which stage lacks observability (e.g., egress queue mapping).
H2-4 · Control & management plane: why “it forwards” but still feels broken
“It forwards packets” does not guarantee it forwards them as intended. Enterprise switches often fail in subtle ways: policies appear correct in configuration text, but the hardware pipeline behaves differently because table programming did not complete, resources are exhausted, or counters are interpreted with the wrong scope. This chapter treats configuration as a chain: if any link breaks, behavior diverges.
1) Management plane building blocks (just enough to debug)
A typical switch includes a management CPU/SoC that runs the control stack (CLI/API, config database, agents), and communicates with the switch ASIC through interfaces such as MDIO (PHY control), I²C/SPI (platform sensors, PoE controllers), or PCIe/SoC fabric (ASIC programming and telemetry). The exact wiring matters because it defines how quickly policies can be committed and how much state can be observed.
2) The “policy becomes hardware” chain
Treat configuration as a sequence of transformations: intent → structured rules → driver programming → ASIC tables → counters. Breaks in this chain explain most “it looks right but behaves wrong” incidents.
- Intent (CLI/API) → Config agent (validation, ordering)
- Drivers/SDK (compile rules into hardware format)
- ASIC tables (MAC/L3/ACL/QoS/queue map)
- Data-plane behavior (classification, scheduling, drops)
- Stats/telemetry (hit counters, drops, queue depth)
3) Three common “illusions” and how to kill them fast
-
Illusion A: “The ACL is configured, so it must be active.”
Reality: the rule may not be programmed, may be shadowed, or may hit a different class/order.
Fast proof: hardware ACL hit counters and table occupancy. -
Illusion B: “QoS is enabled, but voice still jitters.”
Reality: class-to-queue mapping or scheduler policy differs from intent; strict priority may starve others.
Fast proof: queue mapping dump + per-queue drops/latency alignment. -
Illusion C: “Counters look normal, yet users complain.”
Reality: sampling window or counter scope is wrong; tail latency grows before drops.
Fast proof: time-align user impact with queue depth and drop reason deltas.
4) Practical verification checklist (scope-safe)
When behavior disagrees with intent, verify in this order:
- Table resources MAC/ACL/QoS/queue map occupancy and limits.
- Hit counters Per-rule/per-class counters prove actual matching.
- Queue mapping Confirm DSCP/802.1p/port policy → queue index.
- Drop reasons Which queue dropped? tail drop vs early drop indicators.
- Time alignment User impact timestamp ↔ counter deltas ↔ thermal/PoE events.
H2-5 · Ethernet PHY & port subsystem: link issues that masquerade as switching faults
Many “switching faults” are actually port-layer faults. Link instability, hidden bit errors, and temperature-sensitive margins can look like random packet loss, VoIP jitter, or intermittent client disconnects. The fastest way to avoid misdiagnosis is to treat the port as a chain—connector, magnetics, PHY, MAC, and ASIC ingress—and prove which stage is failing using observable counters and a disciplined A/B comparison method.
1) PHY selection boundary (port-level, scope-safe)
1G links are generally tolerant of older cabling and harsher environments. 2.5G/5G are popular for enterprise AP uplinks because they reuse RJ45 infrastructure, but they expose marginal cabling more quickly. 10G copper increases sensitivity to cable quality and thermal margins, so “works at night, flaps at noon” becomes more likely.
Optical ports can reduce EMI and cable-related impairments, but this section stays at the port level: focus on link state, temperature, and loss indicators without diving into module internals.
2) Failure patterns and the “one-proof” evidence for each
-
Autoneg loop / link flapping → frequent up/down or rate bouncing.
Proof: renegotiation counters + event timestamps (match user-impact time). -
Bit errors without obvious drops → app lag / TCP retransmits, while switch drops stay low.
Proof: CRC/FCS and alignment/symbol errors rising on the affected port. -
Speed/feature mismatch (if applicable) → unstable throughput and “works only at X speed”.
Proof: negotiated capabilities vs expected; error rate changes sharply when forced to a lower rate. -
Temperature-coupled instability → errors/flaps that track chassis or port temperature.
Proof: temperature trend aligned with error bursts or renegotiation spikes.
3) Port A/B comparison method (fast isolation)
Port issues become obvious when a single variable is changed while everything else remains constant. Use the following swaps to isolate root cause quickly:
- Same peer, new cable (rules out fixed cabling defects).
- Same cable, new switch port (isolates port hardware vs path).
- Same port, new peer (isolates peer NIC/AP vs switch).
- Same setup, forced speed (observe if stability returns at 1G).
Always capture counters before and after each swap. “Looks stable” is not a proof; counter deltas are.
4) What to log (minimum useful counter set)
- Link state & renegotiation (up/down and negotiation attempts).
- CRC/FCS and frame errors (dirty link signature).
- Temperature (port or chassis sensor if available).
- Rx/Tx counters at MAC (baseline traffic continuity).
- ASIC ingress counters (to separate link faults from queueing).
H2-6 · PoE subsystem (PSE): detection → classification → power allocation → maintain
In an enterprise switch, PoE is not an accessory—it is a power system tightly coupled to port behavior. Many “network disconnect” complaints are actually PD power reset loops: the device reboots, the link renegotiates, and the event looks like random flapping. Debug PoE as a staged workflow and identify which phase fails: detection, classification, inrush, maintain (MPS), or protection/retry.
1) PSE workflow as phases (purpose → failure signature)
-
Detection checks for a valid PD signature.
Failure: power-on aborts quickly; repeated detect attempts. -
Classification estimates power class and sets a baseline budget.
Failure: unstable class results; PD reboots under load steps. -
Inrush charges PD input capacitance without tripping limits.
Failure: immediate current-limit/port shutdown; more frequent on long cables. -
Maintain (MPS) keeps power on by confirming PD presence.
Failure: periodic dropouts when PD enters low-power states or draws below MPS. -
Protection/Retry handles overcurrent/short/overtemp policy.
Failure: repeating reboot cycles that look like “network is unstable.”
The practical goal is to map a user symptom (reboot/flap) to a single phase using events and counter deltas.
2) 802.3af/at/bt differences (engineering impacts, not standard text)
Higher PoE classes increase delivered power but also increase stress on the platform: power budget (total vs per-port), thermal rise (PSE controller and copper path), and cable voltage drop (especially on long runs). These factors change which phase is likely to fail: budget limits behave like classification/policy faults, while drop and thermal margins behave like inrush/maintain faults.
- Budget → port priority and allocation decisions.
- Thermal → derating and “works cold, fails hot” patterns.
- Cable drop → PD undervoltage during load steps or inrush.
3) LLDP-MED power negotiation (scope-safe) and reboot loops
When LLDP-MED negotiation is inconsistent, the PSE may allocate less than the PD’s real peak demand. The link can appear normal until the PD load increases (AP transmit bursts, camera IR enable, speaker volume rise). Then the PD hits undervoltage, reboots, and the port returns to detection/classification—creating a repeating loop that looks like “Ethernet link flapping.”
Proof: power allocation value changes, repeated PoE events aligned with link renegotiation timestamps.
4) What to capture (minimum PoE evidence set)
- Per-port PoE events detect/class/inrush/MPS/protect transitions.
- Allocated vs measured power budget mismatch clues.
- Port temperature derating triggers.
- 48V rail health if platform telemetry exists; look for dips during inrush.
- Time alignment PoE events ↔ link renegotiation ↔ user complaint time.
H2-7 · PoE power integrity: inrush, cable drop, protection, and thermal coupling
Port-level PoE failures often present as “network instability” because a powered device (PD) reboot forces link renegotiation and service restart. The quickest way to avoid false blame is to treat PoE as an electro-thermal system: cable drop, inrush behavior, per-port protection, and temperature-driven derating can combine into repeatable power cycles even when the switching pipeline is healthy.
1) Why some ports drop power “on the same switch”
Port outcomes differ because the weakest margin is not identical on every path. The most common compounding factors are:
- Cable voltage drop (long runs + high current → lower PD input voltage).
- Concurrent power-up (many ports inrush at once → larger rail dip and limit hits).
- Per-port current limit (different thermal conditions can make the effective limit “feel lower”).
- Hot spots and airflow (local heating triggers derating earlier on specific ports).
A stable data plane can still “feel broken” if PDs are power-cycling underneath it.
2) Protection behavior (port-level scope)
Enterprise PoE ports typically enforce policy through short-circuit / overcurrent / overtemperature actions. These actions often create a time-based pattern that looks like periodic outages:
- Overcurrent → fast shutdown or foldback; may retry after a delay.
- Overtemperature → derating (reduced power) or shutoff until cool-down.
- Retry / backoff → repeating “power on → fail → wait → power on” cycles.
This section intentionally avoids system-level 48V front-end details; focus stays on the PSE-to-port behavior.
3) Practical measurement plan (V/I/T aligned with events)
PoE integrity diagnosis becomes straightforward when three signals are time-aligned with port events:
- Port voltage waveform during detection → inrush → steady state (look for dips and repeats).
- Inrush current profile (peak vs limit; detect if foldback/limit triggers).
- Temperature trend (port/PSE sensor vs derating or shutdown events).
A/B method still applies: same PD + different cable length, same cable + different port, staggered vs simultaneous power-up.
4) Quick interpretation rules
- Fails only at high load → insufficient allocation, excessive cable drop, or thermal derating.
- Fails immediately on power-up → inrush limit or short-circuit detection behavior.
- Fails in hot conditions → heatsink/airflow coupling; derating threshold reached.
- Periodic reboot interval → retry/backoff policy is likely driving the pattern.
H2-8 · Board power architecture: rails, sequencing, and “brownout-like” weird bugs
Enterprise switches rely on many rails feeding different domains: switch ASIC core, high-speed SerDes/PLL supplies, PHY rails, management CPU/SoC, and auxiliary loads such as fans and sensors. When a transient droop or excessive ripple hits a sensitive domain, the system may not fully reboot but can still exhibit brownout-like symptoms—port dropouts, silent error bursts, or partial recovery that feels like a network problem.
1) Typical rail domains (what matters operationally)
Organize rails by “what breaks” rather than by regulator count. Sensitive domains often include:
- ASIC core → functional instability or resets if droop crosses thresholds.
- SerDes / PLL rails → link retrain, error bursts, intermittent port drops.
- PHY rails → port-level flapping that mimics cabling issues.
- Mgmt CPU/SoC → “configured but not applied” or delayed telemetry.
- Aux rails → fans, sensors, PoE control logic (side effects under stress).
2) Sequencing and PG/RESET chain (why bugs look random)
Power-good (PG) and reset policies define whether a disturbance causes a clean reboot, a local-domain reset, or a silent malfunction. A critical failure mode is a “near-threshold” droop: the rail dips enough to corrupt a domain but not enough to trigger the expected reset path, producing inconsistent symptoms and partial recovery.
- Clean reset → obvious reboot, consistent logs.
- Domain reset → ports or PHYs restart while the system stays up.
- Soft error window → no reset, but behavior drifts (retrain, CRC bursts, stalls).
3) Common triggers: load steps and coupling
- Traffic bursts → ASIC/SerDes activity increases sharply, stressing transient response.
- PoE events → control and sensing loads change; thermal and rail interactions appear.
- Fan ramp / thermal control → auxiliary rail steps and airflow transitions shift margins.
- Ground/reference noise → ripple coupling into sensitive PLL/SerDes domains.
The goal is not to “measure everything,” but to find which rail correlates with the symptom in time and repeatability.
4) Verification checklist (waveforms + PG/RESET + logs)
- Ripple and droop capture at key rails during stress conditions.
- Load-step tests (stagger PoE, generate traffic bursts, force fan states).
- PG/RESET timing (order, debounce/hold time, glitch checks).
- Time alignment between waveforms, counters, retrain events, and reboot causes.
H2-9 · Thermal & adaptive fan control: keeping noise low without killing ports
In enterprise switches, thermal behavior is not only about maximum temperature—it is about how quickly hotspots rise, whether sensors see those hotspots, and how fast the fan loop responds. When airflow and fan curves are tuned mainly for acoustics, localized heating around ASICs, dense PHY banks, or PoE PSE stages can trigger derating, port instability, or “random” resets that resemble networking faults.
1) Heat sources and airflow (what really sets margins)
Thermal margins depend on where heat is generated and whether the airflow path efficiently removes it. Typical heat contributors include:
- Switch ASIC — steady base load; sets minimum airflow for reliability.
- PHY banks — dense port area; local heating can raise error rates and retrain risk.
- PoE PSE stage — load-dependent loss; hotspots rise quickly under high PoE utilization.
- PSU exhaust — can elevate inlet air temperature, shrinking the whole chassis margin.
Hotspot location matters more than average chassis temperature—especially near dense ports and PoE stages.
2) Fan control loop: PWM + tach feedback + curve inputs
A practical fan loop has three elements: a command path, a feedback path, and a policy that maps conditions to PWM.
- PWM command — sets target fan drive (airflow intent).
- Tach feedback — verifies real RPM (airflow reality; detects stall and mismatch).
- Control policy — fan curve driven by temperature, power, and optionally PoE load.
Using PoE utilization or power as a “feed-forward” input can reduce lag versus waiting for temperature to rise.
3) Adaptive fan curves (quiet when possible, aggressive when needed)
Fan curves must balance noise and reliability. A robust approach uses multi-input decisions:
- Temperature-driven base curve — stable response for slow thermal changes.
- Power/PoE feed-forward — preemptively increases airflow before hotspots peak.
- Rate limiting — avoids oscillation while keeping response time acceptable.
- Domain weighting — prioritize ASIC/PoE regions over “cool” sensors near inlets.
4) Failure patterns that masquerade as port problems
- Bad sensor placement — hotspots are invisible, so fans stay slow until failure appears.
- Curve lag / heavy filtering — airflow reacts too late; heat shock triggers derating/retrain.
- Tach mismatch — PWM increases but RPM does not; airflow never reaches target.
- Neighbor coupling — PoE-heavy ports heat adjacent areas, impacting nearby PHY stability.
H2-10 · Troubleshooting playbook: isolate forwarding vs PHY vs PoE vs thermal
A reliable troubleshooting process starts by classifying symptoms into buckets and collecting a minimal evidence set. The objective is to avoid expensive “random walks” through logs. The playbook below isolates whether the problem is forwarding/policy, PHY/link, PoE power behavior, or thermal control—then validates the hypothesis using port/time/load triangulation.
1) Bucket the symptom (pick one dominant pattern)
- Packet loss / latency — drops, jitter, queueing delay.
- Link flapping — renegotiation, speed/duplex changes, retrains.
- PoE drop / PD reboot — power cycles, port power events.
- Overheat / reset — thermal alarms, fan anomalies, derating.
2) Minimal evidence set (collect only what moves decisions)
- Port counters — CRC/FCS, errors, resets, renegotiations.
- Queue / drop counters — per-port/per-queue drops and bursts.
- Negotiation & link logs — speed changes, retrain timestamps.
- PoE events — detect/class/inrush/limit/derate/shutdown codes.
- Thermal + fan logs — sensor readings, PWM, tach, alarms.
The key is alignment: evidence must be time-matched to the exact failure window.
3) Fastest localization: port · time · load triangulation
- Port A/B — same PD and cable on different ports; compare behavior.
- Time alignment — align counters/events/alarms to the same timestamp window.
- Load steps — reproduce by controlled bursts: traffic, PoE concurrency, fan states.
4) Decision hints (what evidence points where)
- Queue drops spike, link stable → forwarding/policy/queueing bucket.
- CRC bursts, renegotiations → PHY/link/cabling bucket.
- PoE events repeat, PD reboots → PoE bucket (limit/derate/cable drop).
- Temp rises, PWM lags, tach off → thermal bucket (sensor/curve/airflow).
H2-11 · BOM / IC selection checklist (criteria + part-number examples)
How to use this checklist
The goal is not a “parts catalog”. The goal is to map system outcomes (stable forwarding, clean links, PoE reliability, quiet thermals, and recoverable operations) to measurable IC criteria, then anchor those criteria with a short, searchable part-number shortlist for procurement and design exploration.
11.1 Switch ASIC (forwarding pipeline + tables + counters)
- Forwarding features & scale: L2 learning size, L3 routes, ACL/QoS rule depth, multicast behavior.
- Congestion behavior: queue model, buffer strategy, drop/mark actions (how “latency vs loss” is traded).
- Observability: what counters exist, how granular they are, and whether failures can be proven with data.
- Thermal baseline: steady power sets minimum airflow and acoustic limits.
- Port mix fit: 1G/2.5G/5G downlinks + 10G uplinks/stacking (and the required SerDes count).
- Table budgeting: MAC / LPM / ACL(TCAM) / QoS profiles; verify real partitions under intended feature set.
- Queue model: number of queues per port, scheduler options, and drop policy knobs that match enterprise needs.
- Counter coverage: per-port/per-queue drops, rule hit counters, congestion indicators, and reset-cause visibility.
- CPU/control interface: PCIe/SGMII/internal bus + SDK maturity (controls whether config truly programs hardware).
- “Config set but no effect” → tables too small or feature mix silently changes partitions; no hit counters to prove it.
- “No drops but users complain” → queue/buffer model hides loss as latency; counters not granular enough to pinpoint.
- “Random reboots under PoE load” → ASIC thermal baseline underestimated; fan curve cannot keep margin at full PoE.
- Table utilization snapshots under the full intended feature set (VLANs, ACL/QoS, L3 routes).
- Per-queue drop counters and queue depth/occupancy proxies during controlled congestion tests.
- Thermal steady-state at max forwarding + max PoE + worst ambient; verify no derating/reset margins are crossed.
- Marvell Prestera families (enterprise access/aggregation): 98DX25xx / 98DX35xx (family-level shortlists for enterprise designs).
- Broadcom StrataXGS / Multi-layer switch families: BCM53xx / BCM56xx (common enterprise switching families).
- Realtek L3/L2 switch families: RTL93xx (cost-optimized access switch families).
11.2 Ethernet PHY & port subsystem (link stability + diagnostics)
- Link bring-up success rate: negotiation robustness, marginal cabling tolerance, temperature sensitivity.
- “Looks like switching” failures: CRC bursts, renegotiations, and intermittent errors often originate at PHY/cabling.
- Supportability: without PHY diagnostics, link issues become costly and slow to isolate.
- Speed roadmap: 1G only vs mGig (2.5/5G) vs 10GBASE-T; match AP/campus uplink needs.
- ASIC interface match: SGMII/USXGMII/XFI etc.; avoid “works but flaky” interface mode mismatches.
- EMI & cabling tolerance: error counters under worst-case cable, near-field noise, and temperature corners.
- EEE behavior: verify low-power modes do not create jitter/latency spikes that break real deployments.
- Diagnostics: cable diagnostics, FCS/CRC counters, link flap counters, temperature reporting.
- Long-cable BER/CRC profiling across temperature and PoE load conditions.
- Port A/B swap method: same cable+PD across different ports to separate PHY/port hardware from system effects.
- Correlation tests: link errors vs temperature rise vs PoE draw.
- 1G copper PHY examples: Marvell 88E1512 / 88E1548; Microchip KSZ9131; Realtek RTL8211F.
- mGig / 10GBASE-T examples: Marvell/Aquantia AQR113C / AQR107 (mGig/10G families used in enterprise gear).
11.3 PoE PSE (detection → classification → inrush → maintain → protect)
- PD boot reliability: many “mysterious reboots” are PSE state-machine interactions (inrush, MPS, limits).
- Power budgeting: whether the chassis can run many ports at high draw without oscillation or surprise shutdowns.
- Thermal coupling: PSE losses and port density can set the entire acoustic/thermal envelope.
- Standard level: 802.3af/at vs 802.3bt (Type 3/4), 2-pair vs 4-pair support.
- Per-port telemetry: voltage/current/power measurement accuracy; event codes that explain state transitions.
- Inrush control: programmable limits and timing to survive multi-port concurrent power-up.
- MPS robustness: avoid false drop when PD current is bursty or low average.
- Protection policy: short/overcurrent/thermal actions (graceful derating preferred over hard cycling).
- Concurrent plug-in test: 8/16/24 ports power-up within seconds; check for oscillation and rail sag.
- PD reboot triage: align PoE event log + port voltage waveform + temperature to prove root cause.
- Thermal derating: run worst-case PoE budget until equilibrium; confirm stable maintain mode without cycling.
- TI PSE controllers: TPS23881 (802.3bt class), TPS2388 (802.3at class).
- Analog Devices / Linear Technology: LTC4291 / LTC4292 (multiport PSE controller examples).
- Microchip (Microsemi): PD69210 / PD69220 (multiport PoE/PSE family examples).
11.4 Thermal sensors & fan control (quiet operation without hidden hotspots)
- Channel count: enough tach inputs for redundancy and enough PWM outputs for fan banks.
- Closed-loop capability: tach-verified control prevents “PWM high but RPM low” silent failures.
- Sensor strategy: remote diode vs digital sensors; accuracy and placement to capture ASIC/PoE hotspots.
- Curve behavior: slope limits / hysteresis to avoid oscillation and heat shock.
- Fault handling: fan stall, sensor open/short, overtemp alarms, and safe fallback policies.
- Fan controllers: Microchip EMC2305 (multi-channel PWM+tach); ADI/Maxim MAX31790 (multi-channel PWM+tach).
- Temperature sensors: TI TMP464 / TMP468 (multi-channel temperature monitor examples).
11.5 Power telemetry & fault evidence (PMBus/SMBus monitors)
Many “network” incidents are power integrity or protection events. Without power telemetry and reset-cause evidence, root cause becomes guesswork. The lowest-cost improvement in field support is often better power and event logging.
- What is measurable: rail V/I/P, peak capture behavior, alert thresholds, and log readability.
- Interface fit: PMBus/SMBus/I²C compatibility with management CPU/BMC logging stack.
- Fault correlation: ability to time-align rail droops with ASIC/PoE/thermal events.
- Current/power monitors: TI INA226 / INA228 (I²C power monitor examples).
- Hot-swap / power monitoring: ADI ADM1278 (hot-swap controller with monitoring example).
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H2-12 · FAQs × 12 – Enterprise Ethernet Switch
These FAQs are written to match this page’s scope: enterprise access/aggregation switching with L2/L3, Ethernet PHY ports, PoE PSE behavior, board power integrity, and thermal/fan control. Each question maps to one chapter for fast troubleshooting.
