Camera / Display Bias LDO: AVDD, OVDD, ISP & VCM with Sequencing and OVP

1. Application Scope & Power Context

This page targets camera modules, display / panel small boards, and automotive front / surround view cameras that need clean, ordered bias rails.

These boards are usually area-constrained and already have an upstream DC-DC or PMIC, so the LDO here acts as the final, protected, sequenced bias stage rather than the main power source.

In this page we only cover four rails that are common on camera / display bias trees:

• AVDD (2.8–3.3 V) — analog / imaging domain supply.
• OVDD (5.5–6.5 V typical) — display / panel high-side bias that must ramp slowly.
• ISP / Core (1.2–1.8 V) — digital / image-processor domain, power-down sensitive.
• VCM (mid / bias) — must not jump or overshoot at start-up.

Out of scope here: backlight LED drivers, main TCON / panel power, OIS / AF drivers, and motor / actuator loads — those should go to the corresponding power/driver pages.

2. Bias Rails Breakdown (AVDD / OVDD / ISP / VCM)

2.1 AVDD (2.8–3.3 V)

AVDD is the “always there” rail on camera or display-related modules. Current is moderate, but what matters is that AVDD comes up first or very early, and that the LDO can follow the upstream soft-start without oscillating.

2.2 OVDD (5.5–6.5 V, panel / display bias)

OVDD is the most fragile rail: it is higher-voltage, and it often feeds display gates or panel bias nodes. It must have a controlled ramp (soft-start) and it benefits from OVP / clamp in case the upstream buck drifts or overshoots.

2.3 ISP / Core (1.2–1.8 V)

ISP / core rails are the most power-sequence sensitive: they may need to be present only after AVDD is valid, and they must not power down too early, otherwise the image processor or sensor digital domain can latch or crash.

2.4 VCM (bias / mid-level)

VCM can be internally generated by the LDO or derived from AVDD through an external divider. In either case, the key is no sudden jumps at start-up and a predictable slope, so that the camera / panel front-end is not stressed.

2.5 Rail dependency (who goes first, who goes last)

A practical, low-risk power-up order is: AVDD → (ISP & VCM) → OVDD. AVDD establishes the analog / reference environment, ISP / VCM bring up the logic and bias domains, and OVDD is last because it is the highest and most likely to damage the load if it comes early.

3. Sequencing & Soft-Start Requirements

Camera and display inputs are often designed to see low / analog / bias rails first and to see high / panel rails last. If a high-voltage bias (OVDD) comes before AVDD or before ISP/VCM, it can stress ESD clamps, cause display flashing, or permanently damage a sensor/panel input. That is why power-up order is mandatory, not optional.

3.3 Soft-start goals

Soft-start on bias LDOs is not only for “nice waveforms”; it is for OVDD inrush limiting, for protecting sensors/panels from fast overshoot, and for preventing upstream buck / PMIC from false-faulting. The ramp of AVDD must not be shorter than the delay to ISP/VCM, and OVDD must ramp slowest.

3.4 Power-down / reset order

Power-up order is usually: AVDD → (ISP & VCM) → OVDD. For power-down, do the reverse: OVDD off first, ISP/VCM after, AVDD last. This avoids back-feeding the panel/sensor through high-voltage domains. When the bias LDO integrates PG, configure it so PG goes LOW whenever an OVP or fault is triggered.

3.5 Timing parameters to write into BOM

For cross-brand replacements, add a timing block to the BOM with:

• t_rise per rail (AVDD, ISP, VCM, OVDD);
• t_delay between rail validity (PG) and next EN;
• t_fall / shutdown order;
• PG threshold as % of Vout (e.g. 90%);
• OVP trip if the LDO exposes it (ties into Section 4).

Suppliers can only give pin-to-pin or cross-brand alternatives reliably when these timing numbers are explicit.

4. Over-Voltage Protection / Clamp Strategy

Upstream bucks or PMIC rails can rise higher than intended during cold crank recovery, hot-plug, or reboots. Because OVDD is already a high-voltage bias (5.5–6.5 V), even a small percent overshoot can exceed the panel/sensor input rating. Therefore the bias LDO must cap, fold, or shut the rail down.

4.3 Safe window: V_out × (110–120%)

A practical OVP clamp for bias rails is to trigger between 110% and 120% of the nominal Vout. For AVDD and ISP this is a small margin. For OVDD (6.0 V) this can mean 6.6–7.2 V, so check the panel/sensor spec and write the acceptable window in the BOM.

4.4 Special note for OVDD rails

OVDD should always ramp slowly (soft-start) and never overshoot. For display/panel applications, combining a controlled soft-start with an OVP clamp is the safest way to protect the gate-driver or bias networks.

4.5 Automotive / industrial front cameras

If the upstream supply can see load dump, cold-crank recovery, or long harnesses, consider placing an eFuse / surge / OVP stage before the bias LDO, and then let the bias LDO provide the fine clamp for AVDD / OVDD / ISP / VCM. See the protection / eFuse sibling page for front-end options.

5. Selection Rules per Rail

Do not pick one generic LDO and feed every bias line. Each rail (AVDD, OVDD, ISP, VCM) has its own sequencing, soft-start, and protection expectations. Write these rules into the BOM so cross-brand replacements are still safe.

5.1 AVDD selection points

AVDD (2.8–3.3 V) can accept moderate PSRR (40–60 dB) as long as it obeys the power-up order and fits the module footprint. Always check: EN/PG presence, fixed vs. follow-up soft-start, SOT-23 / DFN 2×2 availability, and automotive temp (−40 to 125 °C) if the camera is in a car.

5.2 OVDD selection points

OVDD (5.5–6.5 V) is the most critical: pick parts with enough input headroom / surge tolerance, built-in soft-start, and explicit OVP / clamp. If the LDO does not document its OVP window, do not put it on a display/panel bias line.

5.3 ISP / core selection points

ISP lines (1.2–1.8 V) must be low-noise, accurate (tight Vout tolerance), and must not bounce at start-up. Check PSRR at 100 kHz to reject buck residue, total noise in µV_rms, and that the soft-start is slower than or aligned with AVDD.

5.4 VCM / bias selection points

VCM rails are small-current but sensitive to being overdriven. Select LDOs that either expose a pin for external reference or clearly state “can be overdriven”. Make sure the ramp slope is controlled so the image / display front-end does not jump on power-up.

5.5 Common fields to document for all four rails

Add these columns to your bias-LDO BOM so suppliers can propose pin-to-pin or cross-vendor parts without breaking the sequence:

6. Brand & Part Pointers

The following table gives real, existing parts from the seven target vendors. Each line states which rail it is best for (AVDD / OVDD / ISP / VCM) and which timing / OVP features it exposes. You can drop this into your “Camera / Display Bias LDO” page and expand parameters later.

7. Validation & Cross-Brand Replacement Checklist

This checklist is for small-batch replacements and cross-brand sourcing of camera / display bias LDOs. The goal is to prove that AVDD, OVDD, ISP, and VCM still follow the intended sequence, soft-start, and OVP behavior after the change.

7.1 Capture start-up waveforms for all four rails

Probe AVDD, ISP, VCM, OVDD at the same time, with the trigger on the upstream buck / PMIC EN. Mark the actual t_rise and PG assertion of each rail. Keep this plot as the “golden” reference before doing a brand change.

7.2 Inject upstream over-voltage and check OVP action

Raise the upstream supply by ~10–15% to emulate buck / PMIC overshoot and watch the OVDD rail. A correct bias LDO must go into its configured OVP mode (clamp, foldback, or shutdown) and pull PG low if the brand / package variant is set to do so.

7.3 Measure startup timing at low / high temperature

Repeat the start-up test at low temp (e.g. −40 °C) and high temp (e.g. +85~105 °C). Some LDOs stretch their t_delay or t_rise at cold, which can break a daisy-chained (PG → EN) sequence. Write the full temperature range into the timing requirements in your BOM.

7.4 Compare PG polarity and thresholds across brands / packages

For each candidate LDO, record: PG polarity (active-high or active-low), PG threshold as % of Vout (e.g. 90–93%), and PG delay after regulation. Package variants (SOT vs. DFN) or different vendors may not match. If your camera / display board enables the next rail from PG, mismatched polarity will cause “no image” issues.

7.5 Submission info for small-batch replacements

When asking for a cross-brand / small-quantity alternative, provide:

• Exact sensor / panel PN and its power-up requirements;
• Target sequence (who first, who last, allowed delays);
• Environment / temperature range (lab, outdoor, in-vehicle);
• Expected quantity / batch size;
• Captures from 7.1 and 7.2 (start-up + OVP).

With this information, we can propose brand-compatible AVDD / OVDD / ISP / VCM LDOs quickly.

Submit BOM (48h)

8. Internal Linking / When Not to Use This Page

This page is only for Camera / Display bias LDO with four rails: AVDD, OVDD, ISP, VCM. If your requirement drifts from this pattern, send users to the following sibling pages to avoid content overlap and to keep SEO signals clean.

8.1 Need higher PSRR / lower noise?

Go to “Imaging / ISP / ToF Low-Noise LDO” if the camera system needs very low µV_rms ripple, ≥80 dB PSRR at 1 MHz, or special sensor-supply filtering. This current page does not go that deep into noise.

Open: Imaging / ISP / ToF Low-Noise LDO

8.2 Want a single PMIC to handle all bias rails?

Go to “Camera / Display Power Combo PMIC” if you prefer an integrated device that already sequences AVDD / ISP / VCM / OVDD internally and exposes only one EN / I²C interface.

Open: Camera / Display Power Combo PMIC

8.3 Need surge / short protection on the front-end?

Go to “LDO + eFuse / Load Switch for Sensitive Rails” if the upstream supply can overshoot, load dump, or short. That page handles the protective front-end that feeds this bias LDO stage.

Open: LDO + eFuse / Load Switch for Sensitive Rails

8.4 Just deciding “LDO or not” after a DC-DC?

Go to “LDO vs DC-DC + Post LDO Decision Tree” if your question is only: “Should I add a post-reg LDO after my buck?” That is a generic decision flow and not specific to camera / display bias rails.

Open: LDO vs DC-DC + Post LDO Decision Tree

How do I bring up AVDD, ISP, and OVDD without stressing the sensor/panel?

Use AVDD → ISP/VCM → OVDD. Drive each rail’s EN from the previous rail’s PG (or a controller) and set soft-start: ~2–5 ms for AVDD/ISP, 5–15 ms for OVDD. Log t_rise, t_delay, and PG thresholds. Keep OVDD last to avoid panel input overstress.

Can I use a normal 3.3 V LDO for OVDD if my panel needs 6 V?

Not recommended. OVDD rails need higher voltage rating, controlled slew, and an explicit over-voltage window (≈110–120% of Vout). Generic 3.3 V LDOs rarely specify these. Only consider it if the upstream stage strictly limits surge and you validate overshoot and PG behavior.

What soft-start time is safe for automotive camera modules?

Use 2–5 ms for AVDD/ISP and 5–15 ms for OVDD, with colder environments requiring longer timing (≈×1.5 at −40 °C). Document “SS_AVDD, SS_ISP, SS_OVDD @ temperature range” in the BOM so suppliers match ramp rates under worst-case conditions.

How do over-voltage clamps interact with PG/RESET signals?

It depends on the LDO. Some assert PG low immediately on OVP; others wait for a delay or a foldback threshold. During validation, inject a 10–15% upstream increase and confirm PG polarity, threshold, and delay while observing the clamp/foldback/shutdown mode.

Which vendors have AEC-Q100 options for camera/display bias?

TI, ST, NXP, and onsemi provide broad AEC-Q100 coverage for camera/display rails; Renesas and Microchip offer industrial/auto options; Melexis focuses on sensor-front-end bias. Specify required grade and temperature range so proposals map to AVDD/ISP/VCM/OVDD correctly.

How to test a cross-brand replacement in 5–10 samples?

Capture start-up of all four rails, perform an upstream over-voltage injection, repeat cold/hot starts, confirm PG polarity/threshold/delay, and note package differences. If results match the golden plots and timing, the small-batch swap is typically safe to proceed.

Do I need a separate LDO for VCM or can I derive it from AVDD?

If VCM current is tiny and not overdriven by an external reference, deriving from AVDD is acceptable. Otherwise use a dedicated LDO that allows external reference overdrive and a controlled ramp, preventing image artifacts at power-up and recovery.

What happens if OVDD rises before AVDD?

Best case: visible flicker or artifacts during boot. Worst case: overstress of panel/sensor inputs when a higher-voltage bias appears before analog rails. Keep OVDD last and tie its EN to the prior rail’s PG to enforce the intended sequence.

Can one LDO feed both ISP and VCM if the current is low?

Sometimes, but only if total current is within limits, noise requirements are compatible, and both rails can share the same ramp and enable timing. Otherwise separate them to avoid cross-coupling and to keep sequencing clear during start-up and shut-down.

How to note sequencing requirements in the BOM for suppliers?

Use explicit lines: “AVDD 3.3 V, t_rise=2 ms, PG@90%”, “ISP 1.8 V, enable on AVDD PG + 1 ms”, “OVDD 6.0 V, SS=10 ms, last, OVP=6.6–7.2 V, PG low on OVP”. State PG polarity and temperature range for timing.

Can I swap TI→ST for camera AVDD without firmware changes?

Possibly, if EN/PG polarity and thresholds match and the ramp time stays within your limits. Validate the four-rail start-up and confirm PG behavior. If MCU sequencing depends on PG edges, check any inversion or delay differences carefully.

Is 6 V display bias too risky for consumer-grade LDOs?

Yes, usually. Choose parts that specify OVDD-class operation: high VIN tolerance, controlled soft-start, and an OVP clamp window. Consumer LDOs rarely document these behaviors. Validate with an upstream surge test and PG monitoring.

What’s a safe PG delay to prevent boot flash?

As a rule, keep PG asserted only after the rail is within regulation and stable for 1–3 ms. For OVDD, longer delays are helpful to avoid visible transients. Always confirm at cold and hot temperatures where delays stretch.

Can I keep WLCSP when migrating to automotive grade?

Sometimes. Many auto-grade parts move to DFN/QFN or leaded packages for reliability and test coverage. If WLCSP is required for space, verify AEC-Q100 grade, PG function, ESD ratings, and solder-joint reliability under temperature cycling.

What screenshots should I send when asking for a replacement?

Provide four-rail start-up captures with time markers, an upstream surge test showing OVP/PG behavior, and a note on temperature. Add BOM lines for voltages, SS times, PG thresholds/polarity, and which rail must be last (OVDD).

Get a Cross-Brand Match in 48 Hours

If you must change the LDO brand but still keep the original camera/display power-up waveform, tell us the sensor/panel PN, the four-rail sequence, and the temperature range. We will match parts from TI, ST, NXP, Renesas, onsemi, Microchip, and Melexis against this page.

For small-batch validation (5–10 pcs), attach the start-up and OVP/PG captures from your current build.

Submit BOM (48h)