Impulse / Surge Withstand for Digital Isolation & Isolated Power
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Impulse/Surge withstand is about locking the test nameplate (kV + Ω + coupling + polarity + repetition) and forcing surge energy to stay in the intended loop so the isolation barrier and downstream rails see controlled stress.
Acceptance is judged by repeatable pass classes (A/B/C) with measurable logs and drift limits, not by “no visible damage”.
Scope Guard (No Cross-Page Overlap)
This page focuses on standardized high-energy transients (1.2/50 µs and 10/1000 µs) and how isolated systems survive them through a controllable surge loop, protection energy sharing, and reproducible lab setup.
✅ In-scope
- Waveforms & meaning: 1.2/50 µs vs 10/1000 µs, typical stress classes, and what each shape stresses.
- Isolation-specific failure paths: barrier coupling, protection-driven stress transfer, and where energy actually dissipates.
- Reproducible test path: coupling/decoupling network, wiring, surge loop, measurement points, pass criteria, and reporting “nameplate”.
Deliverables on this page:
(1) a surge-loop drawing method, (2) a test “nameplate” field set, (3) a pass/fail ladder (A/B/C/D behavior).
⛔ Out-of-scope (Link only)
- Creepage/Clearance, pollution degree, altitude derating — geometry/material & long-term insulation rules. (See: Creepage & Clearance / Pollution Degree)
- ESD and EFT/Burst details — fast-edge upset and recovery mechanisms. (See: EMC/ESD pages)
- Hi-pot and partial discharge (PD) — factory insulation verification and defect screening. (See: Production Test & Docs)
Cross-link rule:
Other pages are referenced with one-sentence reminders only. No restating full explanations to avoid content overlap.
Responsive note: the two cards stack automatically on small screens.
Diagram — Boundary Map (link-only neighbors)
Tip: each neighbor is referenced with a single reminder sentence, then a link—no duplicated deep explanations.
What Counts as Impulse / Surge
In isolation design, impulse/surge withstand is defined by standardized waveforms and a repeatable stress path. The two most common shapes used in lab qualification are 1.2/50 µs and 10/1000 µs. They are not a “real-world lightning replay”; they are a reproducible stress model for comparing protection stacks and surge loops.
Waveform definition (numbers → meaning)
- 1.2/50 µs: a steep voltage impulse; the fast front emphasizes peak electric stress and fast coupling into sensitive nodes near the barrier.
- 10/1000 µs: a long-tail impulse; the tail carries more energy, pushing clamps and protection devices toward their thermal/energy limits.
Key takeaway: 1.2/50 highlights front-driven stress; 10/1000 highlights energy-in-the-tail.
Energy intuition (why protection “ratings” fail)
A surge level is never “just kV”. Energy depends on the full test nameplate: waveform + source impedance + coupling mode + repetition. Long-tail impulses can pass once but fail after repeated shots because the protection stack heats or degrades, shifting clamp voltage and leakage.
Practical rule: if the energy path cannot be described (where power is dissipated), results are likely to be lab-dependent.
Common pitfalls (definition & reporting mistakes)
- Reporting only “kV” without source impedance and coupling mode (incomplete stress definition).
- Treating surge like ESD by stacking small TVS parts while ignoring energy and thermal limits.
- Equating “pass” with “no reset” before defining A/B/C/D behavior criteria.
- Skipping surge-loop drawing and relying solely on component datasheet ratings.
- Changing wiring/ground reference between trials, then calling the results “random”.
Diagram — Waveform overlay (front vs energy tail)
Reading tip: always treat “level” as a nameplate: waveform + coupling mode + source impedance + repetition.
Standards & Stress Classes (Reporting-Grade Definition)
A surge/impulse “level” is only comparable when it is defined as a full test nameplate. The same kV number can represent very different energy stress if the source impedance, coupling mode, polarity, or repetition changes.
What to look for in a standard or test report
- Waveform: 1.2/50 µs or 10/1000 µs defines the time scale of stress (front vs energy tail).
- Level (kV): the nominal open-circuit impulse level—never sufficient by itself.
- Source impedance (Ω): sets peak current and energy; the same kV with different Ω is not the same stress.
- Coupling mode: line-to-line vs line-to-ground changes the loop and where stress lands.
- Polarity (+/−): asymmetry can reveal the true weakest link in a protection stack.
- Repetition: number of shots and interval; repeated stress exposes clamp heating and aging.
- Pass criteria: define what “pass” means (no damage vs functional behavior classes).
Must report (minimum comparable nameplate fields)
Waveform + Level + Source impedance + Coupling
Polarity + Repetition + Pass criteria
Setup notes (CDN type, reference/PE point, wiring length) for reproducibility
Practical interpretation: if any of these fields are missing, the reported “level” is incomplete and cross-lab comparison becomes unreliable.
Red flags (common definition mistakes)
- Only “kV” is specified (no Ω, no coupling): energy stress is undefined.
- Coupling is not stated (L-L vs L-G): the surge loop and stress distribution change.
- Polarity is omitted: asymmetry-driven failures are missed.
- Repetition is ignored: clamp heating and aging are not captured.
- Pass criteria is vague (“no issue”): functional resets vs permanent damage are mixed.
Copy-ready nameplate template (for specs and reports)
Waveform: (1.2/50 µs | 10/1000 µs)
Level: X kV
Source impedance: Y Ω
Coupling: (Line-Line | Line-Ground)
Polarity: (+ | − | both)
Repetition: N shots, interval T
Pass criteria: (A | B | C | D behavior)
Setup notes: CDN type, reference/PE point, wiring length
Diagram — Test nameplate (a level is not a single number)
Use the same nameplate fields across labs to remove ambiguity and make results comparable.
Threat Model for Isolated Systems (How Stress Crosses the Barrier)
Surge stress does not need to “punch through” insulation to cause failure. In isolated systems, stress can cross domains through predictable coupling paths, then land on specific weak points such as primary switching nodes, secondary regulation, or interface receivers. Functional failures (reset, lockup, link drop) are common and should be treated with layered pass criteria.
Path 1 — Barrier capacitance (Cbar coupling)
- Mechanism: fast dv/dt drives displacement current across the barrier capacitance.
- What it hits: secondary ground reference, receiver thresholds, and regulation control nodes.
- What to observe: common-mode jump, sporadic resets, and transient comm errors during the impulse front.
Path 2 — Protection-driven stress transfer (loop pull)
- Mechanism: clamp location and reference point define the surge loop; a wrong reference can pull stress into sensitive nodes.
- What it hits: isolation I/O pins, secondary rectifiers/regulators, and internal clamp structures.
- What to observe: polarity-dependent failures, “works once” behavior, and post-shot leakage drift.
Path 3 — External reference jump (cable / chassis / PE)
- Mechanism: line-to-ground surges depend on the real return path via chassis/PE and cabling geometry.
- What it hits: the entire domain reference level, especially receivers and supply UVLO thresholds.
- What to observe: lab-to-lab variance, sensitivity to wiring length, and different outcomes with the same kV.
Typical weak points (what fails first)
Primary switching node: high di/dt and clamp overshoot can exceed device margins.
Secondary rectifier/regulator: stress can be transferred via coupling and clamp loops into control or rectification paths.
Interface receiver/transceiver: reference jumps and common-mode shifts can cause lockup or link drops without permanent damage.
Isolator input structures: overvoltage or latch-up risk increases if surge loops pull stress into I/O pins.
Key clarification:
“Withstand” does not mean “no reset.” Many failures are functional (reset, lockup, link drop) rather than insulation punch-through, so pass criteria should be layered (A/B/C/D).
Diagram — Coupling paths across an isolation barrier
Interpretation: stress can cross by Cbar, be redirected by clamp loops, or shift both domains via chassis/PE reference—often causing functional failures before hard damage.
Define Pass/Fail Properly (Not Just “No Smoke”)
A surge test outcome must be defined as behavior classes, not a single “pass/fail” word. In isolation designs, functional interruptions (reset, link drop, error bursts) are common without permanent damage, so requirements should state what behaviors are acceptable for the product.
Class A — No functional impact
- Definition: no reset, no link drop, no communication error events.
- Observable: counters remain at baseline; no state-machine interruption.
- Evidence: reset reason = none; link-drop = 0; CRC burst = 0.
Class B — Auto-recover (self-healing)
- Definition: transient errors occur, but the system returns to normal automatically.
- Observable: brief CRC burst or short link glitch; recovery within a defined window (X ms).
- Evidence: error counters spike then settle; no manual action required.
Class C — Manual recovery required (no permanent damage)
- Definition: latched fault or non-recoverable state until a manual reset/power-cycle.
- Observable: persistent link-down, stuck fault flag, or supply rail brownout latch.
- Evidence: latched fault set; POR/UVLO/OT logs indicate intervention requirement.
Class D — Permanent damage (fail)
- Definition: the device cannot return to baseline operation or shows unacceptable parameter drift.
- Observable: dead channel, abnormal leakage, stuck short/open, unstable regulation after recovery.
- Evidence: post-shot functional test fails; leakage/clamp level exceeds thresholds (X/Y/N).
Black-box signals to log (minimum set)
Power & protection: UVLO, OT, SC, POR/reset reason, brownout flags, latched fault + clear policy.
Link & data integrity: link-drop / retrain count, CRC burst count, error counter window definition.
Context fields: waveform + kV + Ω + coupling + polarity + shot index + repetition interval (nameplate snapshot).
Common mistake: treating any reset as an automatic fail.
Correct approach: classify the behavior (A/B/C/D) based on the product requirement and recorded evidence.
Diagram — Pass criteria ladder (A → D behavior)
A/B/C/D classes align acceptance with product requirements while keeping evidence-based, reproducible logs.
The Only Way to Predict Outcomes: Draw the Surge Loop
Model a surge as a high-energy pulse source with a defined source impedance and coupling network. Then do one practical action: draw the current loop. The main loop shows where energy is dissipated, while coupled branches explain functional interruptions that appear without permanent damage.
Step 1 — Draw the loop (generator → CDN → DUT → return)
- Mark the reference point (PE/return) explicitly.
- Separate line-to-line and line-to-ground loops (different closures).
- Keep wiring length in mind: longer leads change loop impedance and results.
Step 2 — Mark dissipation points (where energy goes)
Clamp: MOV / TVS / GDT (limits voltage, absorbs or redirects energy)
Series impedance: R / NTC / trace inductance (limits current in the main loop)
Shunt path: Y-cap / chassis path (reduces EMI but can change stress distribution)
Step 3 — Estimate stress distribution (peak vs energy vs upset)
- Peak current path: identifies which components see di/dt and overshoot.
- Energy in the tail: predicts clamp heating and repeated-shot degradation.
- Coupled branches: explain resets/link drops even when hardware survives.
Component roles & limits (avoid false assumptions)
Voltage clamp: fast protection may not be energy-capable; energy-capable protection may age and shift.
Current limiting: effectiveness depends on the actual loop; not every “inductor” reduces surge energy in the main path.
Shunt to chassis: can help EMI, but may increase stress on the barrier or move the upset point to the secondary domain.
Most common failure loop:
the clamp references the wrong point, so the clamp becomes a stress injector and pulls surge energy into sensitive nodes near the isolation barrier.
Diagram — Surge current loop (main loop vs coupled branches)
Always define the return/PE reference and clamp reference point; an incorrect reference can redirect surge energy into the isolation barrier neighborhood.
Protection Stack for Isolation Products (Layered Stress Sharing)
Isolation products survive surge best when stress is absorbed in layers. The design goal is to keep energy at the entrance using energy-capable parts, limit what reaches the barrier neighborhood, and ensure the isolation IC is not forced to act as an energy device.
“Who takes the hit” design rules
- Keep energy at the entrance: place energy-capable parts closest to the port and close the loop to the intended return point.
- Layer the protection: upstream handles energy/peak current; near-barrier stages limit stress on sensitive nodes.
- Do not load the isolation IC: the barrier device should not be the primary energy absorber.
L1 — Port / Line side (energy & peak current)
Typical parts: MOV, GDT, TVS (in combinations)
Focus: energy capability, speed, follow current, lifetime under repetition
If wrong: stress is transported downstream; barrier neighborhood becomes the upset point
L2 — Primary domain (power-stage protection)
Typical parts: RCD/snubber, primary clamp, controller OVP/UVLO
Focus: overshoot control and recovery behavior (avoid brownout oscillation)
If wrong: resets, latch events, or repeated restart storms without permanent damage
L3 — Barrier neighborhood (limit what reaches the isolator pins)
Typical parts: secondary TVS, RC snubber, clamp diodes, input current limiting
Focus: protect sensitive I/O structures and prevent stress injection across the barrier
If wrong: polarity-dependent link drops, unexplained CRC bursts, or isolator pin overstress
L4 — Secondary domain (stabilize rails & interfaces)
Typical parts: rail clamps, secondary TVS, interface-side protection
Focus: convert severe behavior (C) into self-recoverable behavior (B)
If wrong: secondary undervoltage triggers link flaps and latched faults
L5 — Load / I/O boundary (prevent back-injection)
Typical parts: local clamps, series resistors, controlled startup / fault-latch policy
Focus: stop abnormal load states from keeping the system in a non-recoverable condition
If wrong: persistent fault states after a shot even though hardware is intact
Common anti-patterns (stress transport)
- Energy device missing at L1: a TVS alone is forced to absorb energy and degrades quickly under repetition.
- Wrong clamp reference: the clamp redirects current into the barrier neighborhood and creates functional upsets.
Diagram — Protection stack layers (L1 → L5)
Layering keeps energy at L1 while near-barrier stages limit injection into sensitive isolation I/O structures.
Layout & Partition for Surge (Make Stress Follow the Intended Loop)
Surge current always closes a loop. In primary/secondary partitioned layouts, the most common failures come from unintended return paths that cross the gap or inject current into sensitive domains. Layout should minimize loop area, anchor the reference point (PE/chassis), and keep high dv/dt nodes away from the barrier edge.
✅ Do (surge-loop view)
- Keep clamp loop short: port → clamp → return should be compact and closed.
- Define PE/chassis reference: anchor the return point so stress does not drift into signal ground.
- Separate high dv/dt nodes: keep switching nodes away from the barrier edge to reduce Cbar injection.
- Place Y-cap intentionally: connect to the intended reference so common-mode current avoids sensitive domains.
⛔ Don’t (common pitfalls)
- Do not “place clamp but forget return”: a long return loop transports stress across partitions.
- Do not let return cross the gap: unintended paths can inject current into barrier-near I/O nodes.
- Do not put Y-cap at the wrong spot: it can become a stress injector into secondary logic.
- Do not route sensitive traces near the clamp loop: magnetic coupling can create error bursts.
Diagram — Good vs Bad placement (loop closure & reference)
Good placement keeps the clamp at the entrance and closes the loop to the intended return; bad placement enlarges loop area and risks cross-gap injection near the barrier.
Test Setup: CDN, Wiring, and Measurement Points (Reproducibility)
Lab-to-lab differences are often caused by wiring, grounding, cable routing, fixture parasitics, and inconsistent reference points. A reproducible surge result requires fixing the coupling/decoupling network, the return reference, the DUT operating state, and probe reference points in the test record.
Why the same board can differ across labs
- Loop geometry changes: lead length and routing change loop impedance and peak stress.
- Reference drift: unclear PE/return point pushes stress into signal ground.
- Cable & shield bonding: different bonding points change common-mode paths.
- Fixture parasitics: clamps and adapters add inductance/capacitance and distort the shot.
Must-fix setup elements (write into the record)
CDN / coupling network: type, configuration (L-L / L-G), termination, and any series elements.
Cables: length, routing, and shield bond method (single-end / both-end, location).
Reference point: PE/return definition and the physical connection point.
DUT operating state: load, power mode, communication mode/rate, thermal state.
Measurement points: V/I probe location and probe reference consistency (same return).
Reproduction fields (minimum template)
- Nameplate: waveform, kV level, source impedance (Ω), coupling, polarity, repetition, shot index, pass class.
- Setup: cable length, shield bonding, fixture version, PE point, probe locations.
- State: load, power mode, comms rate/mode, and any pre-conditioning.
Checklist — Pre-test
- Confirm CDN type/config and termination match the intended class.
- Fix cable length/routing and shield bond point(s); document the path.
- Define PE/return point and verify clamp reference closes to it.
- Set DUT operating state (load/power/comms) and keep it constant.
- Align probe reference points (V and I probes share the defined return).
Checklist — During-test
- Log shot index, polarity, and repetition interval exactly.
- Capture Vmeas and Imeas at the defined points with consistent reference.
- Record black-box events (reset reason, UVLO/OT/SC flags, link drops, CRC bursts).
- Pause if fixture/cable moves; treat it as a configuration change.
Checklist — Post-test
- Run functional regression and classify behavior (A/B/C/D).
- Check for post-shot drift (leakage, clamp level, rail stability).
- Verify recovery policy outcomes (auto vs manual) match the criterion.
- Archive the full record: nameplate + setup fields + logs + waveforms.
Diagram — Lab setup block diagram (generator → CDN → DUT → host/load)
Reproducibility requires a single defined PE/return reference and fixed probe locations with consistent probe reference points.
Design Checklist (Design → Bring-up → Production Gates)
A practical checklist turns surge knowledge into an auditable engineering flow. The gates below ensure stress-sharing is correct in design, the lab process is reproducible in bring-up, and aging/sampling/traceability are controlled in production.
Gate 1 — Design (loop + stress-sharing locked)
Goal: define the main surge loop, identify coupled branches, and ensure energy stays at the entrance.
- Draw the surge loop (generator/CDN → port → clamp → return) and mark the reference point.
- Define the protection stack (L1–L5) and which layer absorbs energy vs limits stress.
- Size protection parts by peak current, energy in tail, repetition count, and temperature rise (X/Y/N).
- Verify clamp reference does not inject stress into barrier neighborhood.
- Define pass criteria class (A/B/C/D) and attach it to the test nameplate fields.
- Plan black-box signals to log (reset reason, UVLO/OT/SC, link drop, CRC burst).
- Review placement rules: clamp-to-port loop area minimized; PE/return anchor explicit.
- Define post-shot drift checks (leakage, clamp level, rail stability) with thresholds.
Deliverables: loop diagram, protection stack diagram, nameplate template, pass criteria definition, drift check list.
Gate 2 — Bring-up (reproducible setup + graded severity)
Goal: validate setup reproducibility first, then tighten severity step-by-step with consistent logs.
- Start with a low level to validate wiring, reference, and probe points (baseline shot).
- Increase severity gradually; keep the same setup fields for every level.
- Record shot index, polarity, repetition interval, and the full nameplate set.
- Log black-box events and reset reasons per shot; map each to A/B/C/D.
- Track communication errors by time window (burst vs steady) and link-drop patterns.
- Capture V/I waveforms at fixed measurement points; do not change probe reference.
- If the fixture or cable moves, treat it as a configuration change and re-baseline.
- After each level, run regression tests and drift checks; stop if drift exceeds limits.
Deliverables: shot log with full fields, A/B/C/D distribution, waveform captures at fixed points, drift check report.
Gate 3 — Production (aging + sampling + traceability)
Goal: control aging-sensitive parts and ensure consistent behavior with traceable records.
- Define incoming inspection focus: MOV degradation trend, TVS leakage drift, GDT trigger shift (X/Y/N).
- Lock the sampling plan: which level(s) to sample, how often, and pass criteria class target.
- Use the same nameplate and setup field template for production sampling tests.
- Track drift indicators over time (leakage, clamp level, rail stability) and set control limits.
- Record traceability fields: part lots, board revision, fixture version, test configuration ID.
- Define failure classification mapping: functional upset vs permanent damage with evidence.
- Archive reports in a consistent format for audit and lab-to-lab comparison.
- If a supplier change occurs, re-run a baseline level and compare A/B/C/D distributions.
Deliverables: sampling report template, traceability field list, drift control chart inputs, failure taxonomy.
Diagram — Gate flow (Design → Bring-up → Production)
Gate flow keeps requirements auditable: consistent templates enable fair lab-to-lab and lot-to-lot comparisons.
Quick Pairings (Combinations Only)
Rule: each pairing provides only a module stack + one surge hook + a link. No deep details here.
Motor / Inverter
Stack: Isolated Gate Driver + Isolated ΔΣ Modulator + Isolated Bias
Surge hook: lock the surge loop and PE/chassis reference so energy stays at the entrance.
Example parts:
Driver: TI UCC21520 / ADI ADuM4135 / Infineon 1EDC60I12AH
Modulator: TI AMC1306 / TI AMC1304 / ADI AD7403
Bias: TI SN6505 (transformer driver) + small transformer / Murata MGJ2 series module
Modulator: TI AMC1306 / TI AMC1304 / ADI AD7403
Bias: TI SN6505 (transformer driver) + small transformer / Murata MGJ2 series module
BMS / HV Systems
Stack: Isolated CAN(-FD) or isoSPI + Reinforced Isolation + Surge Strategy
Surge hook: prioritize line-to-chassis coupling paths and keep clamp return tied to the correct reference.
Example parts:
Isolated CAN: TI ISO1042 / ADI ADM3055E / TI ISO1050
isoSPI link: ADI LTC6820 (isoSPI interface over twisted pair) :contentReference[oaicite:0]{index=0}
Reinforced digital isolator: Silicon Labs Si86xx family / ADI ADuM141E
isoSPI link: ADI LTC6820 (isoSPI interface over twisted pair) :contentReference[oaicite:0]{index=0}
Reinforced digital isolator: Silicon Labs Si86xx family / ADI ADuM141E
Industrial I/O (Long Cable)
Stack: Isolated RS-485 + Isolated Power
Surge hook: long cable coupling dominates; fixture + cable + shield bond must be frozen for reproducibility.
Example parts:
Isolated RS-485: ADI ADM2587E (iso + integrated power) / TI ISO1410
Isolated power module: Murata NME0505SC / RECOM R05P05S / TRACO TEN 5 series
Isolated power module: Murata NME0505SC / RECOM R05P05S / TRACO TEN 5 series
Medical (USB Service / HMI)
Stack: Isolated USB + Leakage-Aware Isolated Power
Surge hook: avoid “fixing surge” by adding return paths that break leakage limits (details belong to the medical page).
Example parts:
USB isolation (FS/LS): ADI ADuM3160 / ADI ADuM4160 :contentReference[oaicite:1]{index=1}
USB isolation (HS 480 Mbps): TI ISOUSB211 :contentReference[oaicite:2]{index=2}
Isolated power: Murata NXE1 series / RECOM RxxP series (select to match leakage constraints)
USB isolation (HS 480 Mbps): TI ISOUSB211 :contentReference[oaicite:2]{index=2}
Isolated power: Murata NXE1 series / RECOM RxxP series (select to match leakage constraints)
Diagram — Pairing map (module stacks only)
Applications & IC Selection (Surge-Focused, Before FAQ)
Selection must start from the surge nameplate (kV + Ω + coupling + polarity + repetition), then enforce stress-sharing layers, and finally validate pass class and aging under repeated shots.
Selection logic (5 steps)
Each step lists Input → Decision → Output, with example part numbers to anchor the decision.
Step 1 — Lock the surge nameplate
Input: waveform + level (kV) + source impedance (Ω) + coupling (L-L / L-G) + polarity + repetition.
Decision: identify which path dominates (line-to-line vs line-to-chassis) and which return reference is valid.
Output: a single “configuration ID” used across design/bring-up/production records.
Step 2 — Choose protection layers (energy stays at the entrance)
Input: nameplate + intended pass class (A/B/C/D) + repetition/aging expectations.
Decision: pick a minimal stack: Entrance L1 (energy) + L2/L3 (secondary clamp) + closed return + measurement points.
Example protection parts (choose per nameplate):
MOV: Littelfuse V14E series / Bourns MOV-14D series
GDT: Bourns 2038-xx series / Littelfuse CG series
TVS: Littelfuse SMBJ series / Vishay SMBJ series / Semtech SMBJ series
MOV: Littelfuse V14E series / Bourns MOV-14D series
GDT: Bourns 2038-xx series / Littelfuse CG series
TVS: Littelfuse SMBJ series / Vishay SMBJ series / Semtech SMBJ series
Output: a layer map (L1–L5) + placement constraints tied to the surge loop.
Step 3 — Select isolators by impulse behavior (not just data rate)
Input: coupling path + barrier capacitance sensitivity + required safe states.
Decision: choose devices that document barrier behavior and fail modes that fit the pass class.
Example isolator parts (category anchors):
General digital isolator: ADI ADuM141E / Silicon Labs Si86xx family
Isolated CAN(-FD): TI ISO1042 / ADI ADM3055E
Isolated RS-485: ADI ADM2587E / TI ISO1410
Isolated USB: ADI ADuM3160, ADuM4160 :contentReference[oaicite:3]{index=3}; HS option: TI ISOUSB211 :contentReference[oaicite:4]{index=4}
General digital isolator: ADI ADuM141E / Silicon Labs Si86xx family
Isolated CAN(-FD): TI ISO1042 / ADI ADM3055E
Isolated RS-485: ADI ADM2587E / TI ISO1410
Isolated USB: ADI ADuM3160, ADuM4160 :contentReference[oaicite:3]{index=3}; HS option: TI ISOUSB211 :contentReference[oaicite:4]{index=4}
Output: isolator shortlist tied to coupling and pass class (A/B/C/D).
Step 4 — Select isolated power by surge survival path
Input: expected surge path into primary switch/rectifier, OVP/UVLO behavior, and post-shot recovery requirement.
Decision: select either a module or discrete bias path that keeps energy off sensitive secondary rails.
Example isolated power anchors:
Transformer driver (bias): TI SN6505
Low-power module: Murata NME0505SC / RECOM R05P05S
Higher power module: Murata MGJ2 series / TRACO TEN 5 series
Transformer driver (bias): TI SN6505
Low-power module: Murata NME0505SC / RECOM R05P05S
Higher power module: Murata MGJ2 series / TRACO TEN 5 series
Output: isolated power choice + required clamps/snubber locations in the surge loop.
Step 5 — Validate pass class + repetition aging with logs
Input: pass class target (A/B/C/D), repetition count, and drift checks (leakage/clamp level/rail stability).
Decision: lock the test record template (nameplate + setup fields + black-box logs) and keep it unchanged across labs.
Output: auditable reports enabling lab-to-lab and lot-to-lot comparison.
Do not (surge selection anti-patterns)
- Do not report only kV without Ω/coupling/network — energy is not comparable.
- Do not stack TVS parts without fixing the return/PE reference — stress migrates.
- Do not assume “no smoke” equals pass — enforce A/B/C/D classification.
- Do not ignore repeated-shot aging (MOV/TVS/GDT drift) — lifetime is a requirement.
- Do not change fixture/cable/probe reference mid-test — reproducibility collapses.
Diagram — Selection flow (nameplate → layers → devices → validation)
The flow forces comparable reporting: nameplate first, then layers, then devices, then validation under repeated shots.
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FAQs (Field Troubleshooting & Acceptance, Surge/Impulse Only)
Scope rule: answers below only normalize surge/impulse test definition, setup, surge loop, device stress sharing, and acceptance classes.
Data template: Level = X kV @ Y Ω, Coupling = L-L/L-G, Polarity = +/−, Repetition = N shots, Interval = T s, Result = Class A/B/C (D = fail).
Same kV rating, but one lab fails and another passes—what’s the first thing to normalize?
Likely cause: nameplate mismatch (Ω/coupling/polarity/repetition) or setup mismatch (cable/PE reference/probe reference) despite the same kV number.
Quick check: compare kV + Ω + coupling (L-L/L-G) + polarity + N shots + interval, then confirm cable length/routing, shield bonding, and a single defined PE/return point with identical probe reference points.
Fix: lock a configuration ID and freeze wiring/fixture/probe points; re-run a low-level baseline, then step up with no setup changes.
Pass criteria: results match across labs within ±X% for peak V/I at the defined points, and classification is stable at Class A/B/C for N shots at X kV @ Y Ω, coupling L-L/L-G, polarity +/−, interval T s.
Surge test passes at low repetition, fails at higher repetition—what usually drifted?
Likely cause: cumulative heating/aging shifts clamp behavior (MOV/TVS/GDT) or increases leakage; secondary stress migrates as the entrance clamp drifts.
Quick check: log clamp indicators before/after: Vclamp, Ileak, rail droop events, and shot-to-shot trend; confirm repetition interval is truly T s and not shorter in the failing run.
Fix: increase entrance energy handling (bigger L1 or better heat path), extend interval, or add a secondary clamp to keep stress off sensitive nodes.
Pass criteria: at X kV @ Y Ω, N shots with interval T s, clamp drift stays within ΔVclamp ≤ X% and leakage stays ≤ Y (unit), with result Class A/B/C.
No damage, but device resets during surge—power rail collapse or logic upset?
Likely cause: rail droop triggers UVLO/POR (supply collapse), or common-mode injection hits sensitive reset/logic nodes (logic upset) without sustained rail drop.
Quick check: capture rail min voltage, UVLO/POR/reset reason, and compare timing to the surge shot; check if resets correlate to L-G coupling and PE reference changes.
Fix: if rail collapse: improve hold-up/OVP/UVLO strategy or protect the supply entry; if logic upset: reduce injection (lower coupling, tighten return path, add secondary clamp at vulnerable I/O).
Pass criteria: resets ≤ N across N shots at X kV @ Y Ω, with rail droop margin Vmin ≥ X (V) and classification meets Class A/B/C requirement.
MOV looks fine visually, but clamp voltage creeps up over time—what to check first?
Likely cause: MOV aging from repeated energy absorption raises clamping level; thermal stress accelerates drift even without visible damage.
Quick check: compare Vclamp trend and Ileak before/after test; verify repetition and interval; check whether the MOV is absorbing most tail energy (10/1000 µs cases).
Fix: raise energy margin (larger MOV or move energy to an upstream stage), improve thermal path, or distribute stress using L1+L2 design.
Pass criteria: after N shots at X kV @ Y Ω (coupling L-L/L-G), clamp shift stays ΔVclamp ≤ X% and leakage stays ≤ Y (unit), with no move to Class D.
TVS survives once but fails later—energy rating mismatch or thermal stacking?
Likely cause: the TVS is taking tail energy it was not sized for, or repeated shots cause junction heating that stacks faster than cooling.
Quick check: confirm source impedance (Ω) and coupling match the TVS’s intended surge class; compare shot spacing to thermal recovery; inspect post-shot leakage increase.
Fix: move bulk energy to an entrance device (MOV/GDT) and reserve TVS for fast secondary clamping; enforce spacing or heat sinking if repetition is required.
Pass criteria: TVS leakage remains ≤ Y (unit) and no short/open occurs after N shots at X kV @ Y Ω with interval T s; result remains Class A/B/C.
Line-to-ground surge fails, line-to-line passes—where is the missing return path?
Likely cause: the L-G surge current returns through an unintended path (signal ground or across the isolation boundary) because PE/chassis reference is not anchored.
Quick check: locate the L-G clamp reference point and trace the physical return; verify the clamp is tied to the defined PE/return point with a short closed loop.
Fix: re-anchor PE/chassis return, tighten entrance clamp loop, and add secondary clamping where stress transfer is observed.
Pass criteria: under L-G coupling at X kV @ Y Ω, measured stress at sensitive nodes stays below X (unit) and no escalation beyond Class B/C across N shots.
Adding a Y-cap fixed EMI but surge failures got worse—why?
Likely cause: the Y-cap creates a new high-frequency return path that pulls surge common-mode current into the “wrong” domain, increasing stress at sensitive nodes.
Quick check: compare waveforms with/without the Y-cap: node peak voltage, reset/log events, and which coupling mode fails; confirm Y-cap location relative to the entrance clamp and PE reference.
Fix: move the Y-cap reference to the correct chassis/PE point, reduce its value, or add a controlled secondary clamp so injected current does not hit sensitive rails/logic.
Pass criteria: after Y-cap change, surge result meets Class A/B/C at X kV @ Y Ω for N shots with no increase beyond X resets or Y CRC bursts per minute.
Isolation IC survives, but secondary regulator dies—what’s the typical stress transfer path?
Likely cause: the entrance clamp references the wrong return, shifting energy onto the secondary rail; or secondary lacks a clamp so transient overshoot hits the regulator first.
Quick check: capture secondary rail peak/overshoot during surge; check whether the secondary clamp exists and where its return ties; correlate failure with coupling mode (often L-G).
Fix: keep bulk energy at the entrance (L1), then add a targeted secondary clamp at the regulator input with a short local loop and correct return reference.
Pass criteria: secondary rail overshoot stays ≤ X (V) for N shots at X kV @ Y Ω, and no component damage occurs with result Class A/B/C.
Passes with short leads, fails with longer harness—first loop area or reference point?
Likely cause: increased loop inductance and coupling from the longer harness reshapes peak stress; reference point ambiguity grows with cable length.
Quick check: compare peak V/I at the same measurement points; confirm cable routing/shield bond is identical; verify PE/return anchor is unchanged between short/long configurations.
Fix: minimize entrance clamp loop area, relocate clamp closer to the port, and enforce a single return reference; if needed, add a secondary clamp where coupling injects stress.
Pass criteria: with harness length X (m), at X kV @ Y Ω and N shots, peak node stress stays within ±X% of the short-lead baseline and result remains Class A/B/C.
Polarity +/– results differ a lot—what asymmetry is most common?
Likely cause: asymmetric clamp path (diode direction, TVS orientation, MOV/GDT referencing) or asymmetric return geometry that changes current distribution for + vs −.
Quick check: overlay +/− waveforms at the same probe points; verify clamp orientation and whether the return path length differs by polarity (often visible in peak I and delay).
Fix: make clamp and return geometry symmetric where possible; ensure both polarities reference the same PE/return anchor with minimized loop area.
Pass criteria: polarity difference in peak stress stays ≤ X% and both + and − meet Class A/B/C for N shots at X kV @ Y Ω (coupling L-L/L-G).
Only fails when system is in a specific operating mode—what changed in the surge loop?
Likely cause: operating mode changes load paths (switch states, regulators, interface states), which reshapes the surge current loop and shifts which node sees peak stress.
Quick check: run the same surge level in two modes and compare: rail droop, black-box events, and peak node voltages; confirm the mode also changes any relay/FET path connected to chassis or return.
Fix: add mode-robust clamping at the true stress node, or prevent mode-dependent return path changes (keep reference anchored and entrance loop closed).
Pass criteria: for each required mode, at X kV @ Y Ω and N shots, classification meets Class A/B/C with resets ≤ N and error bursts ≤ Y per window.
After surge, leakage current increases—first suspect MOV aging or contamination?
Likely cause: MOV/TVS parameter drift increases leakage, or contamination/moisture creates new leakage paths that become visible after stress.
Quick check: measure leakage at a controlled condition and compare to pre-test baseline; isolate by temporarily removing or bypassing the entrance clamp path (if feasible) to see whether leakage tracks the protection parts.
Fix: if clamp aging: increase energy margin or redistribute stress; if contamination: improve cleaning/coating process and re-check drift under the same nameplate and repetition.
Pass criteria: post-test leakage stays ≤ X (unit) and drift vs baseline stays ≤ Y% after N shots at X kV @ Y Ω; result remains Class A/B/C.
