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eFuse & Hot-Swap Controller ICs — Inrush, SOA, and Fault Control

Answer at a Glance — Should you use eFuse / Hot-Swap?

Choose this page if your design faces high-energy faults, backplane or battery hot-plug, or automotive/industrial transients (cold-crank, load dump). If you only need ramp control, light protection, or ideal-diode OR behavior, go to the PMIC hub → Load Switch / Ideal-Diode OR.

Intro & When to Use

This page focuses on eFuse / Hot-Swap / Surge Stopper solutions for high-energy faults, board-level hot-plug, and automotive/industrial transients. It does not cover low-energy ramp/OR control (see the Load Switch / Ideal-Diode page).

Positioning map comparing Load Switch, Ideal Diode/Power MUX, eFuse, Hot-Swap, and Surge Stopper across monitoring complexity (x-axis) versus energy/current capability (y-axis).
Positioning map: capability vs. energy/current level — where each device class fits.

Use this page if you need:

  • Backplane / battery hot-plug
  • High-energy short-circuit isolation
  • Input OV/UV and reverse protection
  • Timer / latch / retry fault strategies
  • Digital telemetry (PMBus / alarms)

Only need startup dV/dt, small-current protection, or millivolt ORing? Visit the Load Switch / Ideal-Diode OR page.

Topologies

From integrated eFuses to controller + external-FET hot-swap stages. If ORing/priority or digital telemetry is required, see the corresponding variants below.

High-Side eFuse (Integrated Switch)

What it is: Integrated high-side switch with current limit, OV/UV, thermal shutdown, and optional reverse protection (some need external ideal-diode/bridge).

  • Core features: CL/foldback/timer limit, soft-start, fault flags.
  • Best for: Space-constrained boards with moderate energy.
  • Watch-outs: SOA and current are package-limited.
  • Tip: Start here when size & BOM dominate the decision.

Hot-Swap (1 or 2 External FETs)

What it is: Controller drives external MOSFET(s) to shape inrush and handle high-energy faults; two back-to-back FETs provide true bidirectional blocking.

  • Core features: CL/foldback/timer limit, dV/dt control, PG/alarms, retry/latch.
  • Best for: Backplane hot-plug, large Cload, high current.
  • Watch-outs: Validate FET SOA vs pulse width & temperature.
  • Tip: Start here when Max energy × current drives topology.

Ideal-Diode + Hot-Swap Combo

What it is: Front-end ideal-diode/ORing minimizes drop and blocks backfeed; downstream hot-swap shapes inrush and limits fault energy.

  • Core features: Priority/ORing + robust hot-plug & fault handling.
  • Best for: Dual-source main/backup switchover systems.
  • Watch-outs: Avoid loop interaction—add hysteresis and timers.
  • Tip: Use when ORing/priority and hot-plug must coexist.

Digital Telemetry (PMBus / SMBus / Alarms)

What it is: eFuse/hot-swap with digital readouts (V/I/T) and configurable limits via registers; GPIO alarms for fast hardware response.

  • Core features: Telemetry, fault logs, remote limit tuning.
  • Best for: Platform designs needing visibility and diagnostics.
  • Watch-outs: Bus latency vs fault time—keep fast hardware paths.
  • Tip: Choose when you need analytics & configurability.
Selection hint: If Max energy × current × environment transients dominate, begin with Hot-Swap. If size & cost dominate, try Integrated eFuse. Need ORing/priority? Choose Ideal-Diode + Hot-Swap. Need telemetry/control? Pick PMBus/SMBus variants.

Key Specs & Quick Math

Focus on current limiting, controlled ramp, SOA, sense accuracy, thermal capacity, and transient suppression. Use the quick math below to size parts and screen devices.

ILIMIT modes

  • Constant-Current, Foldback, Timer-Limit.
  • Trade-offs across startup success, self-heating, and input droop.

dV/dt (Soft-Start)

  • Set ramp by external CT / RSLEW or device pins.
  • Maps directly to Iinrush with load capacitance.

SOA (Safe Operating Area)

  • External FET is constrained by VDS, pulse width, repetition, and temperature.
  • Defines the energy ceiling for hot-plug and fault events.

Rsense sizing

  • Compute from controller threshold Vlimit: R ≈ Vlimit/Ilimit.
  • Check tolerance, power rating, and Kelvin routing.

Inrush & ramp time

  • Given target Iinrush, back-calc dV/dt and tramp.

Dissipation & thermal

  • Steady vs. limit-mode Pdiss and junction rise.
  • Package θJA, copper area, and parallel FET evaluation.

TVS / RC snub

  • Clamp voltage ≥ worst-case working voltage (with tolerance) and < device abs. max.
  • Match surge energy to TVS rating; RC corner fc=1/(2πRC) to tame spikes.
Quick math

Iinrush ≈ Cload × dV/dt

tramp ≈ ΔV / (dV/dt)

Rsense ≈ Vlimit / Ilimit

Thermal

PFET,steady ≈ I² × RDS(on)

PFET,limit ≈ VDS × Ilimit (short pulses)

ΔT ≈ P × θJA

TVS & RC

Vclamp ≥ Vmax,work(1+tol) < abs max

Esurge ≤ TVS rated energy (match pulse)

fc = 1/(2πRC)

ILIMIT modes — quick comparison

Mode Startup success Self-heating Input droop Tolerance
Constant-Current High with proper dV/dt Medium–High Medium Simple to set
Foldback Medium (verify load start) Lower (cooler at faults) Low–Medium Careful thresholding
Timer-Limit High if ramp ends before timer Bounded by timeout Medium–High (during window) Timer adds robustness
SOA Reading Example — VDS vs I with Pulse Width & Temperature Derating VDS I (log) 10µs 1ms 10ms Derate at high Tj Check VDS, pulse width, repetition, temperature
SOA reading example with pulse-width and temperature derating.
R_sense Sizing — Value, Power, and Error Budget R_sense ≈ V_limit / I_limit Use controller datasheet threshold (V_limit) Kelvin sense to controller Check power rating & pulse P ≈ I² × R (steady); verify short pulses vs. package Error Budget (example) • Resistor tolerance: ±0.5% • Tempco (TCR): ±0.2% @ ΔT • Sense amp offset: ±0.3% • Layout (Kelvin): ±0.2% Total (rss): ≈ ±0.7% (example) Route sense traces away from hot loops Keep differential pair matched
Rsense value, power, and error budgeting cheat sheet.

Design Workflow

Follow this path: define requirements → choose device class → set inrush & protection points → ORing/backfeed policy → PG/EN/alarms → build an experiment table.

  1. Requirements: VIN range/transients, Ipeak/Irms, load type, hot-plug/backplane, safety, ambient profile.
  2. Device choice: eFuse vs Hot-Swap (number/size of external FETs), need for PMBus/alarms.
  3. Inrush & protection points: ILIMIT mode/value, dV/dt, OV/UV, reverse policy, SOA margining.
  4. ORing / anti-backfeed: combine with ideal-diode / power MUX as needed; add priority, hysteresis, and debounce.
  5. PG / EN / alarms: PG thresholds, alarm mapping, retry vs. latch strategy.
  6. Experiment table: test steps, temperature points, hot-plug matrix, recording template (time markers & scope annotations).

Parameter Decision Sheet

Capture ILIMIT, timers, CT/CSS, OV/UV thresholds, SOA headroom, and TVS part numbers. Keep it versioned with BOM changes.

Test Plan (A/B Matrix)

Change only one variable per run: load, capacitance, cable length, source impedance, or temperature. Log pass/fail thresholds and waveforms.

Protection Matrix

Side-by-side comparison across faults and device classes. Each cell summarizes Detection (V/I/T/direction), Action (limit/open/retry/latch), typical Delay, and Waveform notes. PMBus variants add telemetry and alerts.

Fault Class eFuse Hot-Swap (1 FET) Hot-Swap (2 FET) Surge Stopper PMBus Variant
SCP / SC / OC Detect: I via Rsense/amp.
Action: CL/foldback; timer → latch or retry.
Delay: Gate pull-down <10 µs typical.
Waveform: VOUT dip; VDS step; PG deassert. 		Detect: I via sense pin; dV/dt supervised.
Action: CL or foldback; timer window.
Delay: µs-class gate discharge; ms PG.
Waveform: Limited inrush plateau; FET heating. 		Detect: Same as 1FET.
Action: Both FETs off → true isolation.
Delay: µs; verify no reverse spike.
Waveform: Backfeed blocked by series sources. 		Detect: I/V monitor; clamps power.
Action: Current clamp & V clamp; timer → off.
Delay: Fast analog loop (µs).
Waveform: VIN limited; thermal ramp. 		Adds: Read I/V/T; ALERT on OC/SC.
Action: Same as base; limits configurable.
Note: Bus latency; keep HW fast path.
OV / UV Detect: VIN comparators.
Action: Gate off; optional auto-retry.
Delay: µs-ms per filter.
Waveform: Clean cutoff; PG toggles. 		Detect: VIN/FB comparators.
Action: Turn-off with slew control.
Delay: Filtered ms.
Waveform: Controlled fall, no bounce. 		Detect: Same; isolation maintained.
Action: Dual FET off on OV/UV.
Delay: µs-ms.
Waveform: No backfeed at UV shutdown. 		Detect: OV by clamp loop.
Action: Clamp or disconnect on timeout.
Delay: Sub-µs clamp, ms timeout.
Waveform: V limited; thermal rise. 		Adds: Thresholds via registers.
Report: OV/UV status & logs.
Reverse / Backfeed Detect: Direction/V drop sense.
Action: RCB if available; else off.
Delay: µs-class.
Waveform: Verify no VOUT→VIN rise. 		Detect: Reverse V across FET.
Action: Off; body diode still conducts.
Delay: Fast off; not bidirectional block.
Waveform: Small backfeed via diode. 		Detect: Reverse sense both sides.
Action: Back-to-back FETs block both ways.
Delay: µs.
Waveform: No reverse spike; clean isolation. 		Detect: Ideal-diode front end (if used).
Action: ORing control + cutoff on fault.
Delay: Comparator speed (µs).
Waveform: mV-level forward drop. 		Adds: Directional alarms; log events.
Note: Keep HW path for fast reverse block.
Thermal Detect: Junction sensor.
Action: Thermal shutdown; auto-retry.
Delay: Depends on heating time.
Waveform: Periodic restart if latched retry. 		Detect: Controller or FET temp proxy.
Action: Off or reduce limit window.
Waveform: Gate toggles per cooldown. 		Detect: As left; two FETs share heat.
Action: Fast off both paths.
Waveform: Lower hot-spot if balanced. 		Detect: Internal sensor drives clamp/off.
Action: Power limit with timeout.
Waveform: Thermal-limited plateau. 		Adds: Read Tj; program thresholds.
Report: OT status, history.
Timer / Latch / Retry Detect: Timer after limit event.
Action: Latch-off or auto-retry.
Delay: ms scale; set by C/R.
Waveform: Sawtooth if hiccup. 		Detect: Programmed window.
Action: Off; optional cool-down.
Waveform: PG marks retry cadence. 		Detect: Same; dual-path off.
Action: Clean isolation on each cycle.
Waveform: No backfeed between retries. 		Detect: Energy/time limiter.
Action: Clamp then off; restart policy.
Waveform: Limited envelope then drop. 		Adds: Program timers; read counters.
Report: ALERT on latch/retry.
Notes on Hot-Swap with two FETs (reverse block & fast power-down)

Back-to-back MOSFETs provide true bidirectional blocking. During power-down or reverse events, ensure both gates are rapidly discharged to avoid body-diode conduction and backfeed spikes. Validate with forced VOUT > VIN tests.

Fault Handling Flow Detect Decide Act Recover / Retry Report V/I/T comparators, direction check Policy: limit / open / timer / latch Gate pull-down, clamps, isolation Cool-down, hiccup, or manual GPIO PG/ALERT, PMBus logs
Fault handling flow: Detect → Decide → Act → Recover/Retry → Report.

ORing & Muxing Hooks

Interface rules for ideal-diode ORing and power MUX blocks. Keep decision logic, hysteresis, and dwell times decoupled from hot-swap limit/timer loops to avoid oscillation and chatter when sources are close.

Principles

  • Priority policy: fixed-primary, voltage-wins, or GPIO-forced override.
  • Hysteresis & dwell: add ≥ required mV and ≥ few ms to suppress ping-pong near equal sources.
  • Timing decoupling: separate ORing comparator timing from hot-swap limit/timer windows.
  • Isolation: for backfeed-sensitive paths, use back-to-back FETs downstream of ORing.

Risks

  • Loop interaction: ORing loop fights hot-swap current limit → gate oscillation.
  • Insufficient hysteresis: chatter when source voltages converge or cross.
  • Delayed cut-off: backfeed spikes if gates are not quickly discharged on power-down.

Suggested Tests

  • Main ↔ backup switchover with load steps; verify dwell and hysteresis thresholds.
  • Near-equal and crossing source voltages; find the chatter boundary and add margin.
  • Reverse and power-down backfeed checks (2-FET isolation downstream of ORing).
Decoupling ORing & Hot-Swap Loops ORing Controller (priority + hysteresis + dwell) Hot-Swap (limit + timer + SOA) Ideal-Diode / Power MUX Priority + hysteresis Downstream 2-FET isolation Load Decouple timing: keep ORing dwell/hysteresis independent from hot-swap limit window to avoid loop fights and chatter.
Decouple ORing decision timing from hot-swap limit/timer loops; add hysteresis and dwell.

Need deeper ORing/MUX design (thresholds, comparators, priority logic)? See the sibling page: Ideal-Diode / Power MUX.

Layout & Thermal

Prioritize the hot loop, measurement integrity, and transient return paths. Keep power and sense routing deliberate, thermals generous, and probing convenient.

Hot loop minimization

Shrink the VIN–FET–VOUT loop; route input and return in parallel with tight coupling. Place CIN/COUT close to switch nodes to tame di/dt and ringing.

Kelvin Rsense

Use four-terminal sensing; run matched differential traces to the controller. Keep them away from high-current returns. Land on dedicated sense pads (no shared via barrels).

TVS / RC placement

Place the TVS at the input connector; ensure a short, straight return to chassis/ground. Keep any RC snub loop tiny and close to the switching edge you need to damp.

Star grounds (PGND/AGND)

Feed comparators/controllers from a clean AGND. Star back to PGND at a quiet node; Kelvin Sense/PG pins; avoid dropping measurement currents into power ground.

Thermal path

Use large copper under FETs with via arrays. Parallel FETs need symmetric copper to share current. Align hot parts with airflow; avoid trapping heat under tall components.

Probing points

Provide labeled pads for VIN, VOUT, PG, CS, EN, ALARM and a nearby ground spring. Reserve scope space; mark current direction and measurement polarity.

Layout Schematic — Kelvin Rsense, TVS at input, Star Ground, Thermal Copper Input Connector TVS CIN FET R_sense Kelvin+ Kelvin− Controller (AGND) star PGND plane COUT VOUT → Keep sense away from power returns; short TVS return; star AGND to PGND; use via arrays under hot devices.
Layout schematic: Kelvin Rsense, TVS at connector, star ground split, thermal copper and via arrays.
Thermal Path — Copper, Vias, Airflow, Symmetry Airflow FET A FET B Large copper area Lower θ_JA by spreading heat and providing vertical vias; thicker copper reduces ΔT for the same P_diss. Keep symmetry between parallel devices to balance current and temperature rise.
Thermal path: copper area, via arrays, airflow direction, and symmetry for parallel FETs.

Quick Checklist (Copy-Paste)

  • Minimize VIN–FET–VOUT loop; pair input/return.
  • Kelvin four-terminal Rsense; matched differential traces.
  • TVS at connector; short straight return; tiny RC loop.
  • Star AGND to PGND; clean comparator references.
  • Large copper + via arrays; symmetric for parallel FETs.
  • Test pads for VIN/VOUT/PG/CS/EN/ALARM with GND spring.

Validation & Bring-Up

Use a one-variable-at-a-time approach; log scope markers and ambient. Build an A/B matrix and capture limits, waveforms, and pass/fail criteria.

Startup waveform

Measure dV/dt and Iinrush; check input droop and PG timing. Confirm ramp ends before any timer-limit window expires.

Over-current

Validate CC/foldback/timer actions and recovery policy. Record latch vs. retry cadence and junction heating rate.

Thermal shock

Under steady and pulsed limit, log Pdiss → ΔT and thermal shutdown points. Measure cool-down time to restart.

Hot-plug

Exercise battery/backplane insert/remove with/without load and input transients. Verify gate discharge speed and no backfeed spikes.

ORing behavior

Main↔backup switchover under load steps; sweep near-equal sources to find chatter threshold; test power-down backfeed.

EMI & transients

Capture switching spikes, cable resonance, and TVS clamping. Tune RC snub and routing where necessary.

A/B Conditions Matrix

Run Temp Cable Variable Cload Source Z Notes
A1 25 °C 0.5 m dV/dt 220 µF 50 mΩ Base bring-up
A2 25 °C 0.5 m Ilimit 220 µF 50 mΩ CL vs foldback
B1 -20 °C 1.0 m Load step 220 µF 100 mΩ ORing switchover

Bring-Up Checklist

  • Log VIN, VOUT, I, VDS, GATE; mark time zero and trigger conditions.
  • Record thresholds (OV/UV, Ilimit, timers), ambient, and airflow.
  • Save scope screenshots with scale annotations and cursor readouts.
  • Note pass/fail margins and ΔT at steady and pulsed limits.
  • Attach A/B matrix, serial numbers, and configuration hash.

Cross-Brand IC Options

Series-level index only—no part-number deep dive here. Use this as a quick map to eFuse, Hot-Swap, Surge Stopper, Ideal-Diode/OR, and high-side distribution families. For pin-compatible swaps or a vetted shortlist, head to Resources & RFQ and Submit BOM (48h).

Texas Instruments (TI)

  • TPS259x / TPS266x — eFuse  Industrial 12–60 V rails; OV/UV/ILIM/timer for fast bring-up.
  • LM506x — Hot-Swap Controller  External FET(s); high-energy backplane hot-plug.
  • TPS27xxx — High-Side Switch  Power distribution, multi-channel variants.

Analog Devices (ADI)

  • LTC436x — Surge Stopper  Input clamp/ride-through for automotive/industrial.
  • LTC422x / LTC421x — Hot-Swap  Inrush control, fault timers, SOA-friendly with external FETs.
  • LTC435x — Ideal-Diode / OR Controller  mV drop, backfeed block, priority hooks.

STMicroelectronics (ST)

  • STEFxx — eFuse  5–24 V classes; USB/PC/industrial protection.
  • VIPower (selected) — Hot-Swap / Protection  Higher-current protection options.

onsemi

  • NISxxx — eFuse / Protected Switch  Integrated ILIM & thermal; compact BOM.

Renesas

  • ISL614x / ISL612x — Hot-Swap / Power-Path  Back-to-back FET support, PG/alarms.

Microchip

  • MIC25xx / MIC20xx — High-Side Distribution / Protected Switch  Some parts approach eFuse behavior.
  • MCP16xx — Ideal-Diode / Power-Path  Series-dependent; check datasheet limits.

NXP

  • NX5P-series — USB / 5 V Power-Path  Light/medium loads; limited fault energy.
Notes: Series suitability depends on each product’s datasheet (limits, SOA, thresholds, package). Parameters vary across sub-series. For pin-to-pin or alternates, submit your BOM to get a curated list within 48 hours.
Submit BOM (48h) Resources & RFQ

FAQs

Short, practical answers covering eFuse, Hot-Swap, Surge Stopper, current limiting, SOA, Kelvin sensing, ORing, PMBus telemetry, validation, and replacements. Expand any item for actionable guidance and links to the relevant sections of this page.

What’s the boundary between an eFuse, a Hot-Swap controller, and a Surge Stopper?
eFuses integrate limit, OV/UV, and thermal for moderate energy paths with fast bring-up. Hot-Swap controllers use external FETs to handle larger inrush and fault energy, ideal for backplanes. Surge Stoppers clamp input surges and ride-through automotive/industrial transients. Choose by energy, voltage range, and monitoring needs. See: Intro · Topologies
How do I pick among constant-current, foldback, and timer-limit modes?
Constant-current maximizes startup success but heats more and may droop the source. Foldback cools faults and cables but risks failing heavy-load startup. Timer-limit bounds energy and thermal stress—ensure the ramp finishes before timeout. Tune for source stiffness, load behavior, and allowed recovery policy. See: Key Specs & Quick Math
How do I back-solve dV/dt and ramp time from Cload and a target inrush current?
Use Iinrush ≈ Cload × dV/dt. Pick allowable Iinrush, compute dV/dt, then derive tramp ≈ ΔV/(dV/dt). Map dV/dt to your device’s slew pin or CT/RSLEW per datasheet. Verify upstream droop under cable and source impedance. See: Key Specs & Quick Math
How do I read SOA curves with pulse-width and temperature derating?
Plot your worst-case VDS and I against the MOSFET’s pulsed SOA for the event duration. Apply temperature derating for expected Tj. Repetitive pulses require further margin. If the point is outside SOA, slow the ramp, reduce Ilimit, add copper/parallel FETs, or choose a stronger device. See: Key Specs & Quick Math
How should I select Rsense, and why does Kelvin routing matter?
Compute value from the controller threshold: R ≈ Vlimit/Ilimit. Check power rating for steady and pulsed conditions, tolerance, and TCR. Use four-terminal Kelvin pads and matched differential traces to avoid drop errors from high-current returns. Poor routing skews limits and telemetry. See: Layout & Thermal
How do I prioritize actions for reverse/backfeed, OV/UV, and short events?
Protect direction first: block backfeed with back-to-back FETs or ideal-diode control. Then guard voltage—disconnect or clamp on OV; hold off on UV. Finally, enforce current limits, timers, and latch/retry policy. Sequence to avoid unsafe power-through paths during transitions. See: Protection Matrix
How do I prevent gate oscillation or chatter with ORing plus Hot-Swap?
Decouple loops: add hysteresis and dwell to the ORing decision, and keep its timing independent of the Hot-Swap limit/timer window. Avoid near-equal source dithering by setting clear thresholds. Ensure fast gate discharge to stop backfeed when switching priority. Validate with crossing-voltage tests. See: ORing & Muxing Hooks
What’s the quick math and placement rule for TVS and RC snubbers?
Pick TVS clamp above max working voltage (with tolerance) but below absolute max; match surge energy rating to your pulse. Place at the input connector with a short return. Size RC with fc=1/(2πRC); keep its loop tight near the noisy edge you’re damping. See: Key Specs · Layout
Thermal shutdown with retry or latch—what are the system side effects?
Retry creates periodic brownouts, EMI bursts, and thermal cycling; good for temporary faults but noisy. Latch holds off until user or MCU intervention; safer for persistent faults but reduces availability. Choose policy per safety and uptime goals, and signal status via PG/ALERT. See: Protection Matrix
How should I structure backplane hot-plug A/B tests?
Change one variable at a time: temperature, cable length/inductance, load type, Cload, and source impedance. Log VIN, VOUT, I, VDS, and GATE with markers. Capture inrush, input droop, PG timing, and recovery behavior. Add near-equal-source ORing tests for chatter margins. See: Validation & Bring-Up
What does PMBus/telemetry add during design and debug?
Real-time V/I/T readings speed root-cause analysis, enable limit tuning without rework, and provide fault logs for intermittent issues. Keep fast hardware paths for protection; use the bus for policy and visibility. Map ALERT lines to critical events for immediate host response. See: Topologies
How do I validate backfeed blocking and power-down behavior with 2-FET isolation?
Force VOUT > VIN and monitor reverse current; both FETs must turn off rapidly and avoid body-diode conduction. During power-down, ensure fast gate discharge and no backfeed spikes. Test across temperature and with capacitive loads to expose edge cases. See: Protection Matrix · Validation
How do I choose ORing thresholds and hysteresis for near-equal sources?
Set a clear mV-level delta and add dwell so small ripples don’t trigger swaps. Ensure the Hot-Swap ramp window and ORing decision timing are decoupled. Validate with slowly crossing source voltages and load steps to confirm no chatter or loop fighting. See: ORing & Muxing Hooks
How do I estimate FET temperature rise and decide on copper, vias, or paralleling?
Start with P ≈ I²·RDS(on) (steady) and P ≈ VDS·Ilimit (pulsed). Use package θJA for a first ΔT estimate, then improve with copper area and via arrays. Parallel FETs only after ensuring current sharing and symmetric layout. See: Key Specs · Layout
How do I check replacements for compatibility: slopes, thresholds, timing, thermals?
Beyond pinout, match slew control (dV/dt), Ilimit strategy, OV/UV thresholds, RCB/QOD behavior, timers, and PG/ALERT polarity. Re-measure startup and fault waveforms against the original acceptance data. If in doubt, run A/B builds on the same board revision. See: Validation & Bring-Up
Need worksheets, calculators, and checklists? Jump to Resources & RFQ for downloads and a 48-hour BOM review.

Resources & RFQ

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Sibling topics: eFuse / Hot-Swap (this page) · Power Sequencing · PMBus PSM · Load Switch / Ideal Diode-OR
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