H2-1 · Definition & Boundary: What “Gate Voltage Range (+/−)” Means

1) Scope guard (to avoid page overlap)

2) The “three ranges” rule (must be separated)

“Gate voltage range (+/−)” is not a single number. It is the intersection of three different ranges. Mixing them causes most field disputes and lab-to-lab inconsistencies.

3) What “+ / −” means here (and what it does not)

• +VON: the intended “ON” plateau level that sets conduction margin and switching behavior.
• −VGOFF: the intended “OFF” plateau level (often 0 V or a negative bias) that increases dv/dt-induced false-turn-on margin.
• Not a topology tutorial: the meaning of “high-side” vs “low-side” supply generation is not expanded here; only the voltage-window definition is handled.

4) Executable outputs (what this chapter must produce)

This chapter is complete only when it yields concrete, testable numbers (placeholders shown; final values belong to the project).

5) Acceptance criteria template (pass/fail placeholders)

H2-2 · Reading the Datasheet: Mapping ±VG Specs to Real VGS

1) The failure mode this chapter eliminates

• Wrong assumption: VOH/VOL equals the device’s actual VGS.
• Root cause: Reference point and load condition are ignored (HS channel is floating; driver output headroom is load-dependent).
• Result: Incorrect VON/VGOFF targets, hidden overvoltage, and inconsistent lab outcomes.

2) Spec fields and what they actually mean (engineering translation)

3) Reference is the first decision (especially for high-side)

4) Load is the second decision (no-load numbers do not protect a design)

Driver outputs are not ideal voltage sources. Under peak source/sink current, the “real plateau” can be lower/higher than expected. Therefore the mapping must always be done at a defined condition:

5) Programmable ±VG: what to recognize in a datasheet (interface-level only)

• Pin-set: strap pins or resistor-set levels to select discrete VON/VGOFF options.
• Register-set: bit fields controlling amplitude/steps (bus protocol details are out of scope here).
• External rails: VON/VGOFF track supplied rails; validation must include rail droop and sequencing.

6) Minimal mapping output (what this chapter must hand to measurement/QA)

H2-3 · +VON: Why “Higher” Is Not Always Better

1) What +VON really controls (two separate paths)

2) The “hidden limiter”: real VON is load- and rail-dependent

• Output headroom: VOH/VOL under peak current is not equal to the ideal rail value.
• Rail droop: VDD/VSS transient drop narrows the achievable window, reducing the intended plateau.
• Implication: decisions must be based on VGS,on(steady) and VGS,peak(max), not only a nominal VON value.

3) When higher +VON becomes risky (measurable conditions)

4) Decision rule (voltage-window logic only)

Increase +VON only while it improves the chosen objective without violating window constraints. If conduction improvement stalls but EMI/overshoot increases, +VON is no longer the correct knob—other pages cover alternative levers.

H2-4 · −VGOFF: When It Is Needed, How Much, and the Cost

1) The real problem: dv/dt-induced Miller injection

During hard switching, fast dv/dt drives displacement current through the switch’s Miller capacitance (Cgd). This can raise the effective OFF gate voltage: VGS(off,effective) = VGOFF + ΔV.

2) When 0 V is enough (decision criterion)

• 0 V OFF is sufficient when the measured VGS(off,peak) under worst-case dv/dt remains below the false-turn-on threshold by a defined margin.
• If margin collapses (VGS(off,peak) approaches threshold), negative VGOFF becomes a valid mitigation knob.

3) How much negative bias (range-only; device-specific values belong elsewhere)

4) Side effects that must be checked (measurable)

• Negative limit: VGS,peak(min) must remain above VGS(abs min) + margin.
• Waveform “hardness”: stronger pull-down can increase ringing; EMI proxy metrics can degrade.
• Sequencing risk: negative rail present while positive rail collapses can create unexpected output states (handled later in rails/UVLO coupling).

H2-5 · Supply Rails & Headroom: How a Driver “Gets” ±VG (No Topology Details)

1) Three rail classes, three hard windows

2) Headroom matters: VOH/VOL is not the same as the rail

• Under peak source/sink current, the output stage drops voltage, so plateaus can shrink even when rails are correct.
• Practical mapping is load-defined: VON,real ≈ VDD − ΔVOH(IOUT,peak) and VGOFF,real ≈ VSS + ΔVOL(IOUT,peak).
• Therefore, any “achievable ±VG” statement must include IOUT,peak, switching corner, and temperature corner.

3) Rail droop directly narrows the effective VG window

Peak gate-drive pulses draw transient charge from the rails. If the rail network droops, the driver cannot sustain the intended plateau levels, and the effective gate-voltage window becomes narrower.

4) High-side reference: the most common measurement trap

H2-6 · VGS Overvoltage Defense: Clamps, Gate Protection, and Allowed Overshoot

1) Overshoot source: gate-loop parasitics drive ringing

• Fast driver edges excite gate-loop inductance and input capacitances, creating ringing and overshoot on VGS.
• Risk is determined by peak VGS, not only the steady plateau level.
• Layout and Kelvin return determine how effective any clamp or suppressor can be.

2) Gate-side defenses (no full protection expansion)

3) Define “allowed overshoot” as an acceptance boundary

Allowed peak is not “below abs max.” It must include margin for measurement error and corner drift: VGS,peak(max) ≤ VGS(abs max) − margin.

4) Verification outputs (what to measure, not how to probe)

H2-7 · Programmable VG: What Can Be Tuned, Resolution, and Side Effects

1) What is programmable (separate amplitude vs edge shape)

2) Three implementation paths (and what each path costs)

3) Resolution is not accuracy: the specification set that must be captured

• Step (ΔV / Δslew): smallest programmable increment.
• Accuracy: difference between target setting and real plateau.
• Repeatability: consistency across power cycles and operating corners.
• Drift: temperature and supply dependence of real VG.
• Matching: channel-to-channel delta (critical for multi-phase or multi-bridge systems).

4) Side effects that must be re-validated

H2-8 · Coupling With UVLO & Fault States: How ±VG Systems Turn Off Safely

1) Why UVLO needs separate ON/OFF thresholds

• Separate thresholds (hysteresis) prevent repeated toggling around the boundary.
• Goal is to avoid half-conduction and undefined gate plateaus during slow ramps or brownouts.
• Engineering outputs are UVLO_ON, UVLO_OFF, and their required hysteresis margin.

2) The special risk of split rails: −V present while +V collapses

3) Safe-state definition must be explicit (state-machine contract)

4) Time-to-safe is a measurable acceptance requirement

Safe shutdown must be bounded in time and validated across hazard windows: t_safe ≤ X ms (placeholder) while keeping VGS within Abs Max/Abs Min constraints.

H2-9 · Measuring the “Real VGS”: Probes, Reference, Bandwidth, and Acceptance Criteria

1) Reference is the definition: gate-to-Kelvin-source only

• VGS must be measured Gate → Kelvin Source (or the true source reference on the switching node).
• Using power ground or a remote source node as the reference measures a mixture of VGS and parasitic drops.
• Any acceptance threshold is only valid when the reference point is correct.

2) Probing rules: minimize loop area before increasing bandwidth

3) Bandwidth and sampling: capture ringing without inventing it

• Measurement bandwidth must be sufficient to capture the dominant ringing frequency and overshoot peak.
• Sampling rate and record length must preserve both peak and decay behavior for comparison across runs.
• If probing is incorrect, higher bandwidth will amplify coupling artifacts rather than improve truth.

4) Required metrics for a complete VG window verification

H2-10 · Engineering Checklist (Design → Bring-up → Production)

Design gate (before design freeze)

Bring-up gate (prototype validation)

Production gate (manufacturing readiness)