What isolated gate drivers really solve

This page explains why isolated gate drivers are essential in high-side, half-bridge and full-bridge power stages, beyond simply “turning the MOSFET on and off”. It connects dv/dt stress, common-mode transient immunity (CMTI), Miller-effect induced false turn-on and isolated bias requirements into one coherent view.

In many offline and high-voltage adapters, PFC and LLC stages, the switching node slews from 0 V to several hundred volts in tens of nanoseconds. The high-side source or emitter is no longer a quiet reference, but a flying node that drags parasitic capacitances and isolation structures with it. An isolated gate driver creates a defined control domain and a defined power domain, with a robust isolation barrier and gate-drive path between them.

When dv/dt is high, any residual common-mode coupling across the barrier injects current into the gate-drive circuit. If the CMTI of the isolation channel is too low, the internal decoder or input comparators may misinterpret common-mode spikes as legitimate transitions. The visual effect on the gate waveform can be subtle, but the result at system level is sporadic mis-switching that is hard to reproduce and even harder to debug.

Even when the logic channel is clean, the power device itself can be pulled into conduction by the Miller effect. During fast transitions, drain-to-gate capacitance couples the drain voltage swing into the gate. If the off-side gate has weak pull-down or no dedicated Miller clamp, the coupled current lifts VGS above threshold for a short time and creates shoot-through in a half-bridge. Isolated gate drivers address this by combining strong, asymmetric source/sink drive with explicit Miller clamp structures that hold the off-side gate safely low during aggressive dv/dt events.

All of this depends on a solid isolated bias. The driver may need +10 V to +15 V for turn-on and 0 V to −5 V for turn-off, and it supervises these rails with UVLO thresholds. If the isolated bias sags, ripples or starts up slowly, UVLO behaviour, soft turn-off and fault handling are affected long before failures are visible at the gate pin. Treating the driver and its isolated bias interface as one design topic is therefore more realistic than treating them as separate widgets.

The rest of this page focuses on the device scope and interfaces of an isolated gate driver: what the IC takes care of, which pins and domains it connects to, and which topics are intentionally left to other pages such as GaN gate drivers, current and voltage sensing, and isolated feedback paths.

Device scope, interfaces and boundary

An isolated gate driver IC sits between the controller domain and the power switches. Its scope is to translate logic-level control signals into robust gate drive across an isolation barrier, supervise local bias rails and provide fault information back to the controller. It is not responsible for choosing the MOSFET or IGBT type, defining the main power topology, or implementing the full digital control algorithm.

On the controller side, the device terminates PWM, enable and fault pins at logic levels that match typical microcontrollers or digital power controllers. Input structures may include hysteresis, deglitching and defined pull-up or pull-down configurations so that the gate driver enters a predictable safe state when the controller is unpowered or tri-stated. Timing relationships between multiple channels, dead-time insertion and advanced modulation remain the responsibility of the digital controller or a dedicated digital PSU controller.

Inside the device, an isolation channel encodes on/off and fault information across a capacitive or magnetic barrier. This channel is designed for high CMTI and for deterministic propagation delay and skew. It is a communication link dedicated to gate-drive control, not a general-purpose data path for ADC samples or telemetry; those roles are better served by isolated feedback amplifiers, ΣΔ modulators and digital isolators covered on other pages.

On the power side, the driver presents a gate output stage referenced to the source or emitter of the switch, often with a separate Kelvin source pin. The output is characterised by asymmetric peak source and sink currents, output voltage swing and the presence of Miller clamp or two-level gate drive. These parameters must be matched to the total gate charge and required switching speed, while the selection of the switch technology and its package is handled in the power-stage and GaN-driver focused pages.

The driver also interfaces to an isolated bias supply. It draws current from isolated rails such as +15 V and −5 V, supervises them with UVLO comparators and applies defined soft turn-off behaviour if the rails fall below threshold. In many devices, desaturation sense pins and over-current detection blocks feed into local fault logic that rapidly turns the gate off and asserts a fault output toward the controller. System-level reactions to these faults, including logging, retry and reconfiguration, remain under the control of higher-level supervision or a digital power controller.

In summary, the isolated gate driver IC defines a clean boundary: it accepts logic-level control, transfers it safely across an isolation barrier and delivers controlled gate energy and local protection at the switch. It does not replace current and voltage sensing chains, isolated feedback paths, reference and bias design or higher-level regulation loops, which are handled in the dedicated sensing, feedback and controller pages within the Power Supplies & Adapters hierarchy.

Isolation technologies and CMTI foundations

An isolated gate driver relies on a physical isolation structure and an internal signalling scheme to move control information from the controller side to the power side. The isolation technology defines the common-mode capacitance across the barrier and therefore how much common-mode current flows when the switching node experiences high dv/dt. Common-mode transient immunity (CMTI) quantifies how much dv/dt the isolation channel can tolerate without corrupting the decoded on/off information.

Magnetic isolation typically uses a miniature transformer structure. Primary and secondary windings are separated by an insulating layer and coupled through a magnetic core or magnetic material. Parasitic inter-winding capacitance creates a common-mode path, but the energy transfer is primarily magnetic, and the structure can be optimised for high CMTI. This approach is well suited to harsh industrial and high-voltage environments where large dv/dt and common-mode noise are present around the half-bridge or full-bridge switches.

Capacitive isolation uses one or more coupling capacitors fabricated inside the IC. Differential signalling across these capacitors transports the encoded PWM information. Integration in CMOS simplifies multi-channel and bidirectional designs, but the isolation path itself is essentially a controlled capacitance. When the switching node slews, this capacitance conducts common-mode current proportional to CCM and dv/dt, and the internal receivers and comparators must be designed to survive and reject these current spikes.

A useful way to reason about the stress on the isolation barrier is the simple relation ICM ≈ CCM × dv/dt. For example, a 5 pF common-mode capacitance exposed to 50 kV/μs launches roughly 0.25 A of transient current across the barrier, and 10 pF at 100 kV/μs launches roughly 1 A. These currents inject charge into front-end circuits inside the isolator and the gate driver; if the design cannot steer and absorb them cleanly, internal comparators and decoders will misinterpret the disturbance as a logic edge.

CMTI specifications such as >100 kV/μs, >150 kV/μs or >200 kV/μs express the maximum dv/dt at which the device maintains correct operation under defined conditions. For offline adapters and moderate-speed silicon MOSFET bridges, CMTI in the 50–100 kV/μs range may be workable with careful layout. For high-voltage PFC and LLC stages with faster edges, >100–150 kV/μs provides more realistic margin. SiC half-bridges and aggressive high-power stages often benefit from CMTI ratings at or above 150–200 kV/μs, especially when switching waveforms are intentionally sharpened to minimise loss.

To achieve these CMTI levels, many isolated gate drivers implement internal encoding schemes. Edge-based encoding converts each rising or falling edge of the PWM into a well-defined pulse or symbol that crosses the barrier, while periodic refresh frames and auxiliary bits help distinguish valid transitions from random spikes. The receiver only reacts to patterns that match the expected timing and coding rules, so short common-mode disturbances injected by dv/dt are less likely to generate false on/off commands, even in the presence of significant ICM.

Output stage, peak currents and Miller clamp

The output stage of an isolated gate driver is the element that actually charges and discharges the gate of the MOSFET, IGBT, SiC or GaN switch. Peak source and sink currents in the range of 3–10 A, and sometimes 15 A or higher, are not marketing embellishments; they reflect the current required to move tens to hundreds of nanocoulombs of gate charge in tens of nanoseconds. For a given gate charge QG, the approximate switching time is QG/IPEAK, so devices with higher peak drive current can support faster edges and higher power levels, within the constraints of EMI and device limits.

Faster transitions are not always better. Aggressive gate drive shortens switching intervals and reduces switching loss, but it also increases dv/dt and di/dt, raising stress on the isolation barrier, worsening EMI and increasing voltage overshoot at the switch. Practical designs therefore pair the driver’s peak capability with external gate resistors to shape the rise and fall times. The goal is a controlled compromise: fast enough to meet efficiency and thermal targets, but not so fast that CMTI margin, device safe operating area or EMI limits are exceeded.

Many isolated gate drivers use purposefully asymmetric source and sink strengths, with a stronger pull-down than pull-up. During turn-on, a moderate source current reduces dV/dt and limits current spikes into the gate loop. During turn-off, a stronger sink path pulls the gate down rapidly and helps keep the device firmly off, especially when the opposite switch in a half-bridge is transitioning. External gate resistors or separate RG(on) and RG(off) networks further fine-tune the turn-on and turn-off slopes around this asymmetry.

Miller clamp structures extend this concept. When a power device is commanded off, the drain or collector of the opposite device may slew rapidly, and the resulting voltage change couples through the drain–gate or collector–gate capacitance. If the off-side gate is only held low through a moderate resistor, the coupled Miller current can lift VGS or VGE into the threshold region and cause false turn-on. A Miller clamp adds a low-impedance discharge path that activates when the gate voltage falls below an internal threshold, often a few volts, and keeps the gate tightly referenced to the source or emitter during high dv/dt events.

The clamp threshold should sit comfortably below the effective conduction threshold of the device. If the clamp engages only near or above VGS(th), process variation and temperature drift can leave narrow regions where the device enters partial conduction before the clamp fully takes over. Evaluating a driver for demanding half-bridge applications therefore includes checking the clamp activation level, its current capability and the availability of a dedicated clamp pin that can be routed close to the gate and Kelvin source reference.

Wide-bandgap devices introduce further sensitivity. GaN switches tend to have lower gate charge but tighter recommended gate-voltage windows and less tolerance for overshoot or ringing. The general principles remain: controlled peak drive, strong and well-timed turn-off paths and robust Miller suppression are still required. Detailed GaN-specific constraints on gate voltage limits, dv/dt shaping and two-level drive are covered in the dedicated GaN driver page in this Power Supplies & Adapters section, keeping this page focused on the core output-stage and Miller-clamp concepts common to silicon, SiC and GaN devices.

Protections: UVLO, DESAT, over-current and soft turn-off

An isolated gate driver implements local protection paths that react faster than any software loop. Undervoltage lockout (UVLO) on the controller side prevents undefined behaviour when the logic supply is not fully valid, while UVLO on the isolated bias rails prevents the gate from being driven with marginal voltage. DESAT and over-current detection monitor the switch itself and trigger controlled soft turn-off when short-circuit conditions occur. A fault output reports these events back to the MCU or digital PSU controller so that system-level protection and logging can take over.

Primary-side UVLO supervises the low-voltage controller supply, typically 3.3 V or 5 V. When this voltage falls below its threshold, the input stage, encoders and logic inside the driver are no longer guaranteed to interpret PWM and enable signals correctly. A well-designed driver forces the output into a defined safe state under primary UVLO, ignoring any residual toggling at the pins and ensuring that the power switch is not left half-driven while the controller is powering down or starting up.

Secondary-side UVLO supervises the isolated bias rails on the power side, such as +15 V and −5 V or a single +10 V rail. Gate drive strength and achievable VGS or VGE depend directly on these rails. When the bias falls into a grey zone, the switch may be pushed into a region where it is neither fully on nor fully off, increasing loss and risking thermal overstress. Secondary UVLO detects this situation and forces the gate into a safe off state, often while asserting a fault signal so that the controller is aware that bias has been lost or degraded.

DESAT and over-current detection focus on the power device itself. In IGBT and SiC applications, a DESAT pin monitors the voltage across the collector–emitter or drain–source path through a small high-voltage diode and resistor network. Under normal conduction, this voltage stays within a low, predictable range; a short circuit or severe overload pushes it well above this range. By filtering the DESAT signal with a blanking capacitor and comparing it to an internal threshold, the driver can detect dangerous current rise within hundreds of nanoseconds and trigger a local protection sequence without waiting for external current-sense amplifiers or digital filtering.

When DESAT or an internal over-current condition is detected, soft turn-off reduces stress on the switch and the bus. Rather than abruptly forcing the gate to the full off voltage with the strongest possible sink current, the driver redirects the gate through a controlled discharge path. This slows the current decay and limits dI/dt, reducing over-voltage spikes caused by bus inductance and wiring parasitics. Some devices implement a two-step sequence, first pulling the gate to an intermediate level to cap current, then completing a slower transition to the normal off level once the worst of the transient has passed.

Fault outputs expose these local events to the controller. A typical device provides an open-drain or push–pull FAULT pin that indicates UVLO, DESAT, thermal or internal error conditions according to a truth table in the datasheet. The controller monitors this pin alongside its own current, voltage and temperature sensors. When a fault is asserted, the controller can halt PWM generation, reconfigure the system, latch the event in nonvolatile memory or initiate a controlled restart sequence. The isolated gate driver defines the boundary between fast analogue protection at the device and slower, system-level responses in firmware.

Isolated bias interfaces and power integrity

An isolated gate driver depends on a clean, well-controlled bias supply on the power side. This isolated bias sets the available gate voltage range, defines the behaviour of UVLO and directly influences gate-drive strength, dv/dt and soft turn-off robustness. In many designs, a small push–pull or resonant transformer generates ±15 V or a single 10–12 V rail, which is then routed into the driver’s VDD, VEE and COM pins. Power integrity of this bias path is as important as the main DC bus if reliable gate control is expected under high dv/dt conditions.

A typical isolated bias uses a high-frequency transformer driven from a low-voltage rail on the primary. The secondary windings are rectified and filtered to provide +15 V and −5 V, or a single positive rail for devices that do not require negative gate drive. The driver datasheet specifies the acceptable voltage range, UVLO thresholds, start-up current and typical transient current drawn during switching. Matching these requirements to the transformer, rectifier and output capacitors ensures that the bias can support peak gate currents without excessive droop or ripple.

In a high dv/dt environment, the bias network itself is exposed to common-mode noise. Parasitic capacitance between the transformer windings and from secondary copper to the switch node injects displacement current into the isolated ground reference. If the bias return and gate-drive reference share long loops or are mixed with high-current paths, this current modulates the local reference potential and appears as noise on the gate voltage. Keeping the bias loop compact, minimising the area of the secondary return and placing output capacitors close to the driver pins are practical steps to preserve power integrity.

Kelvin source connections further improve this situation. When the power device offers a dedicated Kelvin source or emitter pin, the gate driver, isolated bias return, UVLO sensing and Miller clamp should reference this pin rather than the main current-carrying source lead. The Kelvin pin carries only the comparatively small gate-drive currents, so its voltage remains much more stable than the main source, which experiences L·dI/dt and resistive drops from the power loop. Referencing the driver to the Kelvin source ensures that VGS is defined by the local gate–source pair rather than by a noisy system ground.

The isolated bias section does not attempt to replace detailed reference and LDO design. Low-noise regulators, reference accuracy and sequencing of multiple small rails are covered in the References & Bias page within this hierarchy. Here the focus is on the interface: providing the correct voltage levels and current capability to the driver, arranging the bias returns and Kelvin references so that dv/dt and dI/dt do not corrupt the gate-control reference, and treating the isolated bias as a critical part of the high-voltage power stage rather than a generic auxiliary supply.

Timing shaping: gate resistance, dead time and switching trajectory

The switching trajectory of a half-bridge or full-bridge is not defined only by PWM duty cycle. External gate resistors and dead-time settings determine how quickly the gate voltage moves through its operating range and how steep the resulting dv/dt and di/dt become. Appropriate values for Rg(on) and Rg(off) balance switching loss, EMI and CMTI margin, while carefully chosen dead times protect against shoot-through without forcing long periods of body-diode conduction. Advanced gate shaping techniques further refine these trajectories in demanding power stages.

Gate resistance directly influences the rate at which gate charge moves. For a given drive voltage and total gate charge, larger Rg values lengthen the time required to turn the device on or off, reducing dv/dt and di/dt at the expense of higher switching loss. Smaller Rg values shorten the switching interval and improve efficiency, but increase overshoot, ringing, EMI and stress on the isolation barrier. Separate Rg(on) and Rg(off) networks allow asymmetry: a moderate Rg(on) limits turn-on dv/dt, while a smaller Rg(off) supports fast, firm turn-off and improves immunity to Miller-induced false turn-on.

The effective dead time in a half-bridge is the combination of PWM dead-band and the delays introduced by the gate driver, gate resistors and device characteristics. Dead time must be long enough to prevent high-side and low-side devices from conducting simultaneously, yet short enough to avoid extended periods of body-diode conduction and distorted output waveforms. Practical tuning starts from datasheet recommendations, then uses oscilloscope measurements of gate and switch-node waveforms to confirm that one device is fully off, including its Miller region, before the opposite device reaches its conduction plateau.

Two-level or multi-level gate shaping divides the turn-on event into distinct phases rather than a single linear ramp. In the first phase, a higher effective Rg keeps the initial rise of gate voltage gentle, limiting di/dt while the device leaves its off region and approaches the Miller plateau. In the second phase, a lower effective Rg accelerates the remainder of the transition, completing turn-on with acceptable loss. A third phase can optionally reduce drive strength as the gate approaches its final voltage, controlling overshoot and ringing. This staged approach is particularly useful in high-power stages with significant stray inductance or long cable runs.

Multi-level gate shaping can be implemented with discrete networks that switch in different resistances as the gate voltage crosses thresholds, or by using gate drivers that offer programmable current profiles. In all cases, the goal is to keep the switching trajectory inside the safe operating area of the device and the EMI limits of the system, while still delivering the efficiency expected from modern silicon, SiC and GaN power stages. The isolated gate driver provides the interface where Rg(on), Rg(off), dead time and gate current profile come together to define the actual waveform at the gate.

Layout and isolation partitioning

PCB layout determines whether an isolated gate driver reaches its specified CMTI and switching performance. High di/dt loops in the half-bridge and the gate path must be kept compact, Kelvin source connections must be honoured and the isolation barrier must respect creepage and clearance rules while avoiding unnecessary parasitic capacitance. A clear separation between the noisy power region and the sensitive control region is essential for both safety and signal integrity.

The high-side and low-side power loops carry the largest, fastest-changing currents. These loops include the upper and lower switches and the DC-link capacitors that complete the path. Minimising loop area with tight placement and direct copper connections reduces stray inductance and the voltage spikes associated with di/dt. Gate-drive loops should also be compact: the path from the driver output through the gate resistor, into the gate and back through the Kelvin source or source reference must form a small loop that does not share long segments with the main power current path.

Kelvin source layout plays a central role. When the power device provides a separate Kelvin source or emitter pin, this pin should be connected directly to the driver’s local ground reference, to the isolated bias return and to any protection sensing returns. The main source pin continues to carry the large power current. Keeping these two paths physically separate limits the influence of L·di/dt and resistive drops in the power loop on the gate reference, making Vgs more stable and improving immunity to false turn-on and jitter in the switching trajectory.

Isolation partitioning on the PCB enforces the boundary between the control domain and the power domain. The area around the isolation barrier must provide adequate creepage and clearance according to the system’s voltage rating and applicable safety standards. At the same time, large overlapping planes and wide copper spans across the barrier increase common-mode capacitance. Restricting high dv/dt nodes and large copper areas near the barrier on the noisy side, and avoiding control-ground planes directly under switch nodes, helps keep the effective Ccm in line with the driver’s CMTI capability.

CMTI-aware layout brings these ideas together into a practical checklist. High dv/dt nodes are kept away from sensitive traces and planes; critical signals such as DESAT, fault, gate and bias returns are routed with short, direct paths; and the isolation barrier becomes a visible partition between an intentionally noisy power area and a quieter control area. When the PCB design supports the driver in this way, the isolation channel can deliver the dv/dt immunity promised in the datasheet under real switching conditions.

Application mini-stories for isolated gate drivers

1. 1200 V SiC half-bridge inverter leg

A 1200 V SiC half-bridge leg in an 800–1000 V DC bus inverter or ESS converter pushes the isolated gate driver close to its CMTI and protection limits. Typical devices such as Wolfspeed C3M-class 1200 V SiC MOSFETs or similar families are driven at +15…+18 V turn-on and −3…−5 V turn-off to keep RDS(on) low and prevent false turn-on. Gate charge and desired switching loss lead to drivers with 4–8 A peak source/sink capability so that turn-on and turn-off times stay in the tens of nanoseconds range even with modest external Rg.

In this class of design, the target dv/dt across the half-bridge is typically adjusted into the 20–40 kV/μs range. This level keeps switching loss acceptable while avoiding excessive overshoot on long bus structures and cable interfaces. The isolated gate driver therefore needs a guaranteed CMTI of at least 100 kV/μs, leaving margin for layout parasitics and common-mode capacitances that are not present in datasheet test fixtures. Driver families in this segment often specify 100–150 kV/μs CMTI with tests based on pulse generators and representative PCB layouts.

A built-in Miller clamp supports safe turn-off. When the gate is pulled down from +15…+18 V, the driver begins with a strong Rg(off)-limited discharge. As the gate voltage passes through the 2–3 V region, an internal clamp transistor engages and ties the gate firmly to the Kelvin source reference. After this point, any displacement current flowing through CGD during high dv/dt events is diverted into the clamp rather than raising VGS toward the threshold. This behaviour is essential when the drain swings from 0 V to 800–1000 V within tens of nanoseconds.

The isolated bias supply usually consists of a small push–pull transformer stage that generates +15 V and −5 V rails per gate driver channel. High-side and low-side switches each receive their own isolated bias so that their local references can track their individual source potentials. Output capacitors are placed close to the driver pins, and Kelvin source connections are used wherever the SiC package provides them. Secondary-side UVLO thresholds in the driver are chosen so that any significant droop in these rails forces a safe gate-off state before partial conduction can occur.

Protection and monitoring rely on DESAT detection and a fast fault output. A high-voltage diode and resistor connect the switch drain to the driver’s DESAT pin, which monitors the drain–source voltage. Under normal conduction the voltage remains low; during a short-circuit, it rises quickly beyond the DESAT threshold. The driver blanks the DESAT input for a short interval at turn-on, then monitors it continuously. When DESAT trips, the driver engages a controlled soft turn-off path that limits dI/dt and clamps overvoltage, then asserts a FAULT pin toward the controller. The controller in turn latches off the PWM, logs the event and coordinates any retry sequence.

A representative bill of materials for this story includes: a 1200 V SiC MOSFET pair in a Kelvin-source package, a high-CMTI isolated gate driver with DESAT, soft turn-off, Miller clamp and ±15 V support, and a compact isolated DC/DC bias module or controller capable of delivering a few hundred milliwatts per channel. The driver, bias stage, DESAT network and Kelvin layout work together to keep the SiC leg within its safe operating area under both normal dv/dt and fault conditions.

2. Server PSU PFC plus LLC half-bridge

A 2–3 kW server PSU typically combines a boost PFC stage and an LLC half-bridge or full-bridge converter. The PFC MOSFET operates from a rectified 90–264 VAC input and boosts to around 380–420 V, while the LLC stage converts this to a tightly regulated 12 V or 48 V rail. Switching frequencies in these stages often range from 65–130 kHz for PFC and up to 200–250 kHz for LLC. Gate drive levels are usually +10…+12 V turn-on with 0 V turn-off for superjunction MOSFETs, leaving some margin to VGS(max) but ensuring low conduction loss.

For these AC front-ends, dv/dt on the switch node is commonly tuned into the 10–30 kV/μs range. This is high enough to achieve good efficiency in multi-kilowatt designs but still manageable from an EMI standpoint when combined with careful snubbing and layout. Isolated gate drivers serving the PFC and LLC legs therefore need CMTI ratings of at least 50 kV/μs, with 100 kV/μs or more preferred when the board must handle long connector tails, backplane noise and parallel operation with other modules. Drivers with dual isolated channels are often used so that a PFC high-side and low-side pair, or an LLC half-bridge pair, can be handled in a compact package.

A Miller clamp again protects the MOSFET gates from unintended turn-on when the opposite device commutates. In LLC stages with resonant tanks and leakage inductance, the switch-node waveform can include fast transitions and overshoot, especially under light-load or burst modes. As the MOSFET gate is pulled low, the clamp engages at a few volts above the source, providing a low-impedance path that absorbs current injected through CGD. Dead time between complementary gate signals is trimmed so that body-diode conduction is short but reliable soft commutation is maintained.

Isolated bias is usually derived from an auxiliary winding on the main transformer or from a dedicated front-end auxiliary supply. A small multi-output isolated supply might provide several 10–12 V rails to feed the PFC and LLC drivers. Each channel’s UVLO thresholds must be aligned with the bias design so that the driver disables gate outputs cleanly if the rail dips during start-up, burst-mode transitions or hold-up events. Gate drivers with separate VDD pins per channel allow independent decoupling and improved control over cross-regulation effects between legs.

Protection and monitoring combine local driver functions with a digital PSU controller over an interface such as PMBus. Over-current and short-circuit detection may use a combination of shunt sensing and driver-supported fast fault inputs. The drivers expose fault outputs that feed back to the controller, which then adjusts duty cycle, enters hiccup or latches the unit off depending on the system policy. A typical bill of materials includes a 650 V superjunction MOSFET pair for the PFC, a 600–650 V MOSFET pair for the LLC leg, a dual-channel reinforced isolated gate driver with CMTI above 50–100 kV/μs and an auxiliary bias controller or module sized to support multiple gate channels with sufficient transient current.

Design checklist and IC role mapping

Design checklist for isolated gate drivers

This checklist helps verify that an isolated gate driver matches the requirements of a given Si, SiC or GaN power stage. Each item can be reviewed against the target application before committing to a device family or layout.

• CMTI rating: Confirm that the driver’s specified common-mode transient immunity comfortably exceeds the planned dv/dt across the isolation barrier. For example, a design targeting 20–40 kV/μs at the switch node should use a driver with at least 100 kV/μs CMTI to allow for layout parasitics and worst-case operating conditions.
• Peak drive current: Check that the peak source and sink currents can charge and discharge the device gate charge within the desired switching interval when realistic external gate resistors are included. Higher gate current supports faster edges but raises EMI and CMTI stress.
• Separate Rg(on)/Rg(off) support: Ensure that the gate driver pinout and recommended connections allow independent turn-on and turn-off resistors so that dv/dt and di/dt can be tuned asymmetrically.
• Miller clamp availability: If the application is prone to high dv/dt or uses high-side devices with significant CGD, a built-in Miller clamp that engages near the gate threshold voltage is strongly recommended to prevent false turn-on.
• DESAT and over-current protection: For SiC and IGBT stages where short-circuit robustness is critical, verify that the driver includes DESAT detection with blanking time and soft turn-off, or that an equivalent fast over-current protection path is available in the system.
• UVLO thresholds: Review both primary-side and secondary-side UVLO levels. Logic-side UVLO should prevent operation with marginal controller supplies, while bias-side UVLO must ensure that the gate is not driven when isolated rails fall into an undefined region.
• CMOS vs GaN drive modes: Match the driver’s supported gate voltage range and features to the device technology. GaN FETs often need lower gate voltages, tighter clamps, very short dead times and sometimes special start-up sequencing compared to Si or SiC switches.
• Isolated bias requirements: Confirm the acceptable VDD/VEE range, start-up current, steady-state consumption and ripple tolerance. Cross-check these values against the planned transformer-based or module-based isolated supply for each channel.
• Fault signalling and latching behaviour: Check whether fault outputs are open-drain or push–pull, whether they can be wire-ORed, and how the driver behaves after a fault (latched-off, auto-retry, programmable through pins or resistors).
• Safety creepage and clearance: Ensure that the device package, insulation rating and PCB layout can meet system-level requirements for reinforced or basic insulation. Manufacturer drawings typically specify minimum creepage and clearance distances that must be preserved on the board.
• Channel count and configuration: Decide whether a single-channel, dual-channel or multi-channel driver is best suited to the topology. Dual-channel isolated drivers are convenient for half-bridges, while single-channel devices offer more placement freedom for distributed legs.
• Thermal and switching-frequency margins: Confirm that package thermal resistance and power dissipation are compatible with the planned switching frequency and gate charge so that the driver temperature stays within its specified range under worst-case operation.

IC role mapping for isolated gate driver selection

Once the checklist items are clear, driver choices can be mapped to a few recurring IC roles. The descriptions below help narrow down the search terms and feature sets for different power stages without tying the design to any single vendor.

• Capacitive isolator driver 100 kV/μs: Suited to many AC/DC, PFC and LLC stages where switch-node dv/dt is moderate and compact ICs are valued. These devices combine capacitive isolation with gate-drive stages and typically guarantee at least 100 kV/μs CMTI, making them appropriate for offline supplies and industrial converters with controlled layouts.
• Magnetic isolator driver 150 kV/μs: Intended for harsh industrial and traction environments where dv/dt can exceed tens of kV/μs and where additional CMTI margin is desirable. Magnetic coupling across the barrier supports higher transient immunity and robust reinforced insulation ratings when combined with suitable PCB creepage and clearance.
• SiC-optimized driver with DESAT: Includes strong peak drive currents, support for +15…+18 V / −3…−5 V gate bias, integrated DESAT detection, soft turn-off and often a Miller clamp. This role targets 650–1700 V SiC MOSFET or IGBT stages in motor drives, ESS and high-voltage DC/DC converters.
• Reinforced isolation driver for offline PSUs: Provides reinforced insulation for 85–264 VAC mains applications, with CMTI ratings that fit boost PFC and resonant half-bridge stages. These devices are commonly deployed in ATX/CRPS server PSUs, telecom rectifiers and industrial power systems.
• Dual-channel isolated driver for high-/low-side pairs: Integrates two matched channels in one package to drive complementary switches in a half-bridge. Symmetric propagation delays help maintain accurate dead times, and separate outputs simplify the use of independent Rg(on)/Rg(off) networks per device.
• Automotive-grade isolated driver for 48 V systems: Qualified to automotive standards and designed to withstand cold-crank, load-dump and EMI conditions on 48 V buses. These devices often support 10–12 V gate drive and moderate dv/dt with strong immunity to common-mode disturbances on long wiring harnesses.
• Gate driver with integrated isolated bias supply: Combines the isolation function, gate drive and a small isolated DC/DC converter in one IC or module. This role reduces BOM count and board area in compact adapters and low- to mid-power converters, at the cost of some flexibility in bias configuration.
• GaN-focused isolated driver: Optimized for low gate voltage ranges, very fast edges and fine dead-time control. These devices may include gate clamps, built-in level shifting and specialised protection suited to enhancement-mode GaN FETs in high-frequency adapters and power stages.

For each role, the final device choice should be cross-checked against the application’s CMTI target, gate-voltage requirements, protection scheme and isolation standard. The isolated gate driver then becomes a well-defined building block in the wider power-stage architecture rather than an isolated component choice.

Frequently asked questions about isolated gate drivers

This FAQ highlights how to match isolated gate drivers to real power stages by focusing on CMTI, Miller clamp usage, UVLO, DESAT, isolated bias design, layout and device technology. It can be used as a quick reference when tuning an existing design or selecting a driver family for a new topology.