Definitions (what each metric means)

In gate-driver timing, the same word often hides different reference points. This page uses the following strict meanings:

• tpLH: input rising edge to output rising edge delay (measured at a defined threshold).
• tpHL: input falling edge to output falling edge delay (measured at a defined threshold).
• tpd(avg): a stated average/typical delay derived from tpLH and tpHL (vendor-defined; must cite conditions).
• Channel-to-channel skew: delay difference between two channels under the same conditions and same measurement rule.
• Mismatch: a broader term; includes channel skew and device-to-device variation. This page treats skew as the primary controllable mismatch term.
• Jitter: time uncertainty of edge timing (must be paired with RMS/σ or pk-pk, window length, and bandwidth).

Deterministic vs Random (why the split matters)

• Deterministic components (fixed bias): channel architecture differences, layout asymmetry, supply/reference shifts, threshold offsets.
• Random components (jitter/uncertainty): noise-driven threshold crossing variability and measurement uncertainty (statistical).

Scope Guard (3-line boundary)

This page covers: propagation delay (tpLH/tpHL/tpd), channel-to-channel skew/matching, jitter definitions, and measurement/acceptance framing.

This page does NOT cover: deadtime algorithms, DESAT/Miller/two-level circuits, isolator encoding theory, EMI tuning.

If needed: deadtime/interlock → “Deadtime & Shoot-Through Interlock”; protection → “Protection & Control”; isolation → “Isolated Gate Driver / Combo”.

3-Phase Motor / Servo: small skew becomes electrical asymmetry

• Timing cause: channel-to-channel skew (Δtp) and edge uncertainty (jitter).
• Physical effect: effective duty/edge misalignment across phases.
• System symptoms: phase current imbalance, ripple growth, torque ripple, uneven thermal loading.

Multiphase VR: interleaving cancellation collapses with spacing error

• Timing cause: skew + drift over PVT; jitter widens instantaneous phase error distribution.
• Physical effect: ripple cancellation degrades; thermal spreading worsens.
• System symptoms: output ripple rises, hotspot on one phase, reduced transient margin.

Common field symptoms (timing-only triage table)

Path decomposition (segment the delay budget)

“Propagation delay” can refer to a driver’s internal delay or the full end-to-end timing from the controller to the effective gate edge. To remove ambiguity, delay is decomposed into measured segments:

This page treats driver tpd as TP2→TP3. System acceptance often requires end-to-end timing (TP1→TP3 or Gate*), but the responsibility remains traceable because each segment is measured separately.

Where skew is born (four sources that must not be mixed)

“Skew” is not a single mechanism. Separating the sources prevents incorrect blame on the driver IC when the measured mismatch is created elsewhere.

• Intra-channel asymmetry: tpLH ≠ tpHL (edge-direction dependence) → effective duty/phase bias.
• Inter-channel (same IC): channel-to-channel mismatch under identical conditions (closest to datasheet “matching”).
• Across isolation/interface: TP1→TP2 adds extra delay and jitter; can dominate in isolated systems.
• Layout / measurement induced: probe reference, return path, and test-point choice create apparent skew.

Measurement reference points (TP1 / TP2 / TP3)

Standardized test points align lab results, production tests, and field investigations. The same timing term becomes comparable only when the reference points are fixed.

• TP1: controller output (or isolator output) in the logic domain.
• TP2: gate-driver input pin (the driver’s timing reference input).
• TP3: gate-driver output pin (the driver’s timing reference output).

Using TP1/TP2/TP3 makes “driver tpd” and “end-to-end tpd” unambiguous: the difference is simply which test-point pair is used.

Propagation delay fields (typ / max / over-temp)

Propagation delay numbers are only comparable when the test conditions and reference rules match. Three fields are commonly misused:

• typ: design reference only; does not guarantee worst-case system behavior.
• max: usable for acceptance only when the conditions are understood (VDD, temperature, load, threshold, input slew).
• over-temp: may be a few temperature corners rather than a full sweep; the coverage must be confirmed.

Channel-to-channel matching (same device vs system-level)

Datasheet “channel matching” typically refers to intra-device skew (channels inside one package). System-level skew includes additional segments and must be treated separately.

• Intra-device skew: best approximated by measuring TP2→TP3 across channels on the same IC.
• System-level skew: includes TP1→TP2 (isolation/interface) and board-induced effects; it requires the segmented model from H2-03.

Jitter definitions (RMS vs pk-pk) & asymmetric delays (tpHL ≠ tpLH)

Jitter must be paired with a statistical definition and measurement bandwidth; tpHL/tpLH asymmetry must be treated as a directional timing bias.

• RMS (σ): distribution width; meaningful only with a stated window and bandwidth.
• pk-pk: window-dependent extreme spread; cannot be compared without the same observation window.
• tpHL ≠ tpLH: creates edge-direction dependence and can bias effective duty/phase; measure both edges explicitly.

Datasheet field mapping (field → trap → ask-back)

Use this table to translate datasheet timing fields into a measurement plan and to request missing conditions when needed.

Convert switching period to a time budget (Tsw → ns)

All ns-level timing targets start from the switching period. The first step is converting frequency into an explicit time scale:

For phase-controlled systems, phase error can also be expressed as a time error:

Duty/phase constraint (budget-only, no algorithm details)

Skew and jitter consume the same resource: timing margin. The derivation must declare which margin is being protected.

• Deterministic skew introduces a fixed bias (effective duty/phase offset) that directly erodes timing margin.
• Random jitter widens the timing distribution and must be bounded statistically over a stated observation window.
• Windows and margins (deadtime / alignment / sampling windows) must remain valid after skew+jitter are applied.

Practical targets (where “few ns” comes from)

A practical target is derived by selecting the most restrictive constraint in time and applying a conservative allocation:

Next, allocate the end-to-end budget into measurable segments defined in H2-03:

Reusable budget template (copy/paste)

This template converts system constraints into an acceptance target without requiring control algorithm details.

Deterministic components (bounded, traceable)

Deterministic timing error appears as a repeatable bias under the same conditions. It is managed by bounding each contributor and tying it to a segment.

• Device mismatch: intra-device channel mismatch and device-to-device variation.
• Supply/operating point shifts: VDD and temperature shifts changing thresholds and delay.
• Threshold definition shifts: different crossing rules or slow edges changing the observed delay.
• Layout / measurement bias: reference point and probing method creating apparent skew.

Random components (statistical, window-dependent)

Random timing error cannot be “calibrated away” in acceptance. It must be declared with its statistical definition and observation conditions.

• Threshold crossing noise: time uncertainty due to noise and finite slew.
• Interface uncertainty: added edge uncertainty introduced by interface / isolation segments.
• Measurement noise: instrument timebase and probe-induced uncertainty.

Combining rule (worst-case vs RSS): when to use which

The combining method is a policy decision tied to risk and the maturity of the measurement definition.

Acceptance-ready expression (single inequality)

A timing requirement becomes testable when deterministic skew and random jitter are combined into one stated inequality:

This structure supports traceability: μ_skew is typically dominated by deterministic contributors, while σ_jitter captures the random distribution width. Both are then compared against the derived budget from H2-05.

Error decomposition & combining template (engineering worksheet)

Symmetry rules (routing / components / return path)

Few-ns matching is not achieved by “equal length” alone. The goal is that both channels present the same edge shape and the same reference conditions at the chosen timing reference points (TP2/TP3).

Input conditioning (single-ended vs differential: timing impact only)

Input choices affect timing because they change where the threshold crossing occurs and how sensitive that crossing is to noise.

• Single-ended inputs: threshold is referenced to local ground; ground movement and noise convert directly into crossing time variation.
• Differential inputs: more robust to common-mode shifts; timing still depends on differential slew and bias/common-mode compliance.

Power integrity for timing (how supply ripple maps into tpd variation)

Driver timing is operating-point dependent. Supply ripple and droop can shift delay and mismatch by changing internal thresholds and output stage behavior.

• Slow supply drift: appears as deterministic delay shift (μ change) across operating corners.
• Fast supply noise: appears as timing spread (σ change), often correlated with switching activity.
• Asymmetric decoupling/return: converts supply events into channel-to-channel mismatch (Δtp increases).

Board-level matching checklist (actionable items)

The checklist below is structured by “symmetry points” so it can be reused in an engineering checklist and applied across topologies.

Copy-ready symmetry checklist (Engineering Checklist insert)

Instrument choices (scope vs time-interval statistics tools)

The tool should match the question. Waveform insight and time-interval statistics are different requirements.

• Oscilloscope: best for correlating timing with edge shape and diagnosing causes; results depend strongly on threshold, bandwidth, and probing.
• Time-interval / TIE tools: best for high-resolution timing distribution and RMS jitter statistics over long windows.

Trigger & threshold strategy (fixed vs ratio; rise/fall separated)

Timing results are only comparable when the threshold rule and triggering strategy are fixed and recorded.

• Slow edges + noise increase crossing sensitivity → σ changes with threshold choice.
• Trigger mismatch (trigger at TP1, measure at TP3) can introduce apparent variability when references move.

Statistics: sample count, window length, RMS vs pk-pk

Jitter is a distribution. pk-pk depends on observation window; RMS requires a stated bandwidth and window.

Common mistakes (why measured skew looks unstable)

• Probe ground bounce: long ground leads create apparent timing movement.
• Threshold drift: changing rule or inconsistent channel thresholds shifts μ and σ.
• Reference point mismatch: TP definitions differ across channels or across lab setups.
• Bandwidth mismatch: different filtering changes edge shape and crossing time.

Measurement SOP (steps + record fields + pass/fail interpretation)

This SOP makes delay/skew/jitter measurements repeatable across benches and labs.

Temperature drift signatures (tpd vs T, skew vs T)

Timing stability is defined by how both mean delay (μ) and channel mismatch (Δ) move over temperature. A stable room-temperature number can fail once the drift becomes asymmetric.

Supply sensitivity (VDD and UVLO-edge behavior)

Supply variation can shift delay nonlinearly, especially near UVLO edges or during droop events. This affects both tpd and skew, and often introduces rise/fall asymmetry.

• VDD shift: operating point changes → μ_tpd drifts across corners.
• UVLO-edge proximity: delay distortion can increase rapidly and become asymmetric.
• Channel asymmetry: unequal decoupling/return makes the same droop event create different timing shifts per channel.

Aging as a required axis (without deep modeling)

Aging is treated as an additional validation axis. Instead of relying on a lifetime model, the measurement plan includes “after stress / after soak” checkpoints and compares results using the same reporting contract.

Compensation options (calibration / binning / phase offsets)

Compensation is framed by interfaces and acceptance criteria, not by algorithm details.

• Factory calibration: measure μ_skew at reference corners and store offsets for later application.
• Binning / pairing: reduce worst-case mismatch by screening to a defined timing bin.
• Software phase offsets: apply corner-aware offsets using available telemetry (temperature/supply states).

Output: PVT test matrix template (copy-ready)

This matrix standardizes what is recorded at each Temperature × Voltage point. Threshold rule, bandwidth, and window must remain fixed for comparability.

Differential vs single-ended: threshold uncertainty → jitter path

Interface choice influences timing because it changes how the threshold crossing responds to noise and reference movement.

Across isolation: separate “driver tpd” from “interface/isolation tpd”

End-to-end acceptance uses a full TP pair, but root-cause and budgeting require segmentation.

Skew budgeting at the interface: where to reserve margin

Budget should reflect the nature of each error term: deterministic mismatch (μ) vs random spread (σ).

• Budget allocation: Budget_E2E = Budget_in + Budget_driver + Budget_meas (placeholders).
• Interface emphasis: interface/isolation often dominates σ; reserve margin where σ is expected.
• Acceptance policy: keep one combining policy across segments (e.g., |μ| + n·σ ≤ Budget).

Output: interface timing comparison table (selection-focused)

This table compares options by timing risk, measurement method, and mitigation handle (no brand comparisons).

Copy-ready responsibility boundary statement (spec insert)