SiC MOSFET Driver: CMTI, Miller Clamp & <2 µs SC
H2-1. Definition & Scope: What a SiC MOSFET Driver Must Guarantee
A SiC MOSFET driver is not “just a gate buffer.” It is a guarantee layer that keeps dv/dt-induced errors, short-circuit energy, and gate-voltage stress inside a verifiable window—without drifting in real hardware.
What it is (function stack)
A SiC driver is a coordinated stack of: input interface → isolation (if required) → gate-voltage rails → gate-edge shaping → fault detection → forced safe turn-off. The stack is judged by measured outcomes, not by a single datasheet number.
Interface
Isolation
±Vgs Rails
Edge Control
Fast Fault-Off
What makes it “SiC-grade”
“SiC-grade” means the driver can remain stable under very fast dv/dt and high common-mode stress, while enforcing a tight gate window (e.g., +Vg with optional −Voff) and meeting a sub-microsecond-class protection deadline in a real half-bridge environment.
Core theme: dv/dt immunity + protection timing decide survival; everything else is secondary.
Deliverables (guarantees + acceptance placeholders)
-
dv/dt immunity: no false turn-on under dv/dt = X kV/µs for Y stress events.
Pass: Vgs bump < X V; mis-trigger count N=0. -
Short-circuit response: forced safe turn-off within X µs from SC onset (budgeted chain).
Pass: t_shutdown ≤ X µs; E_sc ≤ Y (units per system spec); no device damage. -
Vgs window control: +Vgs / −Voff and overshoot/undershoot remain inside a defined window.
Pass: Vgs_peak ≤ X V; Vgs_min ≥ −Y V; UVLO chatter N=0. -
Timing integrity: channel skew and jitter do not break PWM resolution or symmetry.
Pass: skew ≤ X ns; symmetry drift ≤ Y over temperature window.
What this page covers / excludes (owner-map rule)
This page owns SiC-specific windows and deadlines: dv/dt/CMTI robustness, Miller false turn-on control, ±Vgs rails strategy, and short-circuit timing budget.
- Not covered here: bootstrap details, bridge topology interlocks, general isolator fundamentals, generic DESAT theory.
- Action: use a one-sentence definition + a link to the owner page for those topics.
H2-2. Why SiC Is Different: dv/dt, Miller, and the Short-Circuit Deadline
SiC fails differently because dv/dt is faster, the common-mode transient is harsher, and the short-circuit energy accumulates quickly. The key is to convert “SiC is fast” into a bounded risk chain with knobs and pass criteria.
Failure modes map (observable symptoms)
- False turn-on / shoot-through spikes: gate bump crosses the effective turn-on threshold.
- Nuisance protection trips: DESAT/OC triggers under dv/dt stress without a real fault.
- “Bench OK, inverter fails”: measurement loop hides true Vgs ringing or CM return path.
- SC shuts down but device dies: turn-off energy/overshoot is not bounded.
- One leg overheats: timing/layout asymmetry shifts losses and EMI to one arm.
First priority in triage: identify whether the signature matches gate bump, logic upset, or hard turn-off overshoot.
What must be bounded (the “cage”)
- Vgs window: peak/valley + ringing must not cross unsafe regions (reliability + false turn-on).
- Short-circuit energy: E_sc is dominated by the shutdown timeline and the turn-off trajectory.
- CMTI / dv/dt immunity: CM transient must not flip inputs, bias the reference, or inject into gate.
- Gate loop parasitics: loop inductance turns every edge knob into ringing and EMI if not controlled.
Acceptance placeholders: Vgs_peak ≤ X V; Vgs_min ≥ −Y V; dv/dt = X kV/µs with mis-trigger N=0;
t_shutdown ≤ X µs; overshoot within X.
Design knobs mapping (knob → boundary → side effect)
- −Voff rail: reduces Miller false turn-on → may increase gate stress and demands strong driver capability.
- Active Miller clamp: hard blocks gate rise during plateau → requires correct reference (Kelvin-S) and tight layout.
- Split Rg / two-level turn-off: balances EMI vs overshoot vs loss → slow turn-off may increase E_sc if a fault occurs.
- Gate loop layout: sets the “real” ringing and immunity → poor layout makes every other knob non-deterministic.
- Protection timing budget: defines E_sc survival window → too aggressive causes nuisance trips; too slow causes damage.
Tuning order (to avoid chasing ghosts): layout & rails → clamp reference → edge shaping → protection timing → EMI polish.
H2-3. System Architecture Choices (for SiC): Isolation, Bias, Sensing, and Fault Loops
SiC gate-drive architecture is determined by two hard constraints: dv/dt-driven common-mode stress and a short-circuit shutdown deadline. The architecture must keep references stable, preserve timing symmetry, and enforce a local hardware safe-off path when faults occur.
Architecture options (A / B / C)
-
A) Isolated gate driver (integrated):
What it is: isolation + driver in one stage.
Buys: tighter channel matching, simpler timing chain.
Costs: barrier capacitance and thermal coupling must be audited.
Fits: multi-bridge inverters, tight skew budgets. -
B) Digital isolator + gate driver (discrete):
What it is: isolator stage feeds a separate driver stage.
Buys: flexible partitioning and component-level tuning.
Costs: added skew sources; more places to leak CM current.
Fits: platforms needing modularity or pin-compatible swaps. -
C) Driver + integrated isolated bias / sensing:
What it is: driver plus isolated bias generation and/or telemetry hooks.
Buys: faster integration, fewer external rails, shorter fault chain.
Costs: bias noise/regulation behavior must be validated under dv/dt.
Fits: high-power density stages where wiring and rails dominate risk.
When to choose each (application buckets)
-
Traction inverter: prioritize local safe-off dominance, robust fault latching, and stable references under harsh dv/dt.
Selection bias: A or C when skew and protection chain must be tightly controlled. -
PV / ESS inverters & DC-DC: prioritize timing consistency across many channels and bias-noise coordination with sampling windows.
Selection bias: A for tight skew; C when isolated bias distribution is the bottleneck. -
PFC + HB/FB/LLC: prioritize edge programmability and repeatable turn-off behavior across temperature and load states.
Selection bias: B when partitioning is needed; A/C when integration shortens the fault chain.
Acceptance placeholders: mis-trigger N=0 at dv/dt=X kV/µs; channel skew ≤ X ns; fault-to-safe-off ≤ X µs.
Hidden costs (must be surfaced early)
-
Symptom: random false turn-on only in system
Root: CM current shifts input/driver reference via barrier capacitance
First check: return-path definition + barrier C + bias decoupling placement -
Symptom: one leg runs hotter / EMI differs by arm
Root: propagation delay mismatch and layout asymmetry amplify losses
First check: skew over temperature + symmetric gate loop geometry -
Symptom: SC shuts down but device damage occurs
Root: fault chain too slow or turn-off path too inductive (overshoot energy)
First check: detect/blank/filter/turn-off timing budget + clamp current path -
Symptom: UVLO chatter during transients
Root: isolated bias droop/noise or insufficient UVLO hysteresis for SiC rails
First check: bias reservoir + UVLO ON/OFF thresholds and hysteresis
H2-4. Key Specs That Actually Matter (SiC Driver Spec Hierarchy)
In SiC systems, a few specs are must-not-fail. The numeric value is only meaningful when the test condition and dv/dt direction are known. The hierarchy below prevents selection from being driven by secondary figures.
Top-5 metrics (why they matter)
-
CMTI / dv/dt immunity: prevents false triggering and logic upset under fast common-mode steps.
Failure: intermittent shoot-through spikes or spurious faults.
Ask: dv/dt direction, Vcm step, and pass/fail definition. -
Protection response time budget: bounds short-circuit energy within the device survival window.
Failure: “shutdown occurs but device damage follows” due to late or hard turn-off.
Ask: detect/blank/filter/turn-off timeline and conditions. -
Vgs range + UVLO thresholds: avoids half-conduction loss and enforces a safe gate-voltage window.
Failure: UVLO chatter, partial turn-on, or over/undershoot risk.
Ask: separate ON/OFF thresholds, hysteresis, and rail collapse behavior. -
Propagation delay / skew: preserves bridge symmetry and PWM resolution (multi-bridge/multi-phase).
Failure: one arm runs hotter, EMI differs, or control bandwidth shrinks.
Ask: skew across channels and over temperature; does it include isolation. -
Peak source/sink current: sets achievable tr/tf for a given Qg and switching frequency target.
Failure: slow edges raise loss; overly fast edges raise ringing/EMI.
Ask: how peak current is defined (Vout point), source vs sink asymmetry.
How to read datasheet traps (test-conditions checklist)
- CMTI: dv/dt direction stated? (positive/negative) • Vcm step amplitude? • output error criteria?
- Delay / skew: includes isolator or driver-only? • measured at which threshold/edge? • temp dependence provided?
- Peak current: defined at what Vout? • recommended Rg range? • sink/source mismatch specified?
- UVLO: separate ON/OFF thresholds? • hysteresis size? • behavior when −Voff rail droops first?
- Protection timing: blanking programmable? • soft turn-off profile defined? • latch vs auto-retry conditions clear?
Rule: compare specs only after normalizing conditions. “Higher number” without conditions is not actionable.
Pass criteria placeholders (X / Y / N)
- CMTI: dv/dt = X kV/µs, Vcm step = Y V, mis-trigger count N=0.
- Skew: channel skew ≤ X ns over temperature window Y.
- Vgs window: Vgs_peak ≤ X V; Vgs_min ≥ −Y V; ringing cycles ≤ N.
- SC shutdown: t_shutdown ≤ X µs; overshoot ≤ Y; E_sc ≤ Z (per system units).
- Drive strength: meet target tr/tf at Qg=X nC and fsw=Y with EMI delta within N.
H2-5. Gate Voltage Rails (+18 / −3…−5 V) & UVLO Strategy
SiC gate-voltage strategy is defined by a Vgs operating window: the positive rail for performance, the optional negative rail for dv/dt immunity, and UVLO thresholds that prevent half-conduction and enforce a safe default state during brownout and faults.
Rail options matrix (+/− rails)
-
+15 V only: moderate switching performance with reduced gate stress.
Trade: less margin against Miller-induced false turn-on at very high dv/dt. -
+18 V only: stronger drive margin for low Rds(on) region and faster transitions.
Trade: tighter overshoot control and stronger UVLO discipline are required. -
+18 V / −3 V: improved dv/dt immunity with modest negative stress.
Trade: negative rail stability must be validated during transients and recovery. -
+18 V / −5 V: maximum false-turn-on suppression for harsh dv/dt environments.
Trade: higher gate stress and higher sink capability demand; strong clamp/reference integrity required.
Selection rule: negative rails are justified when false turn-on risk dominates; otherwise prioritize a stable positive window with controlled overshoot.
UVLO window rules (avoid half-conduction)
-
Independent ON/OFF thresholds + hysteresis: prevents threshold chatter under bias noise and dv/dt injection.
Quick check: UVLO toggles N=0 during dv/dt=X kV/µs stress and load steps.
Pass: no partial gate pulses; threshold stability within X (units per design). -
Window alignment with +Vg rail: if +Vg is not sufficient, forced OFF is safer than a gray region.
Quick check: rail droop tests show no long dwell inside the undefined region.
Pass: undefined-region dwell ≤ X µs (placeholder). -
Negative-rail aware behavior (when −Voff is used): a collapsed −V rail must not silently reduce immunity.
Quick check: test both sequences: −V collapses first, +V collapses first.
Pass: safe OFF maintained; no false turn-on events (N=0).
Fault & brownout behavior (priority and safe state)
- Default OFF: reset/unknown states force gate OFF (no ambiguity).
- Fault dominance: once a fault is asserted, hardware safe-off cannot be overridden by PWM.
- Brownout precedence: when rails are not trusted (UVLO active), OFF dominates over partial ON.
- Recovery policy: latch vs auto-retry is chosen by system risk; recovery must be non-chattering.
Acceptance placeholders: fault-to-OFF ≤ X µs; brownout sequence yields N=0 mis-triggers; Vgs stays inside window limits (X/Y).
H2-6. Edge Control: Split Rg, Slew-Rate Programming, and Two-Level Turn-Off
Edge control converts the EMI vs loss vs ringing trade into a set of repeatable knobs. In SiC, turn-off is particularly sensitive: overshoot control must not compromise the short-circuit deadline, and layout inductance can dominate outcomes if tuning starts from the wrong place.
Knob-to-effect map (directional outcomes)
- Rg,on ↑: EMI ↓ • switching loss ↑ • ringing ↓ (typical trend)
- Rg,off ↑: overshoot ↓ • turn-off loss ↑ • SC energy risk ↑ (key side-effect)
- Slew-rate limit: EMI ↓ • loss ↑ • dv/dt-induced mis-trigger risk ↓
- Two-level turn-off: fast initial clamp + gentle tail → overshoot ↓ while preserving safe-off timing
- Ferrite bead: strong HF ringing damping but can be non-linear with temperature/current
- Series resistor: predictable damping; may require additional HF measures for very fast edges
Common trap: increasing Rg,off to reduce overshoot can violate the short-circuit energy window if fault timing is not re-budgeted.
Recommended tuning sequence (avoid chasing ghosts)
- Layout & rails sanity: verify Kelvin source reference and stable ±V rails.
- Baseline Rg: achieve stable switching with no false turn-on events (N=0).
- Split Rg,on/off: separate turn-on and turn-off objectives.
- Two-level turn-off / slew: resolve overshoot vs EMI conflict with controlled shaping.
- Ferrite/RC polish: final ringing and EMI trimming without changing the protection budget.
Stop rule: if mis-trigger appears, return to reference integrity and clamp/rail checks before continuing knob tuning.
Pass criteria placeholders (X / Y / N)
- Overshoot/undershoot: Vds overshoot ≤ X; Vgs_peak ≤ X; Vgs_min ≥ −Y.
- Ringing: ringing cycles ≤ N; residual HF amplitude ≤ X (placeholder).
- EMI delta: tuning step changes EMI by ≤ X dB in the target band (placeholder).
- Loss/thermal: efficiency or temperature rise shift ≤ X (placeholder).
- Fault compatibility: fault-to-safe-off ≤ X µs remains satisfied after tuning.
H2-7. Active Miller Clamp & False Turn-On Immunity (SiC Focus)
SiC false turn-on is a dv/dt-driven injection problem: common-mode stress and Cgd coupling can create a Vgs bump during turn-off. An active Miller clamp is the hardware guardrail that clamps the gate to a stable reference when the device must remain OFF.
False turn-on symptom → suspect list
-
Symptom: shoot-through spikes during the opposite switch dv/dt event
First suspect: Cgd injection + insufficient OFF stiffness (no clamp / wrong reference)
Quick check: compare Vgs at Kelvin source vs power source reference -
Symptom: intermittent trips or random overcurrent events at high bus voltage
First suspect: clamp timing does not cover plateau region; OFF window is not enforced
Quick check: correlate events with switching edges and Vgs bump occurrences -
Symptom: false turn-on appears only at high temperature
First suspect: reference shift and loop impedance increase; clamp path too long
Quick check: repeat waveforms across temperature corners and monitor gate current -
Symptom: negative rail present but mis-trigger remains
First suspect: −Voff improves margin but does not clamp the injected current path
Quick check: verify clamp conduction and the clamp reference node
Practical rule: if dv/dt events produce measurable Vgs bumps, clamp effectiveness is determined by reference and loop length, not by a negative rail alone.
Clamp design rules (short path, Kelvin reference)
- MUST: clamp return to Kelvin Source (quiet source reference).
- MUST: clamp loop physically short; minimal loop area between gate and clamp device.
- MUST: clamp path avoid sharing high di/dt power-source return segments.
- MUST: clamp enable covers the OFF interval around the plateau region.
- AVOID: clamp return to Power Source (reference shift under load current).
- AVOID: long via chains and routes that cross partitions or noisy reference planes.
- COORDINATE: −Voff provides margin; clamp provides the hard sink path for injected charge.
Goal: injected current is diverted into the clamp loop referenced to Kelvin source, keeping Vgs below the false-turn-on boundary.
Validation checks (waveforms, temperature, gate current)
- Waveform window: Vgs bump amplitude ≤ X, duration ≤ Y, and mis-trigger count N=0 at dv/dt=X kV/µs.
- Clamp engagement: clamp conduction observable during OFF dv/dt events (gate current signature present).
- Reference integrity: Kelvin-source-referenced Vgs remains stable while power-source node shifts under load.
- Corner stress: validate at high temperature, high bus voltage, and fastest edges; results must remain repeatable.
Pass criteria placeholders: bump ≤ X V, N=0 across Y minutes, and stable behavior across temperature window Y.
H2-8. Short-Circuit Protection (<2 µs): DESAT Chain & Soft Turn-Off (SiC Deadline)
The “<2 µs” requirement must be treated as a timing budget contract. The protection chain is decomposed into detect, blanking, decision/reaction, and turn-off shaping. Each knob must reduce false trips without exceeding the survival deadline.
Timing budget (placeholders)
- t_detect = X (sense + threshold crossing)
- t_blank = Y (intentional ignore window; must not exceed the energy window)
- t_react = Z (logic + driver response to initiate safe-off)
- t_off = N (soft turn-off + clamp phase)
- Total ≤ X µs (deadline contract)
Common stretch sources: excessive filtering, long propagation paths, and overly gentle soft turn-off that extends t_off.
Tuning steps (from “survive” to “minimum false trips”)
- Lock the deadline: ensure total chain ≤ X µs under worst-case corners.
- Control Vds peak: shape turn-off to reduce overshoot without expanding total budget.
- Reduce false trips: adjust DESAT threshold, blanking, and filter with budget re-check each step.
- Define recovery: choose latch vs auto-retry and enforce non-chattering behavior.
Stop rule: if a tuning change increases total timing beyond the deadline, revert immediately before optimizing false-trip rate.
Pass criteria placeholders (energy, peak voltage, recovery)
- E_sc ≤ X (system units placeholder) under worst bus voltage and temperature.
- Vds_peak ≤ Y during fault turn-off (overshoot controlled).
- t_safe-off ≤ X µs (fault-to-safe-off deadline met).
- Recovery behavior: latch or auto-retry follows policy; retry count ≤ N; no oscillation.
- Repeatability: results stable across temperature window Y and dv/dt corners.
Passing requires a combined result: deadline met, energy bounded, overshoot controlled, and recovery policy deterministic.
H2-9. CMTI / dv/dt Hardening: What “100–200 kV/µs” Really Requires
CMTI is not “just a number”. A dv/dt event creates displacement current that must return somewhere. If the return path runs through the input reference or gate reference, the result can be logic upset or a Vgs bump. Hardening means: (1) interpret the spec with correct conditions, (2) control CM current paths, and (3) validate with a repeatable dv/dt step test.
CMTI number interpretation checklist
- dv/dt direction defined? (+/− step can stress different internal nodes)
- CM step amplitude defined? (edge shape + overshoot matter, not only slope)
- Input state defined? (high/low/open/filtered changes susceptibility)
- Output allowed behavior defined? (no pulse vs bounded glitch window)
- Reference node defined? (input reference and output reference must be explicit)
- Repetition & duration defined? (single event vs repeated bursts)
- Fixture/cable implied? (parasitics can dominate the measured result)
- Guaranteed vs typical? (use guaranteed conditions for pass/fail contracts)
The same “CMTI” headline can represent very different immunity if direction, step waveform, and reference are not aligned.
CM current path control checklist
- Define the return path: CM displacement current must return in a controlled reference domain.
- Barrier capacitance is real: Ciso and parasitics will conduct dv/dt current.
- Protect the input reference: avoid reference lift that turns into logic threshold errors.
- Protect the gate reference: prevent CM current from creating a Vgs bump at the OFF boundary.
- Prefer closed local loops: avoid “return by chassis/ground” assumptions in fast dv/dt systems.
- Partition correctly: control returns must not cross power return splits or noisy segments.
- Filter with budget awareness: RC filtering can help, but must not break timing/protection budgets.
Hardening is achieved by routing CM current away from sensitive references, not by expecting the current to disappear.
Pass criteria placeholders (dv/dt step, no false trigger)
- dv/dt step: slope = X kV/µs, amplitude = Y V (placeholders).
- Repetition: N events per burst for Y minutes at temperature corner Y.
- No false trigger: output does not create unsafe pulses (N=0 false turn-ons).
- Bounded behavior: if any bounded glitch is allowed, duration ≤ X (placeholder) and does not cross enable thresholds.
- Repeatability: results stable across direction (+/− dv/dt) and corner conditions.
A pass contract requires defined step waveform + defined input state + defined output expectation, not only a CMTI headline.
H2-10. Layout & Gate Loop Parasitics (SiC Layout Rules That Move the Needle)
SiC gate behavior is dominated by the gate loop and reference integrity. Layout must enforce a tight gate loop, a Kelvin source reference, correct driver supply decoupling, and strict return-path partitioning. This section provides executable rules and inspection items (not a generic PCB tutorial).
Placement priority list (what to place first)
- Driver → SiC MOSFET: place driver closest to the gate pins and Kelvin source reference.
- Rg adjacent to gate: Rg sits at the gate pin region to control the local loop.
- Clamp adjacent to gate/ref: clamp return must reference Kelvin source (short loop).
- Local decoupling next: driver supply reservoir placed at driver supply pins with a closed return.
- Symmetry: mirror placement between legs/phases to reduce mismatch and drift sensitivity.
Placement decides the loop inductance ceiling; tuning Rg/slew cannot compensate for a large gate loop.
Routing do / don’t (tight loop, closed return)
DO
- Keep gate and return tightly coupled (minimum loop area).
- Route Kelvin source directly back to driver reference.
- Use short, wide traces where current pulses flow.
- Minimize vias; avoid via chains in the gate loop.
- Maintain symmetry across legs/phases.
DON’T
- Do not reference gate return to power source (shared di/dt return).
- Do not cross splits with sensitive returns.
- Do not create large loop areas with long gate traces.
- Do not place Rg far from the gate pin region.
- Do not rely on chassis/earth as an undefined return path.
Routing objective: prevent reference shift and loop inductance from turning dv/dt into Vgs bumps and ringing.
Inspection checklist (production-review friendly)
- Kelvin S present and independent: returns directly to driver reference (no shared power-S segment).
- Gate loop is tight: loop area minimized; key distance ≤ X (placeholder).
- Rg/clamp location: adjacent to gate region; clamp return to Kelvin S (short loop).
- Driver decoupling: reservoir at driver pins with closed return; no long supply loop.
- Partition integrity: control returns do not cross power splits; return paths are explicit.
- Acceptance placeholders: overshoot ≤ X, ringing cycles ≤ N, false trigger N=0 under dv/dt=X.
Review intent: rules must be verifiable by layout inspection and remain repeatable in production.
H2-11. Validation & Bring-up Playbook (Double-Pulse, Fault Injection, Acceptance Gates)
Goal: reproducible acceptance
Focus: SiC dv/dt / CMTI / <2 µs SC
Output: pass/fail gates
What this section must deliver A validation contract that can be repeated across benches and teams: fixed test sequence, mandatory captures, stop rules, and acceptance gates for dv/dt immunity, false turn-on, and short-circuit shutdown deadlines.
Reference build for a known-good baseline (examples, not exhaustive): UCC21732QDWEVM-025 (TI EVM platform), SN6505BDBVR (push-pull transformer driver on the EVM), TPS70950DBVR (LDO on the EVM).
Bring-up sequence (bench → stress → production)
Step 1 — Bench sanity Verify rails, UVLO behavior, /FLT wiring, default-safe-off state, and no unexpected pulses with PWM disabled.
Step 2 — Double-pulse test (DPT) Capture Vgs / Vds / Id with declared reference points (Kelvin source vs power source) and a consistent probe loop definition.
Step 3 — dv/dt step immunity Apply a controlled common-mode edge and check for zero dangerous output falsing under repeated stress (X/Y/N placeholders below).
Step 4 — Short-circuit (SC) progression Progress from low-energy conditions toward the target corner while enforcing stop rules and logging shutdown timing.
Step 5 — EMC precheck gate Validate that edge-control knobs (Rg split / two-level turn-off / clamp) move emissions in the expected direction without breaking dv/dt immunity.
Step 6 — Production gates Convert bench results into guardbands and define inspectable layout + assembly checks (routing symmetry, Kelvin return, clamp placement).
Instrumentation hooks (make results comparable)
Mandatory declarations (always written into the test log)
- Vgs reference: Kelvin source (preferred) vs power source (must be stated).
- Vds sensing: method and loop constraints (placeholders: loop length ≤ X, bandwidth ≥ Y).
- Trigger rule: dv/dt edge / DESAT trip / overcurrent event (pick one, document it).
- Record pack: bus voltage, temperature, +Vg/−Voff rails, Rg_on/Rg_off, deadtime, clamp enable state.
Practical baseline platforms (examples): UCC21732QDWEVM-025 (TI), SECO-NCD57000-GEVB (onsemi), EVAL-1ED3122MX12H (Infineon), EB1200M62-355JC (Broadcom ACPL-355JC eval setup).
Acceptance gates (placeholders X / Y / N)
DPT gate
- Vgs overshoot ≤ X V; Vgs undershoot ≥ −X V.
- Vds overshoot ≤ Y V; ringing cycles ≤ N (same probe method each run).
- Gate bump during opposite-switch dv/dt: peak ≤ X V and duration ≤ Y ns.
dv/dt immunity gate
- dv/dt step = X kV/µs, amplitude = Y V, repetitions = N → dangerous falsing count = 0.
- /FLT behavior and reset policy follow the declared safety strategy (latch vs retry).
Short-circuit gate
- t_detect + t_blanking + t_safe-off ≤ X µs (budget must be logged, not assumed).
- Energy and voltage limits remain bounded: E_sc ≤ X, Vds_peak ≤ Y (placeholders).
- Stop rules enforced: any drift across N repeats triggers rollback and root-cause review.
H2-12. Applications & IC Selection (SiC Driver) — Playbooks + Selection Logic
Apps → required feature gates
Selection → 5-step decision tree
Includes example part numbers
Scope lock This section lists application playbooks and a selection logic only. It does not explain converter topologies, isolation standards in depth, or generic protection theory.
Application buckets → required driver feature set
Traction inverter (EV/HEV)
- Reinforced isolation + robust dv/dt immunity (target class 100–200 kV/µs).
- −Voff support (−3…−5 V class) + active Miller clamp.
- Fast SC protection chain (deadline < X µs) + soft turn-off.
- Fault reporting (/FLT) and deterministic disable behavior.
Example driver IC part numbers: UCC21750, UCC21732, UCC21732-Q1, NCD57000, 1ED3122MU12H, ACPL-355JC.
PV / ESS inverters & DC-DC
- dv/dt immunity prioritized over “headline peak current.”
- Stable UVLO windows to prevent half-conduction in brownouts.
- Protection policy: latch vs retry aligned with thermal management.
Example driver IC part numbers: UCC21750, UCC21732, NCD57000, ACPL-355JC.
PFC + bridge stages (hard-switching corners)
- Edge control knobs: split Rg + two-level turn-off to balance EMI vs loss.
- Clamp placement + Kelvin reference to suppress false turn-on.
- SC response budget must be verified, not assumed.
Example driver IC part numbers: UCC21732, UCC21750, 1ED3122MU12H.
Industrial drives / servo
- Timing matching and consistent fault behavior across channels.
- Production correlation: guardbands + inspectable layout rules.
- Serviceability: clear /FLT signaling and reset logic.
Example driver IC part numbers: UCC21732, NCD57000, ACPL-355JC, 1ED3122MU12H.
Selection decision tree (5 steps that prevent the classic traps)
Step 1 — Isolation class Decide reinforced/basic isolation first → choose isolated gate driver vs isolator + non-isolated driver.
Step 2 — Gate rails window Determine +Vg and −Voff needs (performance vs dv/dt false turn-on margin) → lock UVLO on/off strategy.
Step 3 — Protection deadline If short-circuit safe-off must be < X µs → prioritize DESAT/OC chain timing and soft turn-off behavior.
Step 4 — Channel & timing Set channel count and matching/skew constraints (multi-bridge and 3-phase systems demand deterministic timing).
Step 5 — Integration level Choose integration (fault reporting, sensing, bias generation strategy) based on noise budget and serviceability.
Concrete part-number shortlist (anchor list)
Isolated SiC-capable gate driver ICs (examples)
- Texas Instruments: UCC21750, UCC21732, UCC21732-Q1
- onsemi: NCD57000
- Infineon: 1ED3122MU12H
- Broadcom: ACPL-355JC
Validation baseline boards (examples)
- TI: UCC21732QDWEVM-025
- onsemi: SECO-NCD57000-GEVB
- Infineon: EVAL-1ED3122MX12H
- Broadcom: EB1200M62-355JC
Common “bias building blocks” seen in reference designs (examples)
- Push-pull transformer driver: SN6505BDBVR
- Primary-side LDO (5 V): TPS70950DBVR
Use case note: automotive/traction projects typically require qualified versions and full safety documentation; the decision tree above locks requirements first, then validates on a reproducible platform.
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H2-13. FAQs (Field Debug & Acceptance Disputes)
Scope lock: only CMTI/dv/dt return paths, Miller clamp, −Voff window, short-circuit protection timing, layout gate-loop parasitics, and validation/bring-up acceptance gates. Each answer is a 4-line, measurable contract (X/Y/N placeholders).
Pass/Fail contract reminder: always state the test condition (dv/dt = X kV/µs at Y V, repetitions N) and the measurement reference
(Kelvin source vs power source). “Looks fine” is not an acceptance criterion.
Datasheet claims 150 kV/µs CMTI, but false turn-on still happens—first suspect which return path?
Likely cause:Common-mode displacement current returns through the input/gate reference (Ciso/parasitics) and lifts the reference, creating a Vgs bump.
Quick check:Run a controlled dv/dt step (± directions) and measure OFF-state Vgs bump using Kelvin-source reference; repeat with the “suspected return” intentionally altered.
Fix:Re-route/contain CM return (partition + shortest local return), protect the input reference (RC filter within timing budget), and tighten the gate loop + clamp reference to Kelvin source.
Pass criteria:At dv/dt=X kV/µs, ΔV=Y V, repeats=N: false turn-on count=0; OFF-state Vgs bump ≤ X V and duration ≤ Y ns.
Adding −5 V fixed false turn-on, but losses/EMI got worse—what knob to adjust next?
Likely cause:Negative bias solved Vgs margin, but edge control moved to an overly aggressive turn-off or overly slow turn-on (Rg/two-level/slew) causing EMI or switching loss.
Quick check:Log tr/tf, Vds overshoot, ringing cycles, and switching-loss proxy (Vds·Id overlap) before/after; isolate effects by sweeping split Rg_on/Rg_off only.
Fix:Keep −Voff, then tune edge with split Rg and/or two-level turn-off (fast initial clamp + gentle tail) or slew programming; add small series damping (e.g., ferrite/resistor) only if needed.
Pass criteria:Maintain falsing=0; EMI delta ≤ X dB; switching-loss delta ≤ Y% (or ΔTj ≤ Y°C) at the same operating point; ringing cycles ≤ N.
Miller clamp enabled, yet shoot-through spikes remain—placement/reference or timing window?
Likely cause:Clamp is referenced to power source (not Kelvin), clamp path inductance is high, or clamp engages too late (not active during the Miller plateau window).
Quick check:Capture Vgs + clamp node (or clamp-enable) relative to Kelvin source; verify clamp engagement occurs before/through the plateau; compare “Kelvin ref” vs “power ref” measurement.
Fix:Move clamp to the gate-pin region, return to Kelvin source, minimize clamp loop inductance, and align clamp enable threshold/timing to cover the plateau and dv/dt event.
Pass criteria:Worst-case dv/dt event: Vgs bump ≤ X V; shoot-through spikes count=0 over N stress cycles; any residual spike energy ≤ Y (placeholder).
Short-circuit shuts down, but Vds overshoot kills devices—soft turn-off current too low or clamp path too inductive?
Likely cause:Soft turn-off is too weak/slow under high current, or the clamp/snubber path is too inductive, producing a destructive Vds peak during forced turn-off.
Quick check:In SC capture: log t_safe-off, Vds_peak, and gate discharge slope; repeat with one knob at a time (soft turn-off current setting, clamp path length/return).
Fix:Increase soft turn-off current (or equivalent setting) within safe gate limits, minimize clamp loop inductance (short + wide + local return), and ensure gate loop/Kelvin reference stays stable during SC.
Pass criteria:At defined SC condition: t_safe-off ≤ X µs; Vds_peak ≤ Y V; survive N SC pulses at temperature Y with no parameter drift beyond X%.
DESAT trips randomly at high temp—blanking/filter or diode leakage path?
Likely cause:DESAT leakage (diode/PCB contamination) or dv/dt injection crosses the threshold; blanking/filter is mis-tuned (too short → noise trips, too long → deadline missed).
Quick check:Record DESAT pin waveform vs temperature; measure “DESAT bias/leakage” in OFF state; sweep blanking time and filter strength while logging false-trip rate.
Fix:Use low-leakage DESAT diode and guard routing/creepage, clean/coat if needed, and retune blanking/filter to suppress noise without violating the SC timing budget.
Pass criteria:At temp=Y: false DESAT trips ≤ N per Y minutes; true SC detect still meets budget t_detect+t_blank+t_safe-off ≤ X µs.
DPT looks fine, but inverter fails in system—probe ground loop hiding true Vgs ringing?
Likely cause:Measurement reference/loop hides gate ringing or reference shift (power-source referenced probing masks Kelvin-source behavior); system wiring adds parasitics not present on the bench.
Quick check:Re-measure Vgs using Kelvin-source reference with a minimized loop (or true differential); compare ring amplitude/frequency and correlate with system failure timestamps.
Fix:Standardize probing (Kelvin reference + short loop) and add dedicated test points at gate/Kelvin; update acceptance gates to the standardized method and repeat DPT + dv/dt checks.
Pass criteria:Using the standardized method: Vgs ringing amplitude ≤ X V and cycles ≤ N; system passes across Y operating points with no fault events.
Only one leg fails EMI—arm-to-arm asymmetry or layout loop mismatch?
Likely cause:Arm-to-arm asymmetry in gate loop inductance, clamp/decoupling placement, or return-path partitioning causes one leg to ring harder and radiate more.
Quick check:Compare per-leg Vds overshoot, ring frequency/decay, and Vgs bump under the same condition; inspect mirrored placement distances (≤ X placeholder) and reference routing.
Fix:Enforce mirrored layout (driver→Rg→gate→Kelvin return), match clamp/decoupling geometry, and use identical Rg footprints/parts; re-run the same DPT capture on both legs.
Pass criteria:Leg-to-leg mismatch in overshoot/ring metrics ≤ X%; EMI delta between legs ≤ Y dB; no falsing events over N cycles.
dv/dt immunity fails only at high bus voltage—Ciso path or gate loop inductance scaling?
Likely cause:Higher bus voltage increases displacement current (I=C·dv/dt) and energy; gate-loop inductance converts the disturbance into a larger Vgs bump near the OFF boundary.
Quick check:Run dv/dt step tests across bus levels and plot Vgs bump vs bus; verify the reference (Kelvin) and track any input upset/fault flags across ± dv/dt directions.
Fix:Reduce effective coupling into sensitive references (shield/partitioning), tighten the gate loop, strengthen clamp effectiveness, and/or reduce slew with a controlled two-level or programmable edge.
Pass criteria:At bus=Y V and dv/dt=X kV/µs, repeats=N: falsing=0; Vgs bump ≤ X V; no logic upset events.
After fault, system latches and won’t recover—latch policy or /FLT handshake missing?
Likely cause:Driver is latched and requires an explicit reset, or /FLT/EN handshake across isolation is incomplete (pulling, timing, or controller state machine).
Quick check:Capture /FLT, EN, PWM (and /RDY if present) around fault; inject a known fault and verify the documented reset sequence is executed with correct timing.
Fix:Implement a deterministic recovery sequence: PWM off → wait X ms → clear latch/reset → verify ready → re-enable; add proper pull network and noise filtering for /FLT.
Pass criteria:Recovery time ≤ X ms; no oscillatory re-fault loops > N times in Y minutes; fault signaling is unambiguous in logs.
UVLO chatter during transients—bias droop or UVLO hysteresis too small?
Likely cause:Isolated bias droops at the driver pins (loop inductance/insufficient reservoir) and UVLO hysteresis is too small, causing toggling during transients.
Quick check:Scope VDD/VSS directly at the driver pins during the transient; count UVLO toggles per event; compare with and without added local reservoir at the pins.
Fix:Increase local decoupling/reservoir at the driver pins, shorten bias supply loop, and widen UVLO hysteresis or adjust thresholds if the device supports it.
Pass criteria:At worst-case transient: UVLO toggles ≤ N per Y minutes; VDD droop margin ≥ X V relative to UVLO_OFF; no unintended output pulses.
Gate waveform clean but junction temp rises—turn-on too slow (loss) or turn-off too fast (ringing/EMI) causing extra loss?
Likely cause:“Clean” waveform hides loss drivers: slow turn-on increases Vds·Id overlap loss, or aggressive turn-off creates ringing/EMI and extra dissipation; deadtime mismatch adds diode conduction.
Quick check:Estimate switching loss from Vds·Id overlap and compare across Rg_on settings; check deadtime/diode conduction interval and ring decay under the same load point.
Fix:Tune Rg_on for lower overlap loss within EMI budget, apply two-level turn-off to reduce ringing without losing clamp control, and retune deadtime to minimize diode conduction.
Pass criteria:At same output power: ΔTj ≤ Y°C (or efficiency improves by X%); EMI delta ≤ X dB; ringing cycles ≤ N; falsing remains 0.
Changing gate resistor vendor changes stability—tolerance/inductance/parasitic packaging effect?
Likely cause:Different resistor package parasitics (ESL/ESR/Cpar) and tolerance shift damping; the footprint/placement adds inductance that changes ring frequency and clamp effectiveness.
Quick check:Measure actual R value and compare ringing frequency/decay with each vendor; swap only the resistor while holding layout/rails/clamp constant to isolate the cause.
Fix:Specify package + tolerance + pulse rating + parasitic constraints, lock the footprint for low ESL, and add a small damping element (bead/RC) only if the acceptance gate is otherwise missed.
Pass criteria:Across vendor lots and temp=Y: ringing cycles ≤ N and overshoot ≤ X; dv/dt immunity falsing remains 0 at dv/dt=X kV/µs.
