UVLO (On/Off Thresholds) for Gate Driver ICs
Core Thesis
Independent UVLO ON/OFF thresholds (VON/VOFF) turn gate-drive power dips into a deterministic “permission boundary”—preventing half-conduction loss and restart chatter. The goal is simple: disable early, recover cleanly, with behavior that is measurable and defensible in reviews and lab tests.
Definition & Scope: UVLO with Independent ON/OFF Thresholds
UVLO (Under-Voltage Lockout) is a driver-side protection function that disables gate-drive output when the driver bias rail falls below a defined threshold, preventing insufficient gate drive from causing half-conduction, uncontrolled switching, or thermal runaway.
Core requirement: Independent turn-on (VON) and turn-off (VOFF) thresholds (or explicit hysteresis)
keep the output stable when VDD/VBS hovers near the boundary.
Without this separation, small rail ripple, load steps, bootstrap droop, or ground bounce can force repeated enable/disable cycles.
Independent VON/VOFF is not a “nice-to-have”: it is the minimum condition for a deterministic output-permit window under real rail dynamics. In gate drivers, the bias rail is rarely ideal DC: switching current pulses, decoupling ESL/ESR, trace resistance, isolated bias noise, and bootstrap refresh events can all create short dips that sit exactly where a single-threshold comparator becomes unstable.
Page boundary (to avoid sibling overlap):
- Covers: how VON/VOFF are defined, how UVLO maps to output behavior (clamp/Hi-Z/pull-down), multi-rail interactions (VDD/VBS/secondary bias), and recovery rules that prevent chatter and restart storms.
- Does not cover: short-circuit detection mechanisms (DESAT), active Miller clamp behavior, or bootstrap sizing math (only referenced by link).
- VON/VOFF + hysteresis window
- Output disable mode + recovery behavior
- Multi-rail UVLO mapping (VDD/VBS/isolated)
- Not here: DESAT / SC detection
- Not here: Active Miller clamp
- Not here: Bootstrap sizing math
Failure Model: What Goes Wrong Without Proper UVLO
UVLO failures are rarely “mysterious.” They follow repeatable patterns because the trigger is physical: rail droop and rail noise at the driver pins (not the bench supply setting). When UVLO thresholds, hysteresis, or recovery rules are wrong, the driver can spend time in a region where the switch is neither cleanly OFF nor fully ON.
Practical lens: Always evaluate UVLO at the driver-local rail (pin-level VDD/VBS),
not only at the bulk capacitor or power entry. Local impedance (trace + via + decoupling ESL/ESR) defines
the instantaneous headroom seen by the UVLO comparator.
Failure A — Half-Conduction Loss Loop
- Symptom: Rising temperature and efficiency drop during brownout or load steps; waveform looks “almost OK” but devices heat quickly.
- Mechanism: VDD/VBS droop → reduced gate drive strength/amplitude → gate sits in a loss-heavy region → conduction loss increases → junction temperature rises → rail droop worsens.
- Quick check: Probe VDD/VBS at driver pins + gate amplitude/plateau during the event; correlate with temperature rise and switching node behavior.
- Consequence: Thermal runaway risk, accelerated aging, and “works in lab / fails in system” behavior under worst-case wiring and transients.
Failure B — Threshold Chatter Near the Boundary
- Symptom: Intermittent enable/disable bursts, EMI spikes, audible noise, or control instability when rails hover near the UVLO boundary.
- Mechanism: Small ripple crosses a single threshold repeatedly → OUT_EN toggles → repeated gate events accumulate → system-level noise and state-machine confusion.
- Quick check: Slow-ramp the bias rail through the boundary and count toggles; verify hysteresis width and debounce behavior.
- Consequence: “Random” resets, unexplained EMI failures, and reduced margin even when average rail voltage appears acceptable.
Failure C — Restart Storm (Enable–Drop–Enable Oscillation)
- Symptom: Periodic start/stop cycles under marginal bias supply; recovery triggers immediately followed by another trip.
- Mechanism: UVLO disables output → load reduces → rail recovers → UVLO re-enables too early → load returns → rail collapses again.
- Quick check: Observe rail and OUT_EN over multiple cycles; check recovery threshold/hold-off and supply foldback behavior.
- Consequence: Persistent instability, extra stress from repeated switching events, and difficult-to-reproduce field failures.
Failure D — False Trip / False Recovery
- Symptom: UVLO trips “without rail drop” or recovers “too early,” often during high dv/dt switching transitions.
- Mechanism: Measurement reference error, ground bounce, or local transient shifts the comparator input across VON/VOFF.
- Quick check: Move the probe reference to driver ground, measure at-pin rail with short ground spring, and compare to bulk-node readings.
- Consequence: Misdiagnosis (blaming thresholds) and wasted iterations unless measurement and local impedance are normalized first.
These patterns make UVLO design testable: if a page defines the failure chains clearly, later chapters can specify thresholds and pass criteria that guarantee the system never operates in the “danger window.”
UVLO Fundamentals: Thresholds, Hysteresis, and State Machine
A robust UVLO is not a single trip point. It is a behavior contract built from two thresholds, noise immunity, and state transitions that define exactly when gate-drive output is permitted.
Key terms:
VON = turn-on threshold (output permission can be asserted),
VOFF = turn-off threshold (output permission must be removed),
hysteresis = VON − VOFF (the minimum rail window that prevents chatter near the boundary).
1) Threshold window (VON/VOFF)
The system must avoid operating in the region where the rail is too low for clean, loss-minimized switching. Independent VON/VOFF ensures that small ripple around the boundary does not toggle the output permission.
2) Debounce / filter
Real rails contain transient dips and spikes. A debounce/filter stage defines the minimum time or pattern required for a threshold crossing to be treated as valid. This prevents spurious trips and false recovery.
3) Propagation to output (safety window)
The crossing of VOFF is not identical to the moment the gate becomes safe. Comparator delay, logic delay, and output discharge dynamics define a finite window. This window must be considered part of the safety boundary.
4) State machine (predictable behavior)
A state machine removes ambiguity: OFF blocks output; ARM waits for stable rail; ON permits output; FAULT represents a qualified UVLO trip; RECOVER enforces controlled re-entry to prevent restart storms.
Recommended state intent (UVLO-only view):
- OFF: output permission is removed; gate output is in a defined safe mode.
- ARM: rail is near VON; debounce/filter qualifies stability before enabling.
- ON: output permission is asserted while the rail remains above VOFF.
- FAULT: a qualified rail undervoltage event is recorded; output permission is removed.
- RECOVER: hold-off or stability qualification prevents rapid re-enable cycles.
Mapping UVLO to Gate Output: What Exactly Is Disabled
UVLO does not only decide “enable or disable.” It also defines how the gate is driven to a safe condition. Different gate drivers implement different disable modes; the mode is a selection-critical behavior because it changes false turn-on risk, recovery behavior, and EMI signature.
Selection dimension: When UVLO trips, identify the output electrical state:
Pull-Down (active discharge), Clamp (hold gate to a safe level), or Hi-Z (high impedance).
Validate behavior at the gate node, not only by reading a datasheet label.
Disable Mode A — Pull-Down
The output stage actively discharges the gate toward a defined safe potential. This is deterministic for shutdown but can increase edge activity during fault transitions.
- Primary risk: higher dV/dt activity during disable; verify EMI impact during repeated events.
- Best fit: systems prioritizing hard off behavior under droop and brownout.
Disable Mode B — Clamp
The gate is held to a defined safe level (or range) to reduce sensitivity to transient coupling at the gate node. The clamp level and discharge strength must match the switch and topology.
- Primary risk: improper clamp level may slow recovery or increase loss during transitions.
- Best fit: high dv/dt environments where deterministic gate potential is required.
Disable Mode C — Hi-Z
The output stage becomes high impedance. The final gate state depends on external resistors and parasitics. This mode can be acceptable only when the external network guarantees safe discharge under all conditions.
- Primary risk: floating gate risk and inconsistent recovery between channels or boards.
- Best fit: architectures where an external network enforces the safe gate state.
Multi-channel implications (UVLO view only):
- Per-channel UVLO: HS and LS can trip independently; recovery may become asymmetric unless coordinated by EN logic.
- Global shutdown on any UVLO: any undervoltage event forces both channels off; behavior is safer but may reduce uptime.
Fault and ready pins (priority and semantics):
- Priority alignment: UVLO trip must dominate output permission; EN and PWM inputs cannot override an active UVLO condition.
- /FLT and /RDY: confirm whether they are latched, open-drain, or pulse-based; verify timing relative to OUT_EN.
- EN gating: verify whether EN is ignored during UVLO, or whether EN must be re-asserted after recovery.
Choosing ON/OFF Thresholds: How to Set VON/VOFF for Different Switches
Setting UVLO thresholds is an engineering decision, not a guess. The goal is to keep operation out of the insufficient gate-drive region where the switch is neither cleanly OFF nor fully ON. Thresholds must be set from the required gate-drive capability (gate voltage and drive strength) and the worst-case bias rail seen at the driver pins.
Rule of thumb:
VON should be high enough that the driver can deliver the required gate-drive capability with margin,
while VOFF should be high enough to remove output permission before the rail enters the loss-heavy danger window.
Hysteresis (VON − VOFF) must cover expected ripple and load-step droop to prevent chatter.
Step 1 — Define the worst-case bias rail at the driver pins
- Use VDD(min) / VBS(min) at the driver pins (include trace/via resistance and decoupling ESL/ESR effects).
- Include brownout depth, load-step droop, and any isolated bias ripple relevant to the topology.
Step 2 — Choose VON from a “safe enable” requirement
- VON must ensure the driver can deliver the required gate-drive capability (voltage + strength) without entering a marginal region.
- Use a margin expression: Margin = VDD(min) − VON(min) ≥ X (X is a design target set by ripple/droop/measurement uncertainty).
Step 3 — Choose VOFF from an “early exit” requirement
- VOFF must remove output permission early enough that the gate does not linger in a loss-heavy region during rail collapse.
- Include the delay from VOFF crossing to a truly safe gate state (comparator + logic + discharge dynamics).
Step 4 — Map the thresholds to switch families (without device physics)
- IGBT: prioritize avoiding partial drive under droop; set VON conservatively and VOFF early to prevent heat escalation.
- SiC MOSFET: prioritize stability against fast transients; ensure hysteresis/debounce prevent boundary chatter.
- GaN HEMT: prioritize a stable, narrow operating window; avoid threshold-adjacent enable/disable behavior.
- LV MOSFET: prioritize load-step resilience (VR/multipoint systems); hysteresis must cover frequent rail excursions.
Thresholds should be treated as a budget: rail headroom, threshold tolerance (min/max), and time-to-safe at the gate must all fit within a defined operating window. This produces stable behavior across process, voltage, temperature, and layout variation.
Multi-Rail Cases: VDD, VBS, VCC2, and Brownout Interactions
Real gate-driver systems often have multiple rails: logic supply, driver bias, bootstrap supply, and isolated secondary bias. UVLO behavior depends on which rails are monitored and how their comparators are combined (global OR, per-channel OR, or dependency-driven gating).
Practical rule: Identify the UVLO decision inputs at the driver pins (VDD/VCC, VBS, VCC2), then define the
combination logic (OR and channel scope) that produces OUT_EN. Verify brownout behavior using rail injection at each input.
Rail map (typical meanings)
- VDD (logic): input interface and internal logic domain.
- VCC (driver bias): output stage energy for charging/discharging the gate.
- VBS (bootstrap): high-side bias derived from switching refresh events.
- VCC2 (isolated): secondary bias for isolated drivers or high-side domains.
Combination logic patterns (UVLO view)
- Global OR: any rail trip disables all outputs (consistent and safe, lower uptime).
- Per-channel OR: HS and LS can trip independently (flexible, requires coordination to avoid asymmetry).
- Dependency: bootstrap/secondary rails can collapse during certain operating modes (risk of restart storms without recovery hold-off).
Brownout interactions (what to lock down)
- Which event removes permission first (HS vs LS), and whether the other channel is also disabled.
- Recovery rules that prevent enable–drop–enable oscillation under foldback supplies.
- Fault/ready pins timing relative to OUT_EN during rail-specific trips.
Multi-rail UVLO should be treated as a system-level specification: inputs, logic, channel scope, and recovery are all part of the expected behavior under brownout and transient conditions.
Startup, Shutdown, and Recovery: Avoiding Chatter and Restart Storm
A stable UVLO design must prevent two failure patterns: chatter (rapid enable/disable toggling near the threshold) and restart storm (repeating enable–brownout–disable cycles caused by foldback supplies or repeated droop). Recovery must be treated as a qualified sequence, not a simple threshold crossing.
Recovery contract:
VDD > VON is a candidate condition only. Enable should occur after qualification
(tQUAL) and optional start delay (tSTART). After a trip (VDD < VOFF),
enforce a hold-off (tHOLD) and a deterministic handshake with EN and /RDY.
1) Enable qualification (no boundary toggling)
- tQUAL (debounce/qualify): require VDD above VON for a minimum time before enabling.
- tSTART (start delay): optional delay or staged enable to avoid immediate brownout re-entry.
- Pin-level rule: qualify the rail at the driver pins (not only at the upstream regulator).
2) Shutdown contract (deterministic exit)
- Trip is qualified when VDD is below VOFF for the defined debounce condition.
- OUT_EN must deassert deterministically, followed by a controlled recovery path.
- Record the event via /FLT semantics (pulse vs latch) and align it to OUT_EN timing.
3) Latch vs auto-retry (policy selection)
- Latch: prevents repeated storms; recovery requires explicit clear or EN re-handshake.
- Auto-retry: improves uptime but needs hold-off/qualification and may require backoff at the controller level.
- Recovery level: consider a stricter recover condition (VREC) instead of enabling immediately at VON.
4) Controller handshake (recommended priority)
- Priority alignment: UVLO active dominates output permission; EN/PWM cannot override an active UVLO condition.
- /RDY indicates “qualified to drive”; EN is the controller-level permission; /FLT indicates a trip event.
- Use a truth-table style contract to prevent ambiguous restart behavior.
Recommended handshake truth table (template):
| Condition | Inputs | OUT_EN | Notes |
|---|---|---|---|
| UVLO active | UVLO=1 (VDD<VOFF) | 0 | Force disable. /FLT asserted per device semantics. Ignore EN/PWM overrides. |
| Latched trip | UVLO=0, LATCH=1 | 0 | Remain disabled until clear condition (external clear or EN re-handshake). |
| Qualified enable | UVLO=0, LATCH=0, EN=1, /RDY=1 | 1 | Enable after tQUAL (+ optional tSTART). Avoid enabling directly at boundary. |
| Hold-off | UVLO cleared, tHOLD active | 0 | Prevents restart storm under foldback supplies or repeated droop events. |
System-Level Consequences: EMI, Thermal, and Control-Loop Stability
UVLO impacts more than safety. Poor threshold placement or unstable recovery can change the switching spectrum, increase dissipation, and destabilize controller behavior. System-level validation should treat UVLO events as performance and stability variables.
Three observable consequences:
EMI spread (frequency-domain instability from repeated enable/disable),
thermal rise (loss escalation under insufficient drive),
and control anomalies (duty jumps and recovery overshoot when the controller is not synchronized to UVLO).
Chain A — Chatter → EMI / audible noise / false triggers
- Cause: rail ripple near the boundary without sufficient hysteresis/qualification.
- Signature: repeated enable/disable cycles broaden the spectrum and create inconsistent EMI outcomes.
- Knobs: increase hysteresis, add tQUAL/tHOLD, enforce a deterministic retry policy.
- Pass criteria: EMI margin ≥ X dB across Y repeated runs (placeholders).
Chain B — Insufficient drive region → Heat rise / efficiency drop
- Cause: VON too low (enables too early) or VOFF too low (disables too late).
- Signature: higher dissipation, abnormal plateaus in switching waveforms, and temperature escalation.
- Knobs: raise VON/VOFF, increase margin budget, reduce rail droop at the driver pins.
- Pass criteria: ΔT ≤ X °C and efficiency ≥ Y % under worst-case droop (placeholders).
Chain C — UVLO interruption → Control anomalies / re-trip storm
- Cause: UVLO removes gate permission while the controller state is not synchronized (EN/ready mismatch).
- Signature: recovery overshoot/undershoot, wind-up-like behavior, and secondary UVLO trips.
- Knobs: enforce EN gating with /RDY, apply recovery soft-start, freeze or limit recovery commands (concept only).
- Pass criteria: no secondary trips; overshoot ≤ X %; recovery time ≤ Y ms (placeholders).
A UVLO event should be validated with both time-domain waveforms and frequency-domain checks. The acceptance target is deterministic behavior under repeated rail injection, temperature, and load-step stress.
Verification & Pass Criteria: How to Test UVLO Properly
UVLO validation must use a single measurement contract to avoid lab-to-lab and reviewer-to-reviewer disputes. The key is to measure rails at the driver pins, define stimulus profiles, and apply repeatable pass criteria for threshold distribution, chatter, disable latency, and partial-drive dwell time.
Measurement contract:
use pin-level VDD/VBS, define ramp and brownout profiles, log OUT_EN state, and correlate /FLT with gate behavior.
Repeat across load and temperature points.
Test methods (stimulus profiles)
- Slow ramp sweep: programmable supply with controlled slope to extract VON/VOFF distribution.
- Brownout injection: step or pulse droop events to stress recovery hold-off and restart behavior.
- Repeated cycling: multiple trip–recover loops to expose chatter and storm patterns.
- Temperature sweep: cold/room/hot points to capture threshold drift and recovery stability.
Observability (signals to capture)
- Rails: VDD(pin), VBS(pin) (and VCC2(pin) if used).
- Gate behavior: Vg, OUT_EN (or gate output state).
- Power stage: VDS/VCE to detect abnormal plateaus and partial-drive signatures.
- Handshake: EN, PWM input, /RDY (if available), /FLT.
Repeatability rules (avoid disputes)
- Always document probe location and reference (pin-level requirement).
- Use the same ramp rate and brownout profile definitions across benches.
- Define chatter counting window and counting object (OUT_EN toggles).
Pass criteria template (placeholders X/Y/N):
| Metric | How to measure (contract) | Pass criteria (template) | Notes |
|---|---|---|---|
| Trigger consistency VON/VOFF distribution |
Slow ramp sweep; extract crossing points at pin-level rails; collect repeated samples across conditions. | Distribution width ≤ X (or drift ≤ Y) across N runs. | Report mean / min / max and test conditions (ramp rate, load, temperature). |
| Chatter count | Define a counting window around the rail excursion; count OUT_EN (or output state) toggles within the window. | Chatter toggles ≤ N per injection event. | Use a consistent window definition and a consistent toggle definition. |
| Disable latency | Time from VOFF crossing (pin-level rail) to OUT_EN deassert (or gate reaching the safe state boundary). | Disable latency ≤ X ns/us. | Capture /FLT timing relative to OUT_EN if required by system contract. |
| Partial-drive dwell | Total time Vg remains within a defined boundary band near the effective gate threshold region (band limits as placeholders). | Dwell time ≤ Y µs per event. | Use VDS/VCE plateaus and temperature rise as supporting evidence when needed. |
Reporting package: include rail profiles, waveforms (VDD/VBS/Vg/VDS), OUT_EN and /FLT timing,
and a summary table of VON/VOFF statistics and chatter counts for repeated runs.
Design Checklist: From Schematic to Bring-Up to Production
UVLO robustness depends on consistent implementation across the product lifecycle. The checklist below turns UVLO into concrete deliverables: rail mapping, handshake definition, tolerance budgeting, and repeatable validation artifacts.
Lifecycle rule: define the UVLO behavior contract in schematic, prove it in bring-up with rail injection,
then lock it down for production with measurable items and traceable records.
Schematic checklist (design intent)
- Rail map: list monitored rails (VDD/VBS/VCC2) and confirm pin-level measurement points.
- Permission path: define EN default state and /RDY gating behavior; document priority vs PWM input.
- Fault semantics: specify /FLT behavior (pulse/latch), pull-ups, and system-level interpretation.
- Debounce/timing: document tQUAL/tSTART/tHOLD placeholders and expected disable latency budget.
- Tolerance budget: include threshold min/max and temperature drift in the VON/VOFF margin plan.
Bring-up checklist (prove behavior)
- Ramp sweep: extract VON/VOFF distribution with slow ramps; record min/max and drift.
- Brownout injection: step/pulse droop per rail; verify OUT_EN, /FLT, and handshake alignment.
- Repeat cycles: run N trip–recover loops; confirm chatter ≤ N and no storm patterns.
- Thermal points: validate cold/room/hot; confirm thresholds and recovery stability.
- Worst load: repeat under worst droop and load step conditions at the driver pins.
Production checklist (measurable + traceable)
- Measurable items: threshold sampling (VON/VOFF), /FLT behavior, and EN gating sanity checks.
- Injection script: simplified brownout test profile for sampling audits or debug stations.
- Traceability: store batch-level threshold statistics and pass/fail summaries for review and audits.
- Documentation package: include the measurement contract, waveform examples, and criteria X/Y/N placeholders filled later.
H2-11 · Applications: Where Independent ON/OFF UVLO Matters Most
How to use this section (UVLO-only scope)
- Trigger: which rail dip puts the driver near the UVLO boundary (VDD/VCC/VBS/VH_x/secondary bias).
- Risk signature: what failure looks like (brownout, chatter, half-conduction, restart storm).
- Minimum measurements: what must be captured to end lab/review disputes (rails + OUT_EN/+fault pins + gate behavior).
- UVLO knobs: which UVLO-related datasheet fields are non-negotiable (independent VON/VOFF, hysteresis, hold-off, per-rail mapping, output safe state).
brownout
chatter
half-conduction
restart storm
Integration rule: treat UVLO as a permission boundary. If any rail can sit near threshold during real transients,
require explicit VON/VOFF (or numeric hysteresis) and a defined output safe state to keep behavior deterministic.
3-Phase Inverter / Servo (motor drive stacks)
- Trigger: bus ripple, regenerative events, or isolated/bootstrapped bias dip pushes VBS/VH_x near UVLO.
- Risk signature: phase permission becomes inconsistent → waveform fragments, EMI spreads, thermal hotspots appear.
- Minimum measurements: VBS/VH_x at the driver pins, VDD/VCC (logic), OUT_EN (or output state), /FLT or /RDY, and one phase Vg.
- UVLO knobs: per-rail mapping (which rail disables which output), VON/VOFF separation to prevent chatter, and a defined safe state (pull-down/clamp/Hi-Z).
- Pass criteria (placeholders): chatter count ≤ N/event; disable latency ≤ X; repeated events keep trip points within Y.
Example driver ICs (part numbers, verify latest datasheet):
- TI UCC21750-Q1 — UVLO on both input and output supplies (VCC/VDD), output held LOW until both rails clear UVLO.
- ST STGAP2SiCD — UVLO on the high-side supply (VH_x) with hysteresis; output buffer enters a defined safe state during UVLO.
- ADI ADuM4121 — isolated gate driver with built-in hysteresis; multiple secondary UVLO threshold options (model grades).
- Skyworks/Silabs Si827x — isolated gate drivers holding outputs low until supplies exceed UVLO for a start interval (tSTART).
LLC / PFC (startup & brownout sensitive stages)
- Trigger: startup sequencing makes VDD/VBS wobble; brownout causes fast rail decay.
- Risk signature: repeated enable/disable bursts → restart storm, wideband EMI, and inconsistent bring-up.
- Minimum measurements: VDD-VSS and HB-HS (bootstrap rail), OUT states, EN/SD, /FLT (if available), and gate output during the first start window.
- UVLO knobs: explicit UVLO_ON/UVLO_OFF thresholds for both low-side rail and bootstrap rail, plus a clean recovery policy (delay/hold-off).
- Pass criteria (placeholders): start window has ≤ N UVLO trips; recovery happens only after rail exceeds VON for X time; no re-trigger within Y.
Example driver ICs (part numbers, verify latest datasheet):
- TI UCC27714 — UVLO on VDD-VSS and HB-HS with UVLO_ON/UVLO_OFF thresholds; UVLO timing impacts enable/disable behavior.
- Infineon IRS21867S — UVLO thresholds on VCC and VBS (UV+ / UV− behavior) to gate outputs when supplies are insufficient.
- onsemi NCP51820 — half-bridge driver with explicit UVLO ON/OFF thresholds (example: VDDUV+ / VDDUV−) for bias-rail protection.
POL / VR Multiphase (bias droop + phase consistency)
- Trigger: fast load step causes driver bias droop; a single phase can hover near UVLO if rail impedance or decoupling is uneven.
- Risk signature: one phase chatters → effective phase count changes → ripple/noise rises and thermal distribution collapses.
- Minimum measurements: driver VCC at pin, per-phase enable/drive presence, and fault/EN handshake into the controller.
- UVLO knobs: wide hysteresis between VON/VOFF (noise immunity), deterministic output low during UVLO, and controller-visible fault signaling.
- Pass criteria (placeholders): phase permission remains consistent across repeated load steps; droop events do not create > N toggles.
Example driver ICs (part numbers, verify latest datasheet):
- onsemi NCP5901 — VR-class synchronous buck MOSFET driver; UVLO ensures outputs remain low when supply is low; EN can reflect fault/UVLO conditions.
- Renesas ISL6625A — buck MOSFET driver with power-on reset rising/falling thresholds that gate operation (UVLO-like permission behavior).
- Infineon EiceDRIVER™ 2EDN family — gate drivers with published UVLO options (family-level UVLO variants).
Diagram intent: show that independent VON/VOFF is not only “safety”; it is a system behavior stabilizer under real rail transients.
H2-12 · IC Selection Notes: What to Look for in a Gate Driver UVLO Spec
UVLO Spec Checklist (turn datasheet text into Pass/Fail)
MUST (fail = reject)
- Independent VON/VOFF or a numeric hysteresis value (prefer min/typ/max + temperature range).
- Monitored rails mapping: which rails (VDD/VCC/HB-HS/VBS/VH_x/secondary) can trigger UVLO, and whether it is per-channel or global.
- Output safe state on UVLO: pull-down vs clamp vs Hi-Z must be explicitly defined for integration and safety review.
SHOULD (strongly preferred)
- Propagation delay & repeatability: enable/disable behavior should have a bounded worst-case, especially during fast droops.
- Fault/ready/enable priority: /FLT, /RDY, EN/SD priority and default states must be clear to prevent restart storms.
NICE (integration speed-ups)
- Built-in start qualification (tSTART/tQUAL) and hold-off guidance for clean recovery.
- Multiple UVLO options (grades/variants) to match different gate bias rails without external glue logic.
Reading tip: treat “UVLO present” as insufficient unless the datasheet states ON/OFF thresholds (or hysteresis),
monitored rail(s), and output safe state. Otherwise, integration ends up defining behavior by assumption.
Shortlist Examples (UVLO-centric, with part numbers)
Reinforced / isolated drivers (inverter stacks)
- TI UCC21750-Q1 — check UVLO on both sides (VCC/VDD) + defined output LOW during UVLO.
- ST STGAP2SiCD — check VH_x UVLO VHon/VHoff and safe state definition.
- ADI ADuM4121 — check selectable secondary UVLO options (grade A/B/C) + built-in hysteresis.
- Skyworks/Silabs Si827x — check “outputs held low until UVLO clears for tSTART”.
HV half-bridge (bootstrap) drivers (LLC/PFC)
- TI UCC27714 — check UVLO_ON/UVLO_OFF for both VDD-VSS and HB-HS rails.
- Infineon IRS21867S — check VCC/VBS UV thresholds (UV+ / UV−) and which outputs shut down.
- onsemi NCP51820 — check explicit bias UVLO ON/OFF thresholds and independent UVLO behavior.
Low-voltage / VR-class drivers (POL/multiphase)
- onsemi NCP5901 — check UVLO behavior and controller-visible EN/fault signaling.
- Renesas ISL6625A — check VCC rising/falling POR thresholds that gate operation (UVLO-like permission boundary).
- Infineon EiceDRIVER™ 2EDN family — check which UVLO option (e.g., 4.2 V / 8 V) matches the rail.
- TI UCC27524A — check VDD UVLO and “output remains low until UVLO clears” behavior for noisy rails.
Common rejection flags (UVLO integration risk)
- Only “UVLO present” is stated, but no ON/OFF thresholds or hysteresis value.
- Monitored rail list is unclear (VDD vs VBS vs secondary bias), so shutdown behavior is ambiguous.
- Output state during UVLO is not defined (pull-down/clamp/Hi-Z), so safety case becomes assumption-driven.
Diagram intent: make UVLO selection deterministic—fields are evidence, gates are rules, shortlist is the outcome.
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H2-13 · FAQs (UVLO): Troubleshooting & Review Disputes
Scope: UVLO thresholds and behavior only (VON/VOFF, hysteresis, debounce/hold-off, multi-rail mapping, output disable mode, EN-/RDY-/FLT priority, and measurement contract).
Answer format: each question uses a fixed 4-line structure with quantified placeholders (X/Y/N) for acceptance criteria.
Answer format: each question uses a fixed 4-line structure with quantified placeholders (X/Y/N) for acceptance criteria.
VDD looks above UVLO, but output is still disabled—first suspect which rail or logic?rail/logic
Likely cause A different monitored rail (VBS/VCC2/secondary) is below VON, pin-level droop is hidden, or EN-/RDY-/FLT priority keeps OUT_EN gated.
Quick check Measure VDD(pin), VBS(pin), EN, /RDY, /FLT, and OUT_EN simultaneously; force all monitored rails ≥ (VON + X mV) for Y ms.
Fix Correct rail mapping and measurement reference, improve local decoupling/trace impedance at pins, and align controller gating to the datasheet priority table.
Pass criteria All monitored rails stay ≥ (VON(max) + X mV) for Y ms and OUT_EN asserts within Z µs with 0 unexpected disables over N enable cycles.
Crossing VON enables, but the driver chatters under load—hysteresis too small or brownout impedance?chatter
Likely cause Hysteresis (VON−VOFF) is too small for rail noise/droop, or source impedance causes repeated VOFF crossings during load steps.
Quick check Log OUT_EN toggles during a load step and overlay VDD(pin) vs VON/VOFF; compare droop amplitude to hysteresis − X mV margin.
Fix Increase pin-level headroom (decoupling, lower impedance), add/extend hold-off or qualification, or select a driver with larger/explicit hysteresis.
Pass criteria Chatter toggles ≤ N per event and VDD(pin) minimum stays above VOFF(max) + X mV during the worst load step for Y repetitions.
Only the high-side trips UVLO during switching—VBS droop or measurement reference mistake?high-side
Likely cause Bootstrap rail VBS (HB−HS) droops below its UVLO threshold, or the measurement reference is wrong due to switching node motion.
Quick check Measure VBS(pin) as (HB−HS) with proper differential probing; validate VBS minimum during max on-time and during switching bursts.
Fix Increase/relocate Cboot, reduce leakage paths, improve diode path/charging interval, and ensure HS UVLO thresholds match the real VBS headroom.
Pass criteria VBS(pin) minimum ≥ VON_HS(max) + X mV across Y worst-case switching cycles with 0 HS UVLO events and OUT_EN stable.
UVLO triggers only at high temperature—threshold drift or bias headroom collapse?temperature
Likely cause UVLO threshold shifts with temperature, bias regulator derates, or leakage increases causing pin-level rail minimum to shrink.
Quick check Run a temperature sweep and extract VON/VOFF distribution at each point; record VDD(pin) and VBS(pin) minimum during worst load.
Fix Increase headroom (supply setpoint/decoupling/impedance), choose tighter UVLO specs, or adjust system gating to require a higher recovery threshold.
Pass criteria At Tmax, (VDDmin(pin) − VON(max)) ≥ X mV and UVLO trips ≤ N across Y thermal cycles with consistent trigger points (spread ≤ Z mV).
Driver recovers, then immediately trips again—restart storm from supply foldback?recovery
Likely cause Auto-retry recovery collides with supply current-limit/foldback, so the rail re-dips and re-triggers UVLO repeatedly.
Quick check Correlate rail recovery slope with OUT_EN and /FLT timing; check if each enable causes a repeat droop within X ms.
Fix Add/extend hold-off, use latch-to-EN reset policy, increase bulk capacitance, or retune supply current limit so recovery clears VON with margin.
Pass criteria After a UVLO event, minimum off-time ≥ X ms and retry count ≤ N within Y s; stable operation persists for Z minutes with 0 re-trips.
Gate waveform shows a mid-level plateau during brownout—output mode clamp or pull-down missing?half-conduction
Likely cause During UVLO, the output enters Hi-Z or weak drive and lacks a defined pull-down/clamp path, leaving Vg in a mid-level region.
Quick check Trigger on VOFF crossing and measure Vg dwell time in a defined band [V1, V2]; compare with OUT_EN state and /FLT timing.
Fix Add/resize external gate pull-down, select a driver with explicit UVLO output low/clamp behavior, and ensure the safe state is consistent across rails.
Pass criteria Vg falls below VSAFE within X ns/us and dwell time within [V1, V2] ≤ Y µs per event, with no abnormal VDS/VCE plateau beyond Z µs.
Two channels don’t recover together—per-channel UVLO mismatch or enable sequencing?multi-channel
Likely cause Per-channel UVLO thresholds differ, rail routing/decoupling differs by channel, or EN sequencing/gating is not symmetric.
Quick check Capture both channels’ rail pins and OUT_EN simultaneously; measure channel-to-channel VOFF/VON crossing time and OUT_EN skew.
Fix Symmetrize routing and decoupling, unify EN distribution, and prefer drivers with specified channel matching for UVLO behavior.
Pass criteria Channel OUT_EN skew ≤ X µs and both channels maintain (rail min − VOFF(max)) ≥ Y mV during the same disturbance across N repetitions.
UVLO is OK on the bench, but fails in the system—ground reference / probe location error?measurement
Likely cause Bench probes measure at the supply source, while the real system has ground bounce/common-mode motion and pin-level droop that is missed.
Quick check Repeat with pin-level differential probing and short ground reference; compare VDD(source) vs VDD(pin) delta during the event.
Fix Standardize the measurement contract (pin-level rails), improve return paths/ground impedance, and add local decoupling to reduce ΔV at pins.
Pass criteria |VDD(source) − VDD(pin)| ≤ X mV at peak and UVLO trigger aligns to pin-level VOFF crossing within Y µs across N test setups.
EN toggling doesn’t behave as expected—/RDY or /FLT priority misunderstood?priority
Likely cause UVLO overrides EN, /RDY gates output until qualification completes, or /FLT latch holds the driver disabled until reset conditions are met.
Quick check Record EN, /RDY, /FLT, OUT_EN, and rails; test with rails forced stable ≥ (VON + X mV) to isolate priority logic.
Fix Implement the datasheet truth table (polarity + priority), add required pull-ups/pull-downs, and reset latched faults per defined sequence.
Pass criteria With rails stable, OUT_EN follows EN within X µs and /FLT clears per spec within Y ms; 0 unexpected disables across N EN toggles.
Lowering VON fixed chatter but increased heating—half-conduction margin collapsed?margin
Likely cause Reduced VON allows operation with insufficient effective gate drive, increasing conduction loss during rail droop (half-conduction region expands).
Quick check Compare VDDmin(pin) to the new VON and measure Vg plateau + VDS/VCE during droop; correlate with temperature rise.
Fix Restore a VON margin plan (raise VON or increase rail headroom), keep hysteresis adequate, and prioritize pin-level impedance reduction over lowering thresholds.
Pass criteria (VDDmin(pin) − VON(max)) ≥ X mV and partial-drive dwell ≤ Y µs; temperature rise under brownout test ≤ Z °C over N cycles.
UVLO never triggers but the device overheats in brownout—threshold set too low for effective Vg?too-low
Likely cause UVLO threshold is too low (or monitors the wrong rail), so the driver stays enabled while gate drive becomes ineffective during brownout.
Quick check Inject a controlled droop and log OUT_EN and Vg; verify whether OUT_EN deasserts before Vg enters the ineffective region [V1, V2].
Fix Select a driver with explicit independent VON/VOFF (higher VON), monitor the correct rail, or add external supervisor gating EN above a defined threshold.
Pass criteria OUT_EN deasserts before Vg < V2 by at least X µs, and brownout energy exposure ≤ Y (J/°C proxy) with 0 overheating events across N runs.
Same IC, different boards, different UVLO behavior—decoupling/trace resistance causing local droop?layout
Likely cause Local droop at the driver pins differs by board due to decoupling placement, trace resistance/inductance, or shared return impedance.
Quick check Measure VDD at the regulator and at the driver pin concurrently; compute ΔV(pin−src) during the event and compare to X mV limit.
Fix Move/upgrade decoupling at the pins, widen/shorten rail traces, add stitching vias for returns, and avoid shared high-current return segments.
Pass criteria ΔV(pin−src) ≤ X mV at peak, VDD(pin) stays above VOFF(max) + Y mV, and UVLO/chatter events = 0 across N stress cycles.
