Device classes (sequencers, rail/window monitors, POR/reset & watchdog, sequencing PMICs, PMBus PSMs, power-monitor ADCs, MCU+front-ends), sequencing modes, monitoring & protection, configuration interfaces, key specs, use-case mapping, design hooks, and quick cheats.
Device Classes
Dedicated Power Sequencer
Many EN/PG I/Os with programmable delays/graphs for up/down and reverse ordering (FPGA/SoC/servers).
Voltage / Rail Monitor (Window)
Upper/lower thresholds with hysteresis/deglitch for brown-out/UV protection.
POR / Reset Supervisor & Watchdog
Accurate thresholds, programmable delays and windowed WDT for system reset trees.
PMIC with Sequencing & Tracking
Integrated DC-DC/LDO with coincident/ratiometric tracking for mobile/embedded.
Power System Manager (PMBus)
I²C/PMBus with settable thresholds/slews, fault logs and telemetry (V/I/T).
Power-Monitor ADC / ΣΔ
Multi-channel measurement with alert pins; enables board-level energy tracking.
MCU + Supervisor Front-End
Low-cost MCU logic with ADC/GPIO sequencing for custom or low-volume builds.
Sequencing Modes
Sequential Power-Up
RailA → RailB → … based on EN dependency graph; the default strategy.
Grouped / Simultaneous
Same-group start with inter-group delays to tame inrush and peak current.
Tracking: Coincident / Ratiometric
Inter-rail following (same-phase or ratio) for FPGA core/aux/IO coordination.
Controlled Power-Down
Reverse/priority shutdown to avoid latch-up and back-feed paths.
DDR / LPDDR Ordering
VDD/VDDQ → VPP → VTT (follows VDDQ; turn off VTT before VDDQ).
Peripherals / SerDes Ordering
Reference/PLL → core → IO → peripherals to avoid latch-up and ESD issues.
Monitoring & Protection
UV/OV Window w/ Hysteresis
0.5–1.5% typical accuracy with programmable hysteresis and filtering.
Slew-Rate & Inrush Coordination
Soft-start dV/dt and inter-group delays to meet inrush limits.
Reverse Current / Backfeed Detect
Coordinate with load-switches/eFuses to block reverse paths.
PGOOD & Fault Propagation
Wired-OR/AND trees with ALL_OFF for single-shot safe power-down.
Telemetry & Black-Box
Timestamp/rail/threshold recording for field root-cause analysis.
Thermal / Fan Hooks
Over-temp derating, power-limit and thermal-electrical coordination.
Interfaces & Configuration
PMBus/SMBus/I²C
Parameters like VOUT_COMMAND, ON_OFF_CONFIG, TON/TOFF and alert registers.
GPIO / Analog Threshold Pins
Precision ref + divider sets thresholds; RC de-glitch at inputs.
JTAG / EEPROM Profiles
Factory-written sequencing profiles with version readback in the field.
SYNC / CLK / POWER_OK
Board/chassis-level cascading and timing synchronization.
Key Specs & Selection
Threshold Accuracy
±0.5–1% (precision) / ±1–2% (general); ties directly to brown-out margins.
Timing Resolution / Jitter
µs–ms with consistent inter-group/inter-rail delays.
Channel Count & Scalability
Local 4–20 rails and daisy-chain to 100+.
PG/EN Levels & Polarity
Open-drain/push-pull, polarity options and wired-OR expansion.
Power / Standby
µA–mA consumption; log retention in battery domain if needed.
Temperature & Automotive
-40–125 °C; AEC-Q100 grades and lifetime planning.
Use-Case Mapping
FPGA / SoC Multi-Rail
Vcore→Vaux→Vio with coincident/ratio tracking and PG-linked resets.
Data-Center Cards
12 V → multi-phase POL → SerDes/memory groups; PMBus monitoring & logs.
Telecom / Base-Stations
Cascaded sequencers across boards, power-fail protection and fan redundancy.
Industrial & Measurement
Precision rail monitors + POR + WDT with black-box events.
Automotive Domain Controllers
Safe up/down with ASIL diagnostics; coordinate eFuse/hot-swap/battery disconnect.
Design Hooks & Pitfalls
One Sequencing Master
Let one module (sequencer/PMIC) lead; others follow with PG/EN—avoid circular deps.
PGOOD De-glitch
RC/digital filtering so short overshoots don’t cascade faults.
Threshold Setting
UV ≈ 90–95% nominal; OV ≈ 105–110% (per load tolerance) with hysteresis.
Soft-Start & Inrush
Iinrush≈Cload·dV/dt; stagger groups and consider front-end limiting.
Power-Down Order
Turn off IO/peripheral rails first, then cores/memory; DDR VTT before VDDQ.
Reference & Dividers
Use precision refs + low-tempco resistors; Kelvin sense to rails.
Chassis-Level Sync
Shared ENABLE bus + PWR_OK; add link-loss timeout and safe state.
Logging & Observability
Fault→timestamp→shutdown→retain; upload on next boot to reduce MTTR.
EMI & Ground Loops
Route PG/EN with return paths; place pull-ups near receivers to avoid false trips.
Validation Matrix
Cover full temp/load, glitches/dips and reset storms; test fast on/off/brownouts.
Quick Cheats
Scope-Capture Golden Waveforms
Use 4–8-ch scope with PG→EN→Vout trigger stacks; save gold references.
Time Budget
Total power-up ≈ Σ(max group soft-starts) + Σ(inter-group delays); servers often < 90–120 s.
Tolerance Triad
Cross-check load tolerance, regulator accuracy and monitor thresholds.
Redundancy Strategy
Dual feeds on key rails → fail triggers controlled degrade/read-only modes.
