Device classes (SRAM/Flash/Antifuse/SoC/CPLD/Small PLD/eFPGA), logic & on-chip resources, IO & multi-Gbps SerDes, clocking & sync, configuration/security/reliability, power & packaging, tools & ecosystem, application patterns, key specs, design hooks, and quick pairings.
Device Classes
SRAM-based FPGA
LUT/FF + BRAM/DSP; needs external config; high density & partial reconfig.
Flash / Non-Volatile FPGA
Instant-on, low power, better SEU immunity for industrial/automotive.
Antifuse FPGA
One-time programmable, strong radiation tolerance for space/defense.
SoC FPGA (FPGA + CPU)
ARM/RISC-V + FPGA; runs Linux/RTOS for vision, comms and control.
CPLD
Macrocell logic, predictable timing and fast boot for glue/reset/timing.
Small PLD / Green FPGA
Ultra-low power and small footprint for sequencing/bridges/GPIO.
Embedded eFPGA IP
Hardened into ASIC/SoC for late protocol adaptation and updates.
Logic & Resources
LUT/FF Fabric
LUT depth/width, adaptive LUTs and configurable multiplier options.
DSP MAC / ALU Blocks
Fixed/float with pipelining for FIR/FFT/matrix compute.
On-Chip Memory
BRAM/UltraRAM eSRAM; true/ps-dual port, ECC and bandwidth banking.
Hard IP
PCIe/DDR/Ethernet/MIPI/crypto hard blocks to reduce timing risk.
AI/ML Engines
Programmable arrays and custom datapaths for low-latency inference.
IO & High-Speed SerDes
General I/O
Configurable rate/ref levels with on-die terminations.
Multi-Gbps SerDes (1–58G+)
PCIe/JESD/Ethernet/CPRI with CTLE/DFE/EQ and jitter templates.
DDR / LPDDR Interfaces
PHY + calibration, write/read eye training; strict SI/PI.
Video/Camera (MIPI/HDMI/DP)
Hard/soft bridges with safe pixel-domain crossing.
Clocking & Sync
Global/Regional Clocks
Low-skew distribution and clean isolation across domains.
PLL/MMCM/Clock Mgmt
Cleanup, mul/div and phase alignment blocks.
PTP/1588 Stamping
Deterministic networking stamps for industrial/telecom.
Reset & Timing Strategy
Sync resets, CDC/FIFOs and complete XDC/SDC constraints.
Configuration · Security · Reliability
Boot & Configuration
SPI/QSPI/JTAG/SD with multi-image/golden fallback.
Bitstream Security
AES/GCM, key wrapping and anti-readback provisions.
SEU/SET Mitigation
Scrubbing, TMR and ECC for robustness.
Field Upgrade / Partial Reconfig
Live updates with partition isolation and bitstream management.
Power & Packaging
Power Domains
Clock/power gating, low-swing IO and low-Vcore tactics.
Power Rails & Sequencing
Vcore/Vaux/Vio order, slopes, decoupling arrays and transients.
Packaging & Thermals
BGA/LGA escape, SI/PI + thermal co-design and warpage control.
Tools & Ecosystem
Synthesis & P&R
Timing closure with physical constraints and floorplanning.
HLS/DSL & IP Reuse
C/C++/OpenCL flows and platform IP reuse.
Simulation & Verification
RTL/UVM, gate-level timing and hardware-in-the-loop.
ILA/SignalTap & JTAG Debug
On-chip logic analysis with triggers and remote debug.
Manufacturing & Test
Boundary scan (1149.1/1149.6), BIST and PRBS tooling.
Application-Focused
Real-Time Networking / SerDes Bridge
PCIe↔Ethernet/JESD bridges with deterministic latency.
Industrial Vision/Imaging
Multi-MIPI/SLVS-EC ingest, de-mosaic/filters and line-level timing.
DAQ / Converter Front-End
JESD204B/C with DDC/spur cleanup and tight sync sampling.
Motor & Power Control Co-Design
Fast protection, PWM synthesis and hardened position/current loops.
Crypto / Root of Trust
HW AES/public-key, protocol offload and updatable secure logic.
Rad-Hard / Automotive
Radiation & ASIL practices with monitoring and documents.
Key Specs & Selection
Logic Size (LUT/FF/K-LEs)
Keep 20–30% headroom for timing closure.
DSP & Memory
Check slices and BRAM/URAM for filters/matrices/buffers.
SerDes Line-Rate/JTOL/EQ
Align with protocol target and channel budget.
Fmax & Clock Regions
Plan for critical paths across multiple clock regions.
Power/Thermal
Analyze static/dynamic power and thermal envelopes.
Longevity & BSP/IP
Drivers/IP availability and long-term supply plans.
Design Hooks & Pitfalls
Timing Closure
Partition clocks; CDC via async FIFOs/handshakes; retime/pipeline.
Complete Constraints
Cover I/O/clock/multicycle/false/virtual paths end-to-end.
Reset & Boot
Sync resets; manage POR and I/O tri-state → active transitions.
SerDes SI/PI
Clean refs, AC-couple/terminate, length-match and EQ budgeting.
DDR Layout
Length-match/grouping, minimize fly-by, Vref/termination & PSRR.
Partial Reconfig
Region boundaries, clock isolation and stable interface shells.
Power & Thermals
Clock gating, low activity and floorplan to avoid hot-spots.
Security & Upgrades
Key mgmt, dual-image rollback and field logs/black-box.
Quick Pairings
High-Speed Capture
FPGA + JESD204C + low-jitter clocks + DDC/FFT + TSN/GbE.
Vision Aggregation
SoC-FPGA with multi-CSI, ISP/accelerators, display/encode & secure boot.
Comms Bridge
SerDes PCIe↔10/25G Ethernet with MACsec/TSN options.
Motor/Power Co-Design
DSC/MCU control + FPGA PWM/fast protection + position/ADC hardening.
