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Jitter Attenuators / Clock Cleaners: Tunable Loop Bandwidth

Jitter Attenuators / Clock Cleaners: Tunable Loop Bandwidth

← Back to:Reference Oscillators & Timing

A clock cleaner is not “the cleanest clock wins”—it is an engineering trade-off tool that shapes jitter transfer to match your endpoint’s acceptance window while preserving the required tracking, redundancy, and holdover. The right choice is the one that meets your defined jitter window + sign-off criteria with a verifiable A/B test, not the lowest ps number on a different window.

What is a Jitter Attenuator / Clock Cleaner

A clock cleaner is a timing control block that shapes the timing noise from an upstream reference into a defined output jitter profile—tracking low-frequency wander when needed and attenuating higher-frequency jitter that hurts converters and high-speed links.

The 3-block mental model

Input Dirty reference (XO/PLL/backplane/clock domain)
Loop Tunable loop bandwidth + reference selection + holdover behavior
Output “Clean” clocks for ADC/DAC sampling, SerDes, and deterministic sync signals (e.g., SYSREF)

Attenuate vs Track (the engineering decision)

  • If the system must follow an external time/frequency reference (network sync, disciplined sources), loop bandwidth cannot be arbitrarily small—wander/offset must be tracked.
  • If the endpoint is random-jitter limited (high-speed ADC/DAC SNR, tight SerDes margin), favor stronger attenuation so the output is dominated by the cleaner’s low-noise source and loop shaping.
  • If both are required, the robust pattern is layering: upstream handles long-term disciplining; downstream cleaner enforces low jitter close to sensitive endpoints.

Scope guardrails (to avoid cross-page overlap)

In scope Loop BW tuning, ref selection, holdover, jitter profiles, validation hooks
Out of scope PN/jitter math derivations, synthesizer spur deep-dive, fanout/crosspoint selection details

This page focuses on how a cleaner is applied and tuned so that the output clock meets endpoint sign-off. Foundational definitions and deep synthesizer theory should be handled by dedicated pages, then referenced here as needed.

Clock cleaner role diagram Diagram showing dirty reference inputs feeding a clock cleaner with tunable loop bandwidth, holdover, and reference selection, producing outputs for ADC, SerDes, and SYSREF. Dirty Ref A XO / PLL / backplane Dirty Ref B backup / ext ref Clock Cleaner Jitter Attenuator Tunable Loop BW Ref Select Holdover Clean Track ADC / DAC sampling clock SerDes ref / CDR assist SYSREF deterministic sync Goal: shape jitter profile

Where it sits in the clock tree

Placement determines what the cleaner can fix. A cleaner cannot remove noise that is introduced after it—fanout buffers, long routes, poor return paths, and supply coupling near endpoints can dominate the final jitter seen by converters or SerDes.

Default placement rule (works in most systems)

  • Use a central cleaner when multiple domains must share a controlled reference (common ref selection, shared alarms, unified holdover policy).
  • Add near-endpoint cleaning or isolation when the last segment is high-risk: long routes, aggressive fanout, mixed-signal coupling, or tight jitter budgets at the endpoint.
  • For both synchronization and low jitter, prefer a layered clock tree: upstream handles long-term tracking; downstream enforces low jitter close to sensitive receivers.

Central cleaner vs near-endpoint cleaner (what changes)

Central Cleaner near source / timing hub
  • Pros: unified ref policy, shared alarms, clean fanout inputs
  • Cons: last-mile routing/fanout can re-inject noise
  • Watch: buffer supply noise, long differential return discontinuities
Endpoint Cleaner close to ADC / SerDes
  • Pros: protects the most sensitive segment, short “clean” routes
  • Cons: can fragment ref policy and complicate redundancy
  • Watch: mismatched loop settings across domains, local coupling

Redundancy and “hitless” switching (scope-limited note)

“Hitless” behavior is a system property: it depends on reference health criteria, phase continuity, and how holdover/smoothing is implemented—not only on the mux. This page focuses on how the cleaner contributes (ref monitoring, holdover policy, and output profile continuity) without diving into crosspoint/mux device selection.

Clock tree placement topologies Diagram comparing star, tree, and backplane clock distributions, showing central versus near-endpoint cleaner placement and the fanout and routing segments that can reintroduce noise. Topologies: Star / Tree / Backplane Central cleaner Near-endpoint iteration STAR Source / Synth Fanout ADC SerDes IO Risk: last-mile re-injection TREE Source / Hub Cleaner + Fanout ADC SerDes Best for: layered control BACKPLANE Timing Hub Backplane / Cable Card A Endpoints Card B Endpoints Note: redundant paths

The only jitter metrics you actually need for selection & sign-off

The fastest way to avoid timing surprises is to speak a budget + sign-off language. That language is not “a single jitter number”—it is a window (integration bandwidth), a composition (random vs deterministic), and a system behavior (transfer / tolerance / generation).

Selection vs sign-off (different goals, different mistakes)

Selection Compare candidates only when the integration window and test conditions match.
  • Window must be stated (example: 12 kHz–20 MHz).
  • Conditions must be stated (output frequency, format, termination, supply filtering).
Sign-off Reproduce the datasheet window and measurement chain; otherwise, results will drift by large factors.
  • Use the same bandwidth / filters (and note if spurs are included).
  • Document fixture, probing, and terminations to avoid “false TIE” readings.

The 3 metrics that close budgets (and why they fail systems)

1) RMS jitter (with window)

This is the random timing-noise total inside a stated integration bandwidth. Converters are typically limited by random jitter (SNR/ENOB degradation at higher input frequencies), while many links translate excess random jitter into margin loss.

2) Deterministic content (spurs / peaks)

A single spur can dominate spurious compliance even if RMS jitter looks small. Sign-off must track presence + offset location of deterministic tones (reference-related spurs, supply modulation, coupling).

3) Transfer / tolerance / generation (one-line split)
  • Transfer: how much input jitter passes through at each offset.
  • Tolerance: how much jitter the endpoint can accept without failing.
  • Generation: jitter created internally (floor) that cannot be filtered away.

Datasheet reading checklist (what to find before committing)

  • Phase noise plots: offset span, output frequency, test setup notes.
  • RMS jitter: integration bandwidth, spur inclusion, conditions.
  • Jitter transfer: loop BW range, peaking behavior, measurement conditions.
  • Output standard: level/termination assumptions (LVDS/HCSL/LVPECL/LVCMOS).
  • Power sensitivity: rail filtering guidance and noise coupling warnings.

Key rule: a jitter number without a stated window is neither comparable nor sign-off-ready. Deep definitions and formulas belong to the dedicated Phase Noise & Jitter page; this section focuses on engineering closure with minimal vocabulary.

Phase noise window alignment for jitter sign-off Simplified phase noise curve with spurs, an integration window highlighted, and two endpoint sign-off windows for ADC and SerDes showing different measurement windows lead to different jitter numbers. PN (simplified) Spur Integration window RMS jitter offset dBc/Hz Endpoint sign-off windows ADC random jitter sensitivity SerDes mask / tolerance segments Different windows → different jitter numbers (match datasheet conditions for sign-off)

Cleaner architectures that matter (and what they imply)

Architecture choice is a behavior choice. The right question is not “which PLL is used,” but how the output behaves under noisy references, switching events, and long-term drift: cleaning strength, tracking ability, and operational complexity.

Architecture map (what changes in practice)

Analog PLL cleaner

  • Shines: strong mid/high-frequency attenuation with stable behavior.
  • Pitfall: if loop settings are wrong, peaking can amplify jitter.
  • Verify: jitter transfer curve + lock time under real reference quality.

DPLL cleaner

  • Shines: programmable tracking/holdover policies; rich monitoring.
  • Pitfall: configuration complexity; behavior can vary by profile.
  • Verify: reference switching, alarm thresholds, and profile persistence.

Dual-loop / multi-loop (often with external VCXO/VCO)

  • Shines: separates tracking (low-f) from cleaning (high-f) more explicitly.
  • Pitfall: higher verification cost; more ways to create spurs/steps.
  • Verify: handoff between loops, phase continuity, and worst-case drift.

Deep synthesizer spur mechanisms belong to the dedicated PLL page; this section focuses on system behavior and verification.

Reference selection & holdover (concept-level, sign-off driven)

Ref select is not “a mux”

  • Health criteria: frequency offset, missing pulses, phase jumps.
  • Switch behavior: phase step vs smooth transition depends on policy + loop settings.

Holdover is an error-growth story

  • Dominant factors: local oscillator quality, thermal gradients, calibration.
  • Sign-off hook: define “usable holdover time” as time-to-exceed system error budget.

Output implications (avoid hidden system mismatches)

  • Related vs independent outputs: correlation affects multi-channel alignment and coherent sampling behavior.
  • Multi-output skew control: phase/latency consistency is a sign-off item when multiple endpoints must align.
  • SYSREF distribution (touchpoint only): deterministic sync signals should be managed within the same clock domain policy; deep JESD204 details belong to the dedicated JESD204 clock page.

Conclusion: Define tracking needs first, then purchase cleaning performance with loop design and verification.

Cleaner architecture comparison cards Three side-by-side architecture cards: Analog PLL, DPLL, and Dual-loop, each with a minimal block diagram and three keywords for cleaning strength, tracking ability, and complexity. Architecture cards behavior-focused comparison Analog PLL Ref Loop VCO Div cleaning strength: medium tracking ability: medium complexity: medium DPLL Ref DPLL core NCO Output cleaning strength: medium tracking ability: strong complexity: higher Dual-loop Ref Tracker Cleaner Output cleaning strength: strong tracking ability: strong complexity: higher

Tunable loop bandwidth: cleaning vs tracking trade-off

Loop bandwidth (BW) is the main control knob that decides how much input reference jitter passes to the output. Smaller BW behaves more like an isolator (stronger attenuation), while larger BW behaves more like a follower (stronger tracking). The best setting is the one that closes the endpoint sign-off window while meeting tracking requirements without creating peaking or long recovery behavior.

What BW really changes (engineering intuition)

Smaller BW Stronger attenuation of input jitter, weaker tracking, slower reacquire.
  • Output becomes more dominated by internal noise floor and power coupling.
  • Good for “keep the endpoint clean” cases (converter clocks, sensitive domains).
Larger BW Stronger tracking, but more input jitter is replicated at the output.
  • Better for synchronization/wander-following needs.
  • Risk: output looks “as dirty as the ref” inside the tracking region.

Practical warning: if BW is reduced but output jitter does not improve, the dominant limiter is likely internal floor, supply sensitivity, or downstream injection (not the reference). This is a sign to verify power filtering and endpoint coupling paths.

A tuning sequence that closes budgets (no control theory required)

  1. Lock the endpoint sign-off window: define the integration bandwidth and acceptance method for the clock domain (converter SNR budget or SerDes mask/tolerance).
  2. Decide if tracking is required: determine whether the domain must follow an external reference (wander/sync), or must isolate and stay clean.
  3. Pick BW direction first: smaller BW for attenuation-first designs; larger BW for tracking-first designs. Treat “mid BW” as a candidate only after peaking behavior is verified.
  4. Tune damping / profile to suppress peaking: stability-related behavior is often dominated by damping and profile settings, not just BW value.

Deep control-theory derivations belong to PLL fundamentals pages; this section focuses on engineering decisions and verification hooks.

Peaking & “getting worse while tuning” (fast symptom → action mapping)

Typical symptoms

  • Integrated RMS jitter increases at mid BW while small/large BW look better.
  • A “bulge” appears in phase-noise/transfer behavior near the BW region.
  • Reacquire after disturbance shows overshoot-like phase wandering or long settle.

Quick checks

  • Compare 3 profiles (small/mid/large BW) using the same integration window.
  • Apply a controlled input disturbance (small phase/frequency step) and observe recovery.
  • If only mid BW is worse, treat peaking/damping as first suspects.

Sign-off hook: verify that the transition region does not dominate the integrated window and that reacquire behavior fits the system downtime/holdover budget.

Jitter transfer vs loop bandwidth (concept) Three jitter transfer curves for small, mid, and large loop bandwidth, with labeled tracking, transition, and attenuation regions and a peaking risk marker in the transition region. Jitter transfer (concept) BW moves the transition region Tracking Transition Attenuation offset |H| Peaking risk Legend Large BW Mid BW Small BW Rule Match BW to endpoint window and tracking requirements.

External references, redundancy, and holdover (how not to get burned)

External reference inputs and redundancy only improve reliability when the system defines health criteria, a switching policy, and a measurable holdover budget. Protocol synchronization details (PTP/SyncE) are handled on timing pages; this section focuses on hardware policy and failure handling.

Multi-reference inputs: priority + health criteria (what must be defined)

  • LOS / missing pulse: detect missing reference activity.
  • Frequency offset: compare against allowed offset thresholds.
  • Phase jump: identify abrupt phase steps that can break hitless expectations.
  • Hysteresis + dwell time: prevent chatter near thresholds.

Implementation note: health criteria must be measurable with local monitoring (counters, alarms, phase/frequency monitors) so that switching decisions remain deterministic across units and test fixtures.

Holdover: define “usable time” by error growth, not by presence of a feature

What sets holdover quality

  • Local oscillator quality (drift sensitivity, thermal behavior).
  • Thermal gradients and placement (airflow, proximity to heat sources).
  • Calibration parameters (temperature compensation, learned drift).

Sign-off definition: “usable holdover time” is the time-to-exceed the system clock error budget (phase/time/frequency), under worst-case temperature and power conditions.

Hitless switching: realistic boundaries (set correct expectations)

Fully disturbance-free switching is only achievable when references are already aligned (or can be smoothly aligned) in phase and frequency. Otherwise, a phase step or short transient is unavoidable, and success depends on the endpoint’s tolerance and the switching policy.

  • Best case: aligned refs + smooth policy → minimal phase disturbance.
  • Worst case: large phase jump at switch → downstream loss-of-lock or sync failure.

Verification hooks (fault injection + pass criteria placeholders)

Fault injection

  • LOS: disconnect / gate reference and observe state transitions.
  • Offset: inject a controlled frequency error and check for false switching.
  • Phase jump: force a step-like event and observe endpoint tolerance behavior.
  • Reacquire: restore main reference and verify recovery behavior and duration.

Pass criteria placeholders

  • No chatter: switching frequency ≤ X events/hour under defined disturbances.
  • Holdover drift slope ≤ budget (time-to-exceed ≥ Y minutes/hours).
  • Reacquire time ≤ system downtime budget; no endpoint loss-of-lock.
Main/backup reference switching state machine A state machine showing Lock Main, Monitor, Switch/Freeze, Holdover, and Reacquire states with trigger tags like LOS, offset, alarm, and stable timer. Ref switching policy state machine (concept) Lock Main Ref A Loop ON Monitor LOS offset Switch / Freeze alarm step Holdover Local XO Freeze Reacquire stable timer Ref A normal LOS holdover recovered Policy hysteresis + dwell time phase continuity rules fault injection sign-off

Endpoint-driven jitter profiles: ADC/DAC vs SerDes vs JESD204 SYSREF

A single “RMS jitter number” is not a universal sign-off metric. Cleaner settings must be mapped to the endpoint’s acceptance window: converters prioritize low random jitter for SNR/ENOB, SerDes prioritizes tolerance/mask behavior (often with SSC), and JESD204 requires coherent ref clock plus SYSREF distribution within alignment windows. This section provides endpoint mapping; protocol compliance details belong to their dedicated pages.

Three endpoint “sign-off windows” (what each domain truly cares about)

Converters (ADC/DAC) Random jitter dominates SNR/ENOB sensitivity; short, differential routing matters.
SerDes Jitter tolerance and masks are king; SSC and correlation expectations may differ by topology.
JESD204 (Ref + SYSREF) Alignment windows and deterministic distribution behavior dominate the integration outcome.

A “profile” should be defined as: measurement window + spur policy + distribution coherence + sign-off method.

Practical mapping: what to optimize and what usually breaks first

Converters: prioritize low integrated random jitter in the endpoint’s integration window, keep the clock path short and differential, and treat spurs as “in-band killers” when they land inside the sampled bandwidth or near key offsets.

SerDes: prioritize tolerance/mask alignment and link stability under expected SSC behavior. Treat “looks clean on RMS jitter” as insufficient unless it matches the receiver’s jitter decomposition and acceptance method.

JESD204: prioritize deterministic ref clock + SYSREF distribution: arrival skew, alignment windows, and behavior during switching/reacquire. “Cleaner is lower jitter” is secondary if SYSREF timing is not repeatable.

Conflict resolution: split profiles by domain instead of forcing one output to do everything

When a system mixes converter clocks (attenuation-first) with SerDes domains (tolerance-first), the robust pattern is hierarchy: upstream stages meet tracking and system synchronization, while downstream stages near sensitive endpoints enforce cleaning. This avoids chasing a single loop BW setting that fails at least one endpoint.

  • Upstream: tracking-friendly profile for system reference following.
  • Downstream: cleaning-friendly profile for the most sensitive domains (typically converters).

Verification hooks (minimum viable sign-off per endpoint)

Converters

  • Measure integrated RMS jitter using the endpoint’s window (same method across builds).
  • Check for in-band spurs and near-offset bulges that correlate with SNR degradation.

SerDes

  • Validate against the receiver’s tolerance/mask method, not only against an RMS number.
  • Compare SSC-on vs SSC-off behavior if the platform expects spread-spectrum operation.

JESD204

  • Verify SYSREF arrival skew and distribution repeatability (alignment window preserved).
  • Verify behavior during switching/reacquire does not violate deterministic timing requirements.

This section maps profiles to endpoints. Detailed protocol and compliance definitions are handled on their dedicated pages.

Endpoint requirements: converters vs SerDes vs JESD204 Three cards showing dominant metric, typical frequency, and common pitfall for ADC/DAC, SerDes, and JESD204 SYSREF domains. Endpoint-driven profiles different windows → different sign-off ADC / DAC noise floor Dominant RMS window Typical 100–500 MHz Pitfall spur in-band long routing SerDes mask / tolerance SSC Dominant tolerance Typical 100 MHz class Pitfall wrong window SSC mismatch JESD204 Ref SYSREF Dominant alignment Typical SYSREF pulses Pitfall SYSREF skew non-determinism

Spurs, supply coupling, and “fake jitter” problems

When a cleaner “does not help,” the common root cause is that the limiter is not random jitter from the reference. Spurs, supply modulation, layout coupling, and measurement traps can dominate the observed result. This section focuses on attribution and fast checks; full EMI strategy belongs to dedicated supply/EMI pages.

Spur attribution: three practical source classes (with quick checks)

Reference spur Moves with reference frequency/ratio changes.

Quick check: change the reference frequency or divider plan; confirm the spur moves accordingly.

Supply spur Correlates with rail ripple and load events.

Quick check: probe the sensitive rails in frequency domain; temporarily improve filtering and watch spur movement.

Layout coupling Changes with routing/return paths and probing.

Quick check: move cable/probe ground method; verify whether the observed spur/jitter changes abnormally.

Why spurs can look worse after “cleaning” (the normal explanation)

Cleaner profiles often reduce the random noise floor first. If a spur’s absolute amplitude stays similar while the floor drops, the spur becomes more prominent on a spectrum plot. This does not mean the cleaner is ineffective; it means the dominant limiter has shifted from random jitter to deterministic components.

Correct interpretation: evaluate random jitter and spur impact separately, using the endpoint’s sign-off window and acceptance method.

Supply isolation “minimum action pack” (avoid supply-modulated jitter)

  • Use low-noise regulation for sensitive clock domains (and keep return paths continuous).
  • Apply domain filtering (π/RC/bead segments) instead of “one filter for everything.”
  • Separate noisy digital return currents from analog clock/VCO returns; avoid crossing splits/slots.
  • Confirm output standard and termination are correct; reflections can convert into apparent edge timing noise.

This section focuses on spur/jitter failure modes. Full EMI planning and compliance belong to dedicated Supply & EMI pages.

Measurement traps: “fake TIE” and misleading plots (fast fixes)

  • Probe loading / grounding: ground method changes can reshape spurs dramatically.
  • Wrong termination: reflections can look like timing variation and inflate TIE.
  • Trigger / timebase: instrument setup can create apparent “jitter” not present in the clock.
  • Bandwidth mismatch: measurement bandwidth changes integrated results; keep windows consistent.

Sign-off rule: repeatability matters more than a single plot. Fix the window, termination, cabling, and analysis method, then compare profiles (before/after cleaning) under identical conditions.

Spur source map: reference vs supply vs layout coupling A central output spectrum with three arrows pointing to reference spurs, supply spurs, and layout coupling, each with a quick check label. Spur attribution map dominant limiter may not be random jitter Output spectrum before after (lower floor) spurs stand out after cleaning Reference Change ref Supply Probe rail Layout Move cable Rule: separate random jitter sign-off from spur attribution, using the endpoint window.

Engineering checklist (design review you can reuse)

This checklist is designed for repeatable design reviews and auditable sign-off. Items are grouped by priority and structured as Must (blocking), Should (risk), and Evidence (what to capture). The intent is to prevent “cleaner looks fine on paper” failures caused by clock-tree placement, supply coupling, routing/termination, or configuration drift.

A) Clock-tree (hierarchy, redundancy, fanout, output standards)

Must

  • Define a single clock-tree hierarchy: Source → Synth/PLL → Cleaner → Fanout → Endpoints.
  • Provide a controlled bypass path (debug/A-B) that can be enabled without rewiring the platform.
  • Define main/backup behavior: ref priority, health criteria (LOS/offset/alarm), and switching policy.

Should

  • Control fanout depth and define a fanout budget per domain (each stage adds jitter/skew risk).
  • Confirm endpoint I/O standards are consistent (LVDS/HCSL/LVPECL/LVCMOS) and termination is planned per standard.

Evidence

  • One-page clock-tree diagram with standards labeled at each output.
  • Endpoint list: frequency, standard, termination, fanout depth, bypass availability.

B) Power (noise budget, isolation, sequencing, sensitive pins)

Must

  • Define sensitive rails and isolate them from high di/dt domains (VCO/PLL/outputs vs digital I/O).
  • Verify sequencing and reset/config order are deterministic and documented.
  • Explicitly review sensitive pins (e.g., REFIN/VCXO/VDD) for dedicated decoupling and clean return paths.

Should

  • Apply domain filtering near the sensitive rail entry (π/RC/bead segments as appropriate).
  • Validate return-current continuity; avoid split/slot crossings that force detours in the sensitive domain.

Evidence

  • Rail measurement points and expected ripple/offset criteria (project-defined).
  • Power-up / config timing diagram and “known-good” profile ID.

C) Routing (diff impedance, length match, return paths, term location)

Must

  • Use controlled impedance routing for differential clock pairs; keep them short and direct.
  • Maintain return-path continuity; forbid split/slot crossings on critical clock routes.
  • Place termination per topology and standard (source vs load); confirm “as-built” matches the plan.

Should

  • Limit long parallel runs near switching nodes and high-speed data lanes.
  • Document critical segments where length matching matters (not every segment needs the same constraint).

Evidence

  • Annotated layout screenshots for key clock routes (diff pair + term + return crossings).
  • Termination BOM list: values, positions, and DNP options.

D) Control (I²C/SPI, boot config, status readback, alarms)

Must

  • Define a deterministic boot sequence: reset → configuration write → readback verify → enable outputs.
  • Read and log lock/holdover/alarm status; do not rely on “seems locked” assumptions.
  • Expose alarms/interrupts to the system (loggable and actionable).

Should

  • Implement configuration versioning and register snapshots for traceability.
  • Use readback compare to prevent silent configuration drift across builds.

Evidence

  • Register dump template: required registers, capture trigger, and storage location.
  • Alarm map: alarm type → system event/log field → operator action.

E) SYSREF / sync signals (minimal “need/no-need” plus routing/distribution notes)

Must

  • Decide whether SYSREF is required (Yes/No) and document the system reason in one line.
  • If used: keep SYSREF distribution deterministic and consistent with the ref clock distribution approach.

Should

  • Apply clock-grade routing discipline to SYSREF (clean returns, controlled paths, correct termination).
  • Avoid introducing non-determinism via unnecessary switching stages on SYSREF paths.

Evidence

  • SYSREF mini diagram: endpoints, fanout depth, and routing/termination notes.
Reusable clock-cleaner design review checklist Five checklist blocks: Tree, Power, Routing, Control, Verify. Each block shows three short keywords. Design review checklist auditable blocks + minimal keywords Tree Hierarchy Redundancy Power Isolation Sequencing Routing Diff / Return Termination Control Boot Read Alarm I²C/SPI + logs Verify A / B Window + records

Verification & production test: how to prove you actually cleaned jitter

Verification should be window-aligned, repeatable, and cost-aware. The goal is not to buy the most expensive lab setup for every unit, but to prove causality (A/B with bypass), capture a minimal production test set that catches drift and misconfiguration, and log enough field data to reproduce failures under the same profile.

The verification path (repeatable, auditable)

Setup → Measure → Compare (bypass) → Decide → Record

Each step must produce a tangible artifact: a wiring/termination plan, a window-aligned measurement, a bypass delta plot, a decision record, and a log/register snapshot.

Lab: align the measurement window with the datasheet and endpoint sign-off

  • Use the same integration window and conditions used by the datasheet (or document the deviation).
  • Keep termination, cabling, probing, and analysis method fixed across builds.
  • Record environmental context: temperature, rail state, reference state, and active profile ID.

Output artifact: a window-labeled measurement report (method + conditions + results).

A/B compare: bypass the cleaner to prove causality and localize the limiter

  • Compare “cleaner in path” vs “bypass” under identical windows and identical measurement setups.
  • If bypass and cleaner are similar, the limiter is likely board-level coupling, supply modulation, or termination.
  • If bypass is worse, the cleaner contributes; then focus on profile tuning and upstream reference quality.

Output artifact: a delta plot and a one-page “limiter classification” note (reference vs supply vs layout vs measurement).

Production + Field: minimal tests and logs that catch drift without expensive instrumentation

Production minimum set

  • Lock time and lock status consistency (repeatable across power cycles).
  • Alarm/LOS/holdover flags (triggerable and readable).
  • Frequency offset and output-level standard sanity checks.
  • Register readback consistency (configuration drift detection).

Field logging essentials

  • Profile/config version ID and register snapshot hash.
  • Alarm counters, reference switching events, and holdover duration.
  • Temperature and rail health summary (for correlation with drift/spurs).

Output artifact: production test record + field log schema that supports replay and root-cause classification.

Verification chain: setup to records A five-step flow: Setup, Measure, Compare (bypass), Decide, Record. Each step includes a short output artifact label. Verification chain repeatable window + A/B causality + records Setup term plan wiring Measure window report Compare (bypass) delta plot Decide class actions Record logs regs Outputs: wiring plan • window-aligned report • bypass delta • decision record • log schema

Applications (templates you can reuse — no scope creep)

This section is intentionally not an industry encyclopedia. Each template is a copy-paste pattern: Clock chain → Key setting → Common pitfall → Example material numbers.

A) High-speed ADC/DAC + JESD204 (Ref clock + SYSREF)

Clock chain: XO/PLL → Cleaner → SYSREF/Fanout → ADC/DAC + SYSREF endpoints
Key setting: define two windows (converter clock jitter vs SYSREF determinism) and lock them as one profile
Common pitfall: SYSREF routing/mux adds non-deterministic delay even when the clock jitter “looks fine”
Example material numbers (starting points)
  • TI: LMK04828 / LMK04821
  • Analog Devices: HMC7044 / AD9528
  • Skyworks (Silicon Labs): Si5395 / Si5345
Verify: output standards, SYSREF capability, and the stated jitter integration window.

B) FPGA/SoC multi-domain (central clean + distribute)

Clock chain: Ref (XO/backplane) → Central cleaner → Fanout → multiple clock domains
Key setting: one “system profile” with consistent output standards/terminations across domains
Common pitfall: mixed I/O standards or inconsistent terminations create “fake jitter” and random link failures
Example material numbers (starting points)
  • Skyworks (Silicon Labs): Si5341 / Si5345
  • TI: LMK04821 / LMK04828
  • Analog Devices: AD9528

C) SerDes / PCIe reference (scope-limited)

Clock chain: Ref → Cleaner/profile → endpoint reference clock pins
Key setting: decide SSC needed? then enforce correct output standard (HCSL/LVDS/LVPECL) + clean power
Common pitfall: optimizing for lowest RMS jitter while violating endpoint tolerance/SSC policy
Example material numbers (starting points)
  • Skyworks (Silicon Labs): Si5341 / Si5395
  • Microchip: ZL30722
  • TI: LMK04821

D) Backplane / multi-card redundancy (don’t get burned)

Clock chain: Main/Backup refs → Cleaner w/ validation → distribution → endpoints
Key setting: define ref health rules (LOS + freq offset + phase jump) and holdover behavior
Common pitfall: “hitless” expectations without defining what phase transient is acceptable for the endpoint
Example material numbers (starting points)
  • TI: LMK05318 (network synchronizer / jitter cleaner)
  • Analog Devices: AD9545
  • Renesas: 8A34001 / 8A34005

E) Sync-required systems (scope-limited: hardware behavior only)

Clock chain: external reference(s) → DPLL cleaner → translated/filtered outputs
Key setting: start from “must track?” then set loop BW range; use fast-lock only for controlled transitions
Common pitfall: setting BW too narrow (great cleaning) and failing tracking/lock-time requirements
Example material numbers (starting points)
  • TI: LMK05318
  • Analog Devices: AD9545
  • Renesas: 8A34001 / 8A34005
  • Microchip: ZL30722

F) Lab A/B debug pattern (bypass to localize)

Clock chain: upstream → (bypass switch) → endpoint, then compare with cleaner enabled
Key setting: align measurement window to datasheet window; keep termination identical in A/B
Common pitfall: declaring “cleaner useless” when spurs/PSU coupling dominate the measurement
Example material numbers (starting points)
  • Microchip: ZL30722 (explicit bypass mode is common in this class)
  • Skyworks (Silicon Labs): Si5345 / Si5395
Diagram — Application “puzzle”: 6 reusable clock-chain patterns
Applications puzzle for jitter attenuators / clock cleaners Six mini-cards, each showing Source to Cleaner to Endpoint with minimal labels for metric, setting, and pitfall. Source → Cleaner → Endpoint (choose profile per endpoint window) A) ADC/DAC + SYSREF SRC CLEAN EP Metric: RMS jitter window Setting: profile + SYSREF B) FPGA/SoC multi-domain SRC CLEAN EP Metric: skew + jitter Pitfall: mixed standards C) SerDes/PCIe ref SRC CLEAN EP Setting: SSC? + standard Pitfall: window mismatch D) Backplane redundancy MAIN BKUP CLEAN EP ALARM E) Must-track systems REF DPLL OUT Rule: track first Then: clean within window F) A/B bypass debug SRC SW CLEAN BYP Same termination, same window, compare logs

IC selection logic (decision tree + must-ask fields)

Selection is a sequence problem: endpoint window → track or not → required attenuation/profile → I/O map → system robustness → prove it in test.

Step 1 — Define endpoint acceptance window
Output: jitter/PN integration window + pass/fail language (converter SNR impact vs link tolerance).
Shortcut: do not compare “ps RMS” unless the integration windows match.
Step 2 — Must it track an external reference?
Output: loop BW target range (track-first vs clean-first profile).
If tracking is required, “cleaning-only” BW can fail lock/holdover expectations.
Step 3 — Characterize the input reference class
Output: required attenuation and profile (noisy backplane vs local XO/TCXO/OCXO).
Cleaner value depends on the “before” quality; quantify it.
Step 4 — Build the I/O map
Output: frequency range, output count, standards (LVDS/HCSL/LVPECL/LVCMOS), phase/delay, SYSREF needs.
Avoid “spec meets” while missing the required output format/termination ecosystem.
Step 5 — System robustness checklist
Output: redundancy, holdover, alarm/interrupt plan, interfaces, thermal/power budget, configuration storage.
“Reference lost” handling must be defined before hardware is frozen.
Step 6 — Prove it (lab → production)
Output: bypass A/B plan + minimal production tests (lock time, alarms, freq offset, key regs checksum).
If it cannot be verified affordably, it is not a selection-complete solution.

Must-ask datasheet fields (audit-ready)

Performance in your window
  • Output jitter spec with integration limits
  • Phase-noise plots with stated conditions
  • Output format limits per standard
Transfer behavior
  • Jitter transfer curve or equivalent guidance
  • Programmable loop BW range + fast-lock modes
  • Peaking / damping notes (how it fails)
Robustness & recovery
  • Holdover spec + what it assumes (oscillator, temperature)
  • Reference validation rules (LOS / offset / phase jump)
  • Lock time and reacquire behavior
Integration & monitoring
  • Alarm pins + status readback registers
  • Profile storage / boot configuration method
  • Bypass mode for A/B debug (if available)

Example material numbers by “decision outcome” (not a product list)

Use these as datasheet starting points. Always verify package suffix, temp grade, output standards, and jitter window.

Converters + SYSREF emphasis
  • Analog Devices: HMC7044, AD9528
  • TI: LMK04828, LMK04821
  • Skyworks (Silicon Labs): Si5395, Si5345
Network sync / holdover / redundancy
  • TI: LMK05318
  • Analog Devices: AD9545
  • Renesas: 8A34001, 8A34005
  • Microchip: ZL30722
“Any-frequency” clocking / multi-output platforms
  • Skyworks (Silicon Labs): Si5341, Si5345
  • Renesas: 8A34001
  • Microchip: ZL30722
Diagram — 6-step decision tree (question → output → verification)
IC selection decision tree for jitter attenuators / clock cleaners Six stacked steps with arrows, each step shows a short question and a concrete output deliverable. Bottom bar lists final deliverables. Selection flow: window → track? → profile → I/O map → robustness → prove it 1 Question: What is the endpoint acceptance window? Output: integration limits + pass language 2 Question: Must the clock track an external reference? Output: loop BW target range 3 Question: How noisy is the input reference (class)? Output: attenuation need + profile choice 4 Question: What is the I/O map (freq, count, standard, SYSREF)? Output: output map + termination plan 5 Question: What is the robustness requirement (redundancy/holdover/alarms)? Output: fault policy + monitoring fields 6 Question: Can it be verified (lab + production) within budget? Output: A/B bypass plan + minimal tests Deliverables: Window • Profile • I/O map • Fault policy • Test plan • Logs

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FAQs (field debug, strictly within clock cleaner boundary)

Each answer is intentionally short and audit-ready. Compare only when the measurement window matches the datasheet window.

Why does output jitter get worse when I widen loop bandwidth?
Likely cause: Wider BW passes more input jitter (and may introduce transfer peaking in the transition region).
Quick check: Compare output integrated jitter in the same window W at two BW settings; look for a hump/peaking near the crossover region in the PN/TIE plot.
Fix: Start from the endpoint window → choose the smallest BW that still meets tracking/lock needs; use a “low-peaking” profile if available (e.g., AD9545 / LMK05318 class devices provide multiple profiles).
Pass criteria: Integrated RMS jitter(W) ≤ J_budget and no observable peaking above the allowed margin (e.g., peak gain ≤ G_max in the transition band).
Why does my cleaner “lock” but the ADC SNR still collapses at high input frequency?
Likely cause: The acceptance window used for “jitter” does not match the ADC’s effective sensitivity window; board-level coupling/termination can dominate even when locked.
Quick check: Do A/B at the ADC: measure SNR vs fin with cleaner enabled vs bypass, keeping identical routing/termination; confirm the jitter integration window equals the datasheet claim window.
Fix: Re-define the window W for ADC sign-off; tighten clock routing (short, differential, correct termination), and use a converter-oriented cleaner path (e.g., LMK04828 / HMC7044 / Si5395 class) with appropriate profile.
Pass criteria: At fin = F_max, ΔSNR(clean vs baseline) ≤ ΔSNR_max AND Integrated jitter(W_ADC) ≤ J_budget_ADC under the same measurement setup.
Why do I see a spur at the reference offset that survives cleaning?
Likely cause: The spur is deterministic (reference spur / divider spur / coupling) and is not removed by “random-jitter” attenuation.
Quick check: Slightly detune the reference (or swap reference source): if the spur moves with it, it is reference-related; if it correlates with a rail ripple or load step, it is supply/coupling-related.
Fix: Clean the spur at the source and isolation points: ref path isolation, rail filtering, separation of supplies/returns; if available, select a profile with better spur performance (device-dependent; check AD9528 / Si5345 / LMK04821 class docs).
Pass criteria: Spur amplitude ≤ spur_mask at the specified offset(s), and SFDR/BER impact is below the system limit (e.g., spur ≤ S_spur_max dBc in band).
Cleaner looks great on the bench—why does it fail on the real PCB?
Likely cause: The PCB introduces “fake jitter” via wrong termination/impedance, return-path discontinuity, or supply coupling into the clock path.
Quick check: Measure at the same node and same window W (bench vs PCB). Then probe the PCB at: cleaner output pin → after fanout → at endpoint. Look for a step-change after one stage.
Fix: Enforce output-standard discipline (LVDS/HCSL/LVPECL) + correct termination placement; isolate supplies (quiet LDO/filters) and preserve continuous return paths under the clock pair.
Pass criteria: Board measurement equals bench-equivalent within tolerance: |J_board(W) − J_bench(W)| ≤ ΔJ_max and pass/fail is repeatable across power cycles.
How can I tell if the problem is supply coupling vs reference spurs?
Likely cause: A spur/jitter signature is being injected either through the reference path (ref spurs) or through rails/ground (supply modulation).
Quick check: Two knobs test: (1) swap/retune reference while keeping rails constant; (2) change rail filtering/load (or power the cleaner from a quieter source) while keeping reference constant. Track which knob moves the spur.
Fix: If reference-driven → improve ref cleanliness/isolation. If rail-driven → strengthen PSRR chain (quiet LDO, π filter, domain split) and reduce coupling loops.
Pass criteria: A single corrective action produces a consistent improvement: Δspur ≥ A_min dB or Δjitter(W) ≥ J_improve_min across repeated runs.
Why does switching references cause a phase step even with “hitless” claims?
Likely cause: “Hitless” is conditional—if refs are not phase-aligned (or health rules trigger a hard event), a transient phase step can still occur.
Quick check: Capture phase/time error at switchover and correlate with the device state machine (lock/holdover/reacquire). Check whether refs are frequency- and phase-coherent at the switching moment.
Fix: Define ref health rules (LOS + offset + phase jump) and switching policy (freeze/align/guard time). Devices targeting this space include AD9545 / LMK05318 / 8A34001-class parts—use their recommended modes rather than default.
Pass criteria: Phase step ≤ φ_max (endpoint tolerance) and reacquire/settle time ≤ T_settle_max, with no false switch events over N cycles.
Holdover seems fine at room temp—why does it drift badly across temperature?
Likely cause: Holdover performance is dominated by the local timebase quality and its temperature behavior (and by whether temperature compensation/calibration is enabled).
Quick check: Run a temperature sweep and log frequency/time error during holdover. Confirm whether calibration tables/temperature sensor inputs are used as intended (device feature dependent).
Fix: Upgrade the local reference quality (XO→TCXO/OCXO if required) and enable temperature compensation/calibration hooks. In holdover-centric designs, AD9545 / LMK05318 / 8A34001-class devices are common starting points—verify their holdover assumptions.
Pass criteria: Over the full temperature range: |Δf_holdover| ≤ f_max AND |TIE| ≤ TIE_max over the specified holdover duration.
Why does bypass mode look cleaner than “clean” mode in my setup?
Likely cause: Measurement/termination/spur dominance: cleaning lowers the noise floor, making deterministic spurs more visible; or the bypass path is being measured under a different window/termination.
Quick check: Ensure identical termination, identical node, identical window W, identical instrument settings. Compare (a) integrated jitter(W) and (b) spur height vs floor—both matter.
Fix: Fix spurs/coupling first (rails/layout/ref isolation). Then choose a profile that meets the endpoint window (e.g., Si5345/Si5395 or AD9528/LMK04821 family profiles—verify with datasheets).
Pass criteria: In the target window W: J_clean(W) ≤ J_bypass(W) by margin M, and spur_mask is met simultaneously (not one-at-a-time).
Why does SYSREF alignment degrade after changing loop settings?
Likely cause: Loop/profile changes alter effective group delay/phase relationships; SYSREF distribution may no longer be deterministic relative to the ref clock.
Quick check: Measure ref-to-SYSREF timing determinism before/after the change; confirm SYSREF path uses consistent buffering/termination and no unintended mux events.
Fix: Treat “ref + SYSREF” as one locked profile (do not tweak only one side). For converter clocking ecosystems, LMK04828 / HMC7044 / AD9528-class parts are common; verify SYSREF handling modes and recommended routing.
Pass criteria: Alignment error ≤ E_max (system-defined) over N power cycles and after profile changes; no intermittent alignment loss events.
What’s the fastest way to A/B test whether the cleaner is the bottleneck?
Likely cause: Bottleneck could be upstream reference, cleaner configuration, board coupling, or downstream fanout/endpoint termination.
Quick check: Three-node A/B: (1) measure at cleaner output pin, (2) after fanout, (3) at endpoint—then repeat with bypass (if supported). Keep window W and termination identical.
Fix: If degradation appears after fanout → prioritize additive jitter/rail isolation there. If already bad at cleaner output → profile/BW/ref path is the target. Use devices with explicit bypass/profiles when possible (e.g., Si5345/Si5395 / ZL30722-class devices—verify feature set per datasheet).
Pass criteria: Bottleneck segment identified by a step-change ≥ ΔJ_step in the same window W; fixing that segment yields repeatable improvement ≥ J_improve_min.
How do I choose jitter integration bandwidth to match the datasheet claim?
Likely cause: “ps RMS jitter” is only comparable when the integration limits, filters, and measurement method match the datasheet conditions.
Quick check: Recreate the datasheet window: same lower/upper offsets, same filtering/weighting, and same output mode. If the device offers multiple plots/specs, use the one that matches your endpoint window.
Fix: Freeze a single sign-off window W for your project and document it (lab + production). When selecting parts (e.g., LMK04828/AD9528/Si5395/AD9545 families), always tie the claim to its stated window.
Pass criteria: Your measurement uncertainty is bounded (U ≤ U_max) and the device meets J(W) ≤ J_spec(W) with guardband G across repeats and conditions.
Why does adding fanout buffers ruin the cleaner’s performance?
Likely cause: Fanout stage adds additive jitter/spurs, violates output-standard termination, or injects rail noise into the clock path.
Quick check: Measure jitter/PN at cleaner output vs after fanout under the same window W. If the delta appears only after fanout, it is additive/coupling rather than cleaner-limited.
Fix: Choose a low additive-jitter fanout with correct standard support and strong supply isolation; keep termination correct and close to the receiver. As starting points, use fanout families commonly paired with cleaners (verify): LMK048xx/LMK1Cxx ecosystem (TI) or dedicated low-jitter fanout parts from major vendors.
Pass criteria: Added jitter from fanout ≤ J_add_max and spur_mask is maintained at all outputs; skew/drift meets the system alignment budget.
Parts referenced in this FAQ (examples; verify suffix/package/temp grade)
Converter / SYSREF ecosystems
LMK04828, LMK04821, HMC7044, AD9528, Si5395, Si5345
Holdover / redundancy / DPLL
AD9545, LMK05318, 8A34001 / 8A34005, ZL30722
Note
Use as datasheet starting points only; validate output standards, jitter windows, and your endpoint acceptance plan.
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