• Multi-range matching: keep the downstream ADC/DAQ near its optimal input range across signal amplitude changes.
• Repeatability: gain ratios are set by internal networks (switchable resistors, switched-cap, transconductance cells), improving cross-board consistency.
• Controllable switching behavior: gain updates have defined timing and recovery, enabling blanking, sync updates, and production scripts.

• Input types: single-ended and differential; common-mode/headroom constraints as they relate to gain states.
• Gain mechanisms: resistor ladders, INA-like PGAs, fully-differential PGAs, switched-cap/charge-redistribution gain.
• Control: SPI/I²C, latch/sync pins, update timing, default state, and readback integrity.
• System position: Sensor/MUX → PGA → (optional AAF) → ADC/DAQ, focusing on settling, noise, and range utilization.

• Filter topology deep dives (Sallen-Key/MFB/SVF/biquads): only interface constraints are mentioned.
• Full FDA/ADC-driver theory: only the “must-not-break” load/stability checks are referenced.
• ADC architecture education: the ADC is treated as a load and timing constraint (settling window, sampling kickback).

• Primary target: lowest referred-to-input noise and drift in the passband.
• Main risk: leakage/contamination and bias current masquerading as “drift” at high gain.
• Must-own check: shorted-input RTI noise and warm-up stability at the intended gain state.

• Primary target: keep peaks inside the ADC window with guardband (avoid clipping and “empty codes”).
• Main risk: range chatter and wrong decisions if the chain is sampled before settling completes.
• Must-own check: tSETTLE at the required error after each gain step (not just “looks flat”).

• Primary target: identical settling and gain accuracy across channels.
• Main risk: different source impedances create different effective RC time constants → inconsistent settling per channel.
• Must-own check: per-channel settling test at the same gain state (scripted), including the real sampling window.

• Best at: repeatable gain ratios and production consistency.
• Primary risk: charge injection and node re-distribution → glitch + settling ownership after gain steps.
• Practical cue: large source impedance or capacitive load amplifies step transients and settling spread.

• Best at: differential sensors and long cables where CMRR dominates.
• Primary risk: input common-mode/headroom and protection behavior → slow overload recovery can mimic drift.
• Practical cue: a “perfect” DC spec can collapse when common-mode moves or clamps conduct.

• Best at: controlling output common-mode and driving differential chains.
• Primary risk: VOCM and output headroom; capacitive load (AAF/ADC input) can trigger ringing or stability loss.
• Practical cue: THD often spikes when swing approaches rails or VOCM is injected with noise.

• Best at: precise ratios via capacitor matching; stable gain across process.
• Primary risk: clock-related spur and folded noise; switching artifacts depend on clock integrity and layout.
• Practical cue: spurs at fCLK or harmonics indicate coupling into the analog path.

Continuous gain is useful for AGC and smooth control loops, but control-path noise and linearity calibration become primary owners. This page focuses on discrete programmable gain states.

• Best for: broad multi-range capture with simple firmware mapping.
• Risk: large step sizes can cause frequent re-ranging and larger switching transients.
• Rule: enforce hysteresis and minimum dwell time; keep a per-step settling budget.

• Best for: measurement systems where error budgets and calibration are tied to a small set of predictable ranges.
• Risk: too many states increase validation burden (settling + THD per state).
• Rule: keep states few and testable; validate worst-case settling in each state.

• Best for: thresholding and protection-style decisions where amplitude margins are tracked in dB.
• Risk: repeated step decisions can chatter without a clean metric and timing discipline.
• Rule: align decision thresholds with the valid sampling window; require lockout after each update.

SPI, I²C, parallel pins, or strap pins. The interface choice matters less than when the new gain becomes active and how the chain is gated until settling completes.

• Immediate update: gain changes right after write → always requires blanking.
• Latched update: write to shadow registers, then latch → enables predictable sync.
• Sync/LDAC-style: external edge triggers simultaneous activation → best for multi-channel coherence.

• Mute/hold behavior: define whether the output is disconnected, held, or continuous during updates.
• Readback integrity: readback, CRC/locking, and a deterministic power-up default state.
• Multi-channel sync: deterministic group update for multi-PGA or multi-channel PGAs.

• en / 1/f corner → noise floor, low-frequency stability
• in / bias / leakage → high-source-Z error, drift-like behavior
• Input range / common-mode → unexpected clipping, gain-state collapse
• Overload recovery → slow return after transients, “memory” errors

• Gain error / drift → calibration burden, temp stability
• Step accuracy / monotonicity → auto-range chatter, range boundary errors
• Gain flatness vs frequency → in-band amplitude error, channel mismatch

• Output swing / headroom → clipping margin per gain state
• THD/SFDR vs swing → distortion “knee” near limits
• Capacitive-load stability → ringing, slow settle, intermittent oscillation
• VOCM (diff) → distortion, headroom, common-mode noise coupling

• Glitch magnitude → false thresholds, invalid samples
• Settling time (to error band) → usable sampling window
• Slew / large-signal BW → step response, peak handling

• Signature: noise floor rises at low frequency; averaging stops improving after a point.
• Quick check: short input and measure RTI noise vs gain states; compare low-band vs wide-band.
• Mitigation: limit bandwidth, choose lower-noise PGA, avoid unnecessary gain where ADC no longer dominates.

• Signature: “drift” depends on humidity, cable touch, or channel selection; channel offsets diverge.
• Quick check: compare open/short input, swap source resistance, and repeat after warm-up.
• Mitigation: reduce source impedance, guard/clean PCB, define input bias return paths, limit leakage paths.

• Signature: distortion or clipping appears only at certain common-mode or gain states.
• Quick check: sweep common-mode while holding differential amplitude constant; record THD/clip flags.
• Mitigation: adjust VOCM/biasing, reduce swing in sensitive states, select wider-CM architecture.

• Signature: false thresholds, range chatter, or “bad samples” right after gain updates.
• Quick check: step gain and sample at the actual decision time; verify inside the target error band.
• Mitigation: enforce blanking + tSETTLE per step; prefer sync updates for multi-channel systems.

Best for selecting gain and comparing architectures. Everything is translated back to the input so source and front-end trade-offs become visible.

Useful for verifying output noise against ADC full-scale windows and for consistent bench measurements at a fixed output amplitude.

Combine source thermal noise with PGA en/in (high source impedance makes bias/leakage and current noise dominate the error).

Noise grows with bandwidth. The measurement bandwidth is set by filtering and sampling strategy; use the same bandwidth in budgeting and validation.

ADC noise and quantization, referred to input, shrink as gain increases. Once that term is small, further gain only reduces headroom and worsens distortion or settling.

• Signature: spike amplitude tracks step direction and step size.
• Usually worse with: high-impedance internal nodes and temperature swings.

• Signature: a step-like offset after the update, then a slow return.
• Usually worse with: larger state changes and mixed source impedances (MUX chains).

• Signature: the waveform looks clipped or slewed, then recovers slowly.
• Usually worse with: near-rail swing, heavy load, or capacitive drive.

• Signature: differential looks acceptable but CM jump causes THD/settling to degrade.
• Usually worse with: VOCM bandwidth limits or CM noise coupling.

• %FS for full-scale referenced systems
• LSB for ADC resolution referenced checks
• Absolute for threshold / protection decisions

tSETTLE changes with (from→to) gain states, output swing and common-mode, source impedance, load model, and measurement bandwidth.

Samples taken before tSETTLE@ε must be treated as invalid (discard, hold, or mark). This prevents glitch energy from entering control or decision logic.

• Delay sampling start after updates; discard N samples based on tSETTLE@ε.
• Use the same rule in firmware and production validation.

• Hold last valid output or mute during the invalid window.
• For decisions, tag samples as invalid rather than averaging them in.

• Use intermediate states for large jumps; limit maximum step size.
• Add hysteresis and minimum dwell time to prevent range chatter.

• Sources: cables, AAF input caps, ADC input network.
• Signature: ringing and longer tSETTLE; can become intermittent oscillation.

• Reality: the PGA “sees” frequency-dependent impedance, not the schematic.
• Signature: ringing/THD gets worse only in certain frequency ranges.

• Reality: periodic charge bursts distort settling and create sampling-related spurs.
• Signature: artifacts align with sampling rate or aperture timing.

• Reality: VOCM bandwidth and symmetry determine both stability and THD.
• Signature: CM noise or CM steps show up as differential distortion.

Place Riso close to the PGA output so the driver is isolated from downstream capacitance and sampling pulses.

Increase Riso gradually and track: ringing amplitude, tSETTLE@ε, and THD/SFDR. Stop when stability improves without unacceptable bandwidth loss.

Too much Riso forms extra poles/zeros with Cload and can reduce bandwidth or add gain error at high frequency.

• Clip / near-rail flags for hard protection.
• Window checks for amplitude boundaries.
• Noise proxy (SNR-like) to detect wasted resolution.

Apply up/down transitions that match the gain step table. Avoid large jumps that amplify transients and settling burden.

Use a wider band than measurement uncertainty so noise never toggles ranges. The saturation side can be more conservative than the low-level side.

Enforce a minimum time (or sample count) in each range. This prevents range chatter and protects throughput.

After any gain update, mark samples invalid until settling reaches the chosen error band. Discard, hold, or tag—never average invalid data in.

Require at least one valid sample after blanking to confirm the new range. If it fails the window, transition again with hysteresis and dwell rules.

• Binary-ish steps: fastest coverage of dynamic range.
• Ratio steps: stable boundaries for measurement chains.
• dB steps: consistent perceived changes for audio-like envelopes.

• Downshift: protect headroom and distortion (avoid clipping and recovery).
• Upshift: reduce resolution waste (avoid ADC noise dominance).
• Limit step size: keep settling windows bounded.

• Asymmetric hysteresis: tighter on the “too small” side, wider on the “near clip” side.
• Minimum dwell: lock each state long enough to get valid samples.
• Confirmation sample: require a valid re-check before declaring stable.

• Calibrate every range only if range-to-range error dominates the budget.
• Otherwise, prioritize the ranges used most often or nearest the decision thresholds.

• Use a small set of temperature points and a repeatable rule to update coefficients.
• Bind coefficients to the test conditions (bandwidth, range, and settling rule).

• Version: calibration version and firmware version must be recorded together.
• Traceability: include date, temperature model identifier, and range table identifier.
• Fallback: keep factory defaults and last-known-good for rollback.

After calibration, verify with an independent point. If it fails, do not accept the new coefficients.

Track coefficient movement across time/temperature. If drift exceeds the guardband, trigger re-calibration or rollback.

If a new calibration fails verification, revert to last-known-good and record the failure event for diagnosis.

• Keep high-Z nodes short and shielded; avoid long parallel runs.
• Define a bias return path so inputs do not float in certain ranges.

• Use guard rings for high-Z nodes and keep the guard reference consistent.
• Flux residue + humidity becomes a leakage amplifier; treat cleaning as an electrical step.

• TVS/ESD parts can leak; leakage often looks like “drift” at high gain.
• Verify leakage across temperature and humidity conditions.

• Match differential routes and keep return paths continuous.
• Avoid crossing splits; preserve symmetry through the PGA and into the ADC.

• Keep SPI/I²C and fast edges away from high-gain input nodes.
• Route digital lines with a clean return; avoid “loop” coupling into analog.

If the return path is broken, the system will create an unintended antenna. At high gain, this becomes deterministic spurs and unstable settling.

Use input RC to limit fault currents and reduce event energy; validate that it does not over-slow settling or create unacceptable phase shift.

Prefer low-capacitance protection to avoid loading high-gain nodes; check leakage across temperature to prevent drift-like errors.

Protection capacitance changes the effective load. Re-check ringing and tSETTLE@ε after adding the protection network.

• Input short point for RTI noise checks.
• Reference injection point for gain/offset verification.
• Loopback path for end-to-end validation.

• Range state, temperature point, bandwidth setting.
• Settling rule: error band ε and blanking duration.
• Calibration version and firmware version.

• Per range: noise, headroom, and tSETTLE@ε once with real loads.
• Confirm auto-range does not chatter under worst-case noise.