Scope: S/H (sample-and-hold) and T/H (track-and-hold) as analog signal-conditioning blocks that freeze a voltage at a defined instant so downstream measurement can finish with predictable timing and error.

A sample-and-hold family block has one core job: turn a continuous-time input into a short-time stable value. That stability window is not “free”; it is created by a switch, a hold capacitor, and a buffer, and it carries characteristic error terms (settling residue, pedestal, droop, and timing uncertainty).

S/H vs T/H is not just naming:

• S/H (Sample → Hold): the input is connected during a sampling window; at the sampling edge the circuit switches to hold. The critical requirement is that the held value must be settled to the target accuracy by the end of the acquisition interval.
• T/H (Track → Hold): the output actively follows the input during track, then freezes at the hold event. This is preferred when the system must define a precise sampling instant and keep the output consistent right up to that moment (common in fast pulse/step capture and tightly timed multi-channel sampling).

Where it sits (boundary kept intentionally clean): a practical chain places S/H or T/H after front-end gain/buffering and before the downstream decision/measurement engine. The block is often inserted because downstream needs time to settle, integrate, compare, or serialize the measurement—but the input may not wait.

Purpose: align all later specs to one time-axis language. Without a shared timing model, “acquisition time,” “aperture,” and “hold step” become ambiguous and design decisions drift.

The timing model defines when the circuit is allowed to follow the input and when the output must remain stable. The boundary between these states is the sampling event. In real circuits, the switching event produces a short transient (pedestal/glitch) that must be separated from the usable hold interval.

Core terms (execution-level definitions):

• Track time: interval where the switch is on and the hold node follows the input.
• Acquisition time: time required after an input change for the hold node to reach the target accuracy (e.g., ≤0.01%FS).
• Hold time: interval after the hold event where the output must remain within the allowed droop/error budget.
• Aperture delay: delay from the control edge to the effective sampling instant at the hold node.
• Aperture jitter (σt): time uncertainty of the effective sampling instant; converts input slope into voltage noise.

Purpose: turn datasheet terms into predictable failure modes. Each spec below is mapped to the error it creates and the use cases where it becomes the dominant limit.

S/H and T/H parts are often compared by “typical specs” without checking the conditions. The same headline metric can mean different real behavior depending on step size (ΔV), source impedance, hold capacitor, and timing window. A practical selection starts from error budget + timing window, then verifies which spec controls that budget.

Purpose: explain why large steps are the hardest case and provide a calculation framework to back-solve acquisition time or C_hold from an accuracy target.

During track, the hold capacitor must be charged (or discharged) toward the new input value. The dominant first-order path is an equivalent resistance feeding C_hold: R_eq ≈ R_source + R_on + R_driver. For many systems, the “headline” acquisition time is simply the time needed for this network to reduce the step error below a target.

A practical approximation for the remaining error after track time t is: residue ≈ exp(−t / (R_eq · C_hold)). This turns acquisition into a back-solvable constraint:

• Pick target error ε (e.g., 0.1%FS = 1e-3, 0.01%FS = 1e-4).
• Required time-constants N ≈ ln(1/ε) → about ~7τ for 0.1% and ~9–10τ for 0.01%.
• Enforce t_track ≥ N · R_eq · C_hold (or back-solve C_hold / R_eq).

Common large-step failure signatures (and what they imply):

• Ramp-like approach to final value → driver is slew-rate limited (track window must increase or driver must be upgraded).
• Long tail after an initial jump → driver recovery dominates (headroom, output swing, or recovery behavior is limiting).
• Overshoot / bounce around the hold node → parasitics and drive impedance interact (layout and isolation become first-order).

Purpose: split “hold drift” into controllable terms. Hold accuracy is a charge budget problem: leakage removes charge linearly with time, while dielectric absorption adds memory-like recovery tails.

During the usable hold window, the held value changes mainly because a net leakage current discharges (or charges) the hold capacitor. A first-order droop estimate is: ΔV ≈ I_leak · t_hold / C_hold. This makes hold design back-solvable: for a given drift limit and hold time, the maximum allowed leakage can be derived.

Where leakage comes from (dominant paths):

• Switch off-leakage: device leakage through the sampling switch when open; rises strongly with temperature.
• Buffer/input bias paths: input bias currents and ESD/protection leakage connected to the hold node.
• PCB surface leakage: contamination/humidity create parallel leakage; often dominates in high-impedance nodes.

Dielectric absorption (DA) is different from droop. DA behaves like a “memory tail”: after track-to-hold transitions and voltage steps, trapped polarization relaxes slowly and can cause rebound / slow recovery. DA can corrupt precision sampling sequences even when droop looks small over the same time window.

C_hold selection (decision-grade conclusion):

• C0G/NP0: low DA and stable behavior → preferred for precision hold and repeatable sampling sequences.
• X7R (high-K): higher volumetric efficiency but typically higher DA and stronger voltage/temperature dependence → more “memory tail” risk.

Purpose: treat pedestal/glitch as controllable engineering terms, not vague “switch noise.” The hold edge can create an instantaneous step (pedestal) plus a transient (glitch) that must be reduced or time-gated.

Two dominant mechanisms create a hold-edge step: charge injection (channel charge released when the switch turns off) and clock feedthrough (capacitive coupling from the clock gate into the hold node). Both appear as a pedestal error that scales against the hold capacitance: ΔV ≈ Q_inj / C_hold (injection-dominated), and ΔV ≈ (C_cpl/C_tot) · ΔV_clk (feedthrough-dominated).

Why “repeatable vs non-repeatable” matters:

• Repeatable pedestal (stable offset): can be calibrated or subtracted if it is consistent over PVT and signal conditions.
• Signal-dependent pedestal (varies with V_in / common-mode): harder to calibrate; structural suppression is preferred.

Common suppression toolbox (with what each one mainly attacks):

• Bottom-plate sampling: reduces charge injection into the hold node by turning off plates in a controlled order.
• Dummy switch: injects compensating charge to cancel part of Q_inj.
• Complementary switch / transmission gate: improves linearity and reduces signal-dependent artifacts.
• Differential sampling: cancels common-mode feedthrough and improves rejection of clock coupling.
• Clock shaping: reduces ΔV_clk and coupling energy (must not compromise sampling instant definition).

Purpose: set a clear threshold for when jitter is the limit. If SNR degrades mainly with input frequency (f_in), timing uncertainty is converting slope into voltage noise.

Aperture jitter (σ_t) is uncertainty in the effective sampling instant. For a changing input, that time error becomes a voltage error proportional to the signal slope. As f_in increases, slope increases, and the same σ_t produces more noise.

A common engineering estimate of the jitter-limited SNR for a sinusoidal input is: SNR_jitter ≈ −20·log10(2π·f_in·σ_t). This formula is most useful for back-solving a maximum allowable σ_t given a target SNR at f_in,max.

What tends to worsen σ_t (high-level drivers):

• Control edge noise: noise on the sampling control edge shifts threshold crossing time.
• Threshold drift: comparator/logic threshold variation translates into timing uncertainty.
• Supply disturbance: supply/ground noise modulates edge speed and thresholds.
• Comparator jitter: when the sampling moment is derived from a comparator event, its internal noise becomes σ_t.

Purpose: turn “large-step linearity” into actionable knobs. Many S/H/T/H paths look fine for small signals, but distort or miss-settle under large steps because the sampling impedance changes with input level.

A key nonlinearity driver is R_on modulation: the sampling switch on-resistance varies with input voltage, especially on single-supply systems or near the rails where available V_GS margin shrinks. When R_on depends on V_in, the effective acquisition time-constant changes with amplitude, turning a fixed time window into an amplitude-dependent residue.

Bootstrapped switches address this by keeping the switch V_GS approximately constant during tracking. A flatter V_GS produces a flatter R_on vs V_in, improving large-swing THD and reducing “some amplitudes settle worse than others.” However, bootstrap techniques introduce risks that must be checked at the architecture level.

Actionable knobs (what to change first):

• Improve headroom: avoid near-rail operation or range the signal before the sampling switch.
• Flatten R_on: bootstrapped or complementary switch structures to reduce V_in dependence.
• Strengthen drive: reduce R_driver and ensure the driver does not slew-limit on large steps.
• Reduce coupling: minimize parasitics at the hold node and isolate clock/drive return paths.

Purpose: make architecture selection concrete without leaving the S/H / T/H scope. Each choice shifts which error term dominates: node vulnerability, isolation, common-mode control, or memory/crosstalk penalties.

Architecture is not about “best”; it is about putting the dominant error term into a controllable place. A direct hold capacitor is simple, but the hold node is exposed. Adding a hold buffer isolates the node from load variability. A differential T/H structure improves common-mode behavior and can cancel some clock-related artifacts when symmetry is maintained. Multiplexed sampling trades cost/area for isolation and memory effects.

What changes between architectures (decision-grade summary):

• Direct (unbuffered) hold: simplest; hold node is fragile. Any load, leakage path, or coupling directly corrupts the held value.
• Buffered hold: isolates the hold capacitor from external loading; shifts hold accuracy toward buffer input leakage/bias and recovery behavior.
• Fully-differential T/H: improves common-mode control and can reduce apparent pedestal by symmetry; requires matched parasitics and routing.
• MUXed S/H: enables many channels; adds isolation limits, charge sharing, and “memory” between channels if the hold element is shared.

Purpose: convert “works in theory, fails on PCB” into actionable layout rules. The hold node is often high-impedance and extremely sensitive to leakage, coupling, and reference movement (ground bounce).

1) Leakage and contamination (hold drift becomes random):

• Guard ring and cleanliness: humidity, flux residue, and contamination create surface leakage that directly increases droop.
• Shortest possible high-Z routing: keep the hold node compact and shielded; avoid long exposed traces and vias.
• Material and coating decisions: if the environment is humid or variable, protective measures can make drift repeatable.

2) Coupling and loop area (pedestal/glitch grows):

• Clock isolation: the sampling clock edge is a strong aggressor. Keep it physically separated from the hold node and input network.
• Minimize the C_hold loop: place C_hold close to the switch/buffer; reduce loop area to reduce pickup and return-path injection.
• Control the return path: avoid routing digital return currents through the analog reference region near the hold node.

3) Symmetry and grounding discipline (differential cancellation only works if parasitics match):

• Symmetric differential routing: keep both halves in similar environments so common-mode coupling does not become differential error.
• Kelvin ground for sensitive references: separate high-current returns from the hold reference node.
• Local decoupling: place decoupling close to the switch driver and buffer supply pins to reduce edge-induced supply modulation.

Purpose: turn “it seems to work” into a repeatable proof flow. Each test maps to a specific error mechanism (acquisition, pedestal, droop/leakage, jitter, coupling/memory) and produces pass/fail criteria that can be re-run in production and service.

Test philosophy (keep results comparable):

• Define the sampling instant (the effective hold event). All numbers must reference the same timing point.
• Separate “mean” vs “spread”: mean pedestal can often be calibrated; random spread sets the hard limit.
• Measure trends, not only single points: droop vs time, SNR vs f_in, and step error vs time reveal root causes faster.