A State-Variable Filter (SVF) is a 2nd-order active filter that provides LP/HP/BP (and notch via HP+LP) from one core, with f0 and Q that can be tuned independently.
This guide shows how to design, tune, and verify SVFs so Q, notch depth, and distortion stay stable on real PCBs—not just in simulation.
What is a State-Variable Filter (SVF)?
One-sentence definition
A state-variable filter is a second-order active filter built around two integrators (internal “states”), which lets one signal path produce
LP, BP, and HP outputs simultaneously (and a Notch can be formed by combining HP and LP).
Why it is called “state-variable”
The two integrator outputs are internal variables that “carry memory” of the signal over time. Those internal nodes fully describe the filter’s present
behavior, so multiple responses can be derived without building separate filters.
State #1 (Integrator 1 output): commonly used as the BP response (energy centered around f0).
State #2 (Integrator 2 output): commonly used as the LP response (accumulated/averaged content).
HP is typically available at the summer (error) node, providing a complementary response.
What each output is used for (engineering view)
HP output
Removes DC/slow drift and keeps fast content; useful for de-trend, edge emphasis, and notch synthesis.
BP output
Concentrates gain around f0; ideal for detection, narrowband extraction, tone tracking, and lock-in style chains.
LP output
Limits bandwidth for anti-alias/denoise; also provides a stable node for feedback and system-level shaping.
Notch (HP + LP)
A notch can be formed by summing HP and LP; notch depth depends on amplitude/phase matching (details belong to the notch chapter).
The two-knob mental model: tune f0 and tune Q
SVF design becomes straightforward when treated as two independent controls:
f0 mainly follows the integrators’ time constants, while Q mainly follows a feedback gain/ratio.
Tune f0: change the integrator RC (resistor bank, capacitor bank, or a controlled element).
Tune Q: change a feedback coefficient (gain/ratio) while keeping the integrator RC stable.
Practical rule: keep tuning paths orthogonal; avoid “tuning Q by accident” through loading or mismatched parts.
SVF signal-flow overview (LP / BP / HP + Notch)
Key idea: the same two internal states generate consistent LP/BP/HP responses; notch is synthesized by combining HP and LP. f0 and Q are controlled by different knobs.
Why SVF: Multi-Response Outputs & Tunable Q (When to use it)
Choose SVF when any of these is true
Tunable band-pass / tunable notch is required
SVF supports clean tuning of f0 and Q, enabling narrowband extraction or interference suppression without rebuilding the entire network.
Multiple responses are needed from one signal path
LP/BP/HP are derived from the same internal states, keeping the responses aligned (same f0/Q) and reducing cross-filter mismatch.
The system needs controlled selectivity without a high-order filter
SVF is a strong choice for second-order shaping with adjustable selectivity and consistent response family—before moving to cascaded biquads.
Avoid SVF when a simpler or more integrated option is a better fit
Ultra-simple fixed LP/HP with minimal parts and power → Sallen-Key LP/HP is often a better match.
Fixed LP/HP with stable ratios and predictable Q setting → MFB LP/HP is often easier to keep consistent.
Strong electronic tunability / integrated AFE behavior → Gm-C or switched-capacitor filters are usually more appropriate.
These alternatives belong to their own topology pages; this SVF page stays focused on the SVF design and bring-up loop.
What SVF “costs” in real hardware (the hidden constraints)
High-Q sensitivity
As Q increases, finite op-amp bandwidth, phase margin, and loading errors become dominant. “Works in simulation” often fails at high Q without margin.
Notch depth is a matching problem
Notch is synthesized (HP+LP). Deep rejection requires amplitude/phase matching across temperature and aging; trim hooks may be needed for production.
Dynamic range bottlenecks
BP nodes can hit swing limits first; overload recovery can dominate settling. Headroom budgeting must be done at internal nodes, not only at the final output.
Fast decision gate (30-second checklist)
Need tunable f0 and tunable Q? SVF is a primary candidate.
Need both LP and BP simultaneously? SVF can provide both without cross-filter mismatch.
Need a notch that tracks f0? SVF can synthesize it, but plan for matching/trim.
Need the simplest fixed LP/HP? SVF is likely overkill.
SVF selection gate (use-case routing)
SVF is strongest when tunability and multiple responses are needed; simpler fixed filters or integrated tunables are better when SVF’s tuning/matching cost is unnecessary.
Canonical SVF Forms: Voltage-Mode vs “K-Controlled” SVF
How to recognize an SVF in a schematic (fast pattern check)
Two integrators in series (Integrator 1 → Integrator 2) that create the internal “states”.
A summer / error node feeding the integrator chain (the HP response often comes from this node).
Multiple outputs exposed from internal nodes: typically BP (state #1) and LP (state #2), plus an HP path.
Both forms below share the same SVF “skeleton”. The key difference is whether Q is mostly fixed by ratios or is explicitly controlled by a single parameter K.
Voltage-mode SVF (classic form)
What it is
A summer drives two integrators. The outputs are taken directly from the error node (HP) and the two states (BP/LP).
Why it is used
Straightforward implementation and predictable behavior when component ratios are stable. Good for fixed or limited-step designs.
What to watch
At high Q, finite op-amp phase margin and loading errors can distort the intended response; margin planning belongs to the non-idealities chapter.
“K-controlled” SVF (Q as an explicit knob)
What it is
The same SVF skeleton, but a single parameter K is inserted in the feedback path so Q (damping/selectivity) can be tuned without rebuilding the integrators.
Why it is used
Tunable filters prefer orthogonal controls: keep f0 tied to RC time constants while Q follows a gain/ratio knob (K).
Typical implementations
K can come from a resistor ratio, a programmable gain block, or a controlled element (digipot/VGA). Detailed tuning trade-offs belong to the tuning chapter.
SVF form recognition: classic vs K-controlled (side-by-side)
Both forms expose the same response family (HP/BP/LP, plus notch by summation). The K-controlled form makes Q an explicit tuning handle while keeping the integrator RC blocks recognizable and reusable.
Transfer Functions You Actually Need (f0, Q, Gain Mapping)
What sets the center frequency f0 (minimum actionable mapping)
In an SVF, f0 is primarily set by the two integrators’ time constants. In most practical designs, the tuning direction is “RC up → f0 down” and “RC down → f0 up”.
This mapping is sufficient to pick R/C values and to plan trim ranges.
Design action: pick capacitor values first (size, leakage, availability), then solve for resistor values that land in a noise- and drive-friendly range.
Verification hook: treat R/C tolerance as a direct f0 error term; confirm with a quick sweep around the target frequency.
What sets selectivity Q (why K is a practical knob)
Q is primarily set by a feedback coefficient (often represented as K in a K-controlled SVF). Increasing that coefficient typically increases selectivity:
K ↑ → Q ↑ (narrower passband / deeper resonance around f0).
Design action: keep Q-setting elements separate from the integrator RC elements to avoid coupling “tune Q” into “shift f0”.
Production note: plan a small trim range on K (or the ratio that creates K) if a tight Q target must hold across tolerance and temperature.
Output gain mapping (what differs between HP / BP / LP)
The three primary outputs come from different internal nodes, so their peak amplitudes and headroom limits are not identical.
A practical SVF budget treats internal nodes as first-class signals, not as “hidden implementation details”.
BP node: often shows the strongest concentration around f0; it can clip first when Q is increased.
LP/HP nodes: are complementary in shape; they may look “fine” while BP is already non-linear.
Design action: allocate swing margin at BP and at the summing node before concluding the final output has enough headroom.
Notch output: why “Notch = HP + LP” becomes a matching problem
A notch output can be synthesized by summing HP and LP. In theory this can create deep rejection at f0, but in hardware the depth is set by
amplitude and phase matching between the two paths. Small mismatches (tolerance, temperature drift, loading) directly translate into a shallower notch.
Parameter mapping: tune f0, tune Q, read outputs (LP/HP/BP/Notch)
This page only uses the minimal mapping needed for design and verification: f0 is an RC time-constant outcome, Q is a feedback-coefficient outcome (often represented by K), and notch depth is controlled by HP/LP matching.
This workflow converts these inputs into R/C/K values, op-amp requirements, and a short verification checklist.
Step 1 — Lock the response goal (what must be true on the bench)
Define pass conditions
Specify f0 tolerance, Q/BW tolerance, and the expected amplitude range where those specs must hold.
Guard latency if needed
If the chain is closed-loop or time-critical, define an upper bound on group delay or step response ringing.
Step 2 — Choose the SVF form (fixed vs independently tunable Q)
Need independent Q tuning: prefer a K-controlled SVF so Q can move without dragging f0.
Mostly fixed Q: classic voltage-mode SVF is often sufficient and straightforward to implement.
Output usage: decide early which node is the primary deliverable (BP vs LP vs notch synthesis) to avoid headroom surprises later.
Navigation only: if the need is “simplest 2nd-order LP/HP”, Sallen-Key or MFB pages are better entry points.
Step 3 — Pick capacitors first (stability, leakage, and practical tuning ranges)
Stability: capacitor value stability and matching dominate repeatability of f0 and notch alignment.
Leakage sensitivity: low-frequency or high-impedance designs magnify leakage and bias-current effects; larger C may reduce required R.
Manufacturability: choose a preferred capacitor family/value grid so tuning can be done via banks (C bank) or by solving R.
Step 4 — Solve resistors (stay in a noise- and drive-friendly range)
Directionally correct rule
After choosing C, R follows from the target f0. The practical goal is to keep R away from extremes where either thermal noise and leakage dominate (too large) or op-amp drive and distortion dominate (too small).
Two failure modes to avoid
R too high: higher in-band noise contribution, larger bias/leakage error, higher parasitic sensitivity.
R too low: heavier loading on the amplifier, higher current, earlier distortion under swing.
Step 5 — Set Q using the feedback coefficient (K network)
Q is a loop outcome: treat K (or the ratio that implements it) as a controlled design knob.
Guardband: if Q must be stable across tolerance/temperature, plan trim headroom on K rather than reworking integrator RC.
Headroom planning: higher Q raises internal BP amplitude; allocate swing margin at internal nodes, not only at the final output.
Step 6 — Non-ideal checks (turn “works on paper” into “works on PCB”)
Stability & bandwidth margin
Ensure the op-amp has sufficient GBW and phase margin for the intended Q and loading. High-Q behavior is especially sensitive to phase lag.
Large-signal integrity
Check slew-rate, output swing, recovery, and input common-mode range. Monitor the BP internal node for early compression.
Noise budget entry point
Combine resistor thermal noise, amplifier noise, and the effective bandwidth around the target response. Do not assume the final output node tells the whole story.
Deliverables (what this workflow must produce)
Component set: R/C values plus K (or ratio) for the target Q, with a tuning/trim range if required.
The flow intentionally forces decisions in the order that prevents coupling: lock the response goal, pick a form, choose C, solve R, set Q via K, then validate non-ideal margins before finalizing.
Practical Tuning: How to Tune f0 and Q Without Breaking It
Tuning f0 (three practical paths and what they trade)
R bank (stepped)
Predictable and repeatable. Watch switch parasitics and keep resistor values within a noise/drive-friendly window.
C bank (stepped)
Keeps R unchanged while moving f0. Matching and switch injection become the main risks at higher Q or higher frequency.
Digipot (convenient, but performance-limiting)
Fast for field tuning, but can degrade linearity and add resistance-dependent noise; validate distortion and bandwidth at each tuning extreme.
Tuning Q (keep it on the feedback knob, not inside the integrators)
Preferred: tune Q via K / feedback gain (ratio network, programmable gain block, VGA).
Reason: preserve orthogonality—move Q without unintentionally shifting f0 or changing the integrator noise profile.
Limit: cap the maximum Q to what the op-amp margin and internal node headroom can sustain.
Tuning rules (the sequence that prevents “tunes but breaks”)
Tune f0 first, then tune Q (center the response before sharpening it).
Watch internal BP headroom (BP often clips first even if the final output looks fine).
Re-verify after each change with a minimal sweep around f0 (extract f0, Q/BW, and check ringing/settling).
Tuning pass criteria (observable checks)
f0 window: measured f0 stays inside the target tolerance across tuning codes.
Q/BW window: extracted Q (or -3 dB BW) stays inside the target tolerance without instability.
No compression: BP node does not show early clipping or slow recovery under the maximum intended signal amplitude.
Stability behavior: step response shows controlled ringing (no sustained oscillation).
Notch tracking: notch dip moves with f0 (depth limits are addressed in the notch chapter).
The tuning strategy keeps controls orthogonal: move f0 with RC choices (banks or carefully validated digipots) and move Q with feedback gain (K). This prevents “tuning works but performance collapses”.
Non-Idealities That Kill SVF (GBW, SR, Saturation Recovery, Component Tolerance)
Fast symptom-to-root-cause map (why it simulates fine but fails on PCB)
Q won’t build / peak looks soft: insufficient GBW or phase margin under actual loading.
Response changes with amplitude: slew-rate or headroom limits causing BP compression/clipping.
Long tail after overload or switching: saturation recovery dominates settling time.
Same schematic, different behavior: tolerance coupling in ratios; mismatch shifts Q and notch alignment.
This section focuses on mechanisms + test hooks + fixes. Notch depth limits and matching strategy are handled in the notch-focused chapter.
GBW / Phase
Soft peak / f0 shift
Symptom
Q does not reach target; peak becomes blunt; f0 shifts under real load or when Q is increased.
Quick check
Small-signal sweep around f0: peak height and width vs expected.
Repeat with a different load or probe point; look for peak shape change.
Fix
Increase GBW/phase margin headroom or reduce effective loading.
Reduce target Q or reduce internal gain that amplifies phase lag sensitivity.
Pass criteria
Peak shape and f0 remain consistent across intended load and input amplitude; no “mystery Q” loss when tuning.
Slew Rate
BP clipping / “fake Q”
Symptom
Under large signals, the BP node clips or shows slope-limited edges; the measured bandwidth/peak appears to change with amplitude.
Quick check
Increase input amplitude in steps and watch the BP node waveform first.
If peak/Q changes with amplitude, treat it as a large-signal limit, not a small-signal design issue.
Fix
Reduce internal BP swing (gain distribution) or cap maximum Q.
Increase SR/headroom margin; reduce loading that forces high output current.
Pass criteria
At maximum intended amplitude, BP shows no clipping/slope limit; frequency response does not drift with amplitude.
Saturation Recovery
Long tail settling
Symptom
After overload or switching, the output takes a long time to return to steady-state; notch/BP measurements show “tails”.
Quick check
Apply a step or abrupt amplitude change; measure time-to-settle to the steady band.
Probe internal nodes; identify which node hits a rail first (BP is a common trigger).
Set adequate measurement settle time; validate recovery at worst-case stimuli.
Pass criteria
After worst-case overload, settling returns within the allowed window and stays there without “creep”.
Tolerance / Mismatch
Spread / notch drift
Symptom
Q and f0 vary across builds; notch alignment shifts. Ratio-sensitive networks amplify small component errors.
Quick check
Monte Carlo or tolerance sweep for f0 and Q distribution.
On-board statistics: compare multiple builds at the same measurement conditions.
Fix
Use matched/ratio-stable networks and stable capacitor families; keep layout symmetric.
Reserve trim hooks for K/ratios; treat notch depth as a matching-and-cal problem (next chapter).
Pass criteria
f0 and Q remain inside the required windows across tolerance and environment; notch alignment is stable enough for the target depth strategy.
Failure mechanisms: symptoms as wave thumbnails (GBW / SR / Recovery / Tolerance)
Use the thumbnail patterns as triage: soft peaks point to GBW/phase, amplitude-dependent changes point to SR/headroom, long tails point to recovery, and wide build-to-build spread points to tolerance coupling.
Practical priority order (to stop endless rework)
Prove GBW/phase margin at the intended load and tuning range.
Prove large-signal integrity by watching BP headroom and SR limits.
Prove recovery behavior with an overload/step test and set settle rules.
Only then optimize tolerance/matching for notch depth and consistency.
The diagram is qualitative by design. The correct workflow is to identify the first limiting node (often BP), then apply the lever that fixes that node without breaking tuning orthogonality.
Notch with SVF: Depth, Matching, and Temperature Drift
Key idea: deep notch is not “free” — it is a cancellation spec
SVF notch is formed by Notch = HP + LP. A deep notch only happens when amplitude and phase are well matched at the target frequency. Any mismatch or drift creates a residual tone that “fills” the notch.
Minimum conditions for cancellation (what must be true at the notch frequency)
Amplitude match
At the notch frequency, |HP| ≈ |LP|. Residual depth collapses quickly when the two paths are unbalanced.
Phase match
At the notch frequency, phase alignment must satisfy cancellation. Small phase errors become large residual tones.
Stability over environment
Matching must hold over temperature, aging, and parasitics. A “deep at room temp” notch is not a production-ready notch.
Three common notch killers (what makes a deep notch become shallow)
Layer 1Tolerance / ratio mismatch
Symptom: different boards show different notch depth and notch frequency.
Quick check: sweep multiple units; observe spread in depth and notch location.
Core issue: notch depth is dominated by ratio accuracy, not absolute values.
Layer 2Temp drift not tracking
Symptom: deep at room temp, shallow when warm or during warm-up.
Quick check: log notch depth vs temperature/time; look for systematic depth loss.
Core issue: what matters is drift tracking between HP and LP paths.
Quick check: compare probe points/grounding; check for asymmetric routing or loading.
Core issue: cancellation specs are fragile — any asymmetry becomes residual.
Practical strategies (component choice + trim hooks + production scan)
A) Component discipline
Use stable capacitor families for the integrators (NP0/C0G when applicable).
Prefer matched resistor networks for ratio-critical paths.
Keep paired parts close and in the same thermal zone to improve drift tracking.
B) Reserve trim points (for depth, not for a nominal value)
Trim R ratio to re-balance HP vs LP amplitude/phase at the notch frequency.
Digipot / resistor bank for repeatable and field-serviceable tuning.
EEPROM coefficients to store production calibration parameters (details in the calibration chapter).
C) Production scan to lock the deepest point
Coarse sweep to locate the notch neighborhood, then narrow sweep to maximize depth.
Use 2-point/3-point checks around the notch to detect drift and avoid “overfitting” to a single point.
Record notch frequency and depth as traceable fields for yield analysis and re-cal triggers.
Notch depth “matching funnel”: from ideal cancellation to real-world residual
Treat notch depth as a cancellation specification. The correct approach is to control symmetry (parts + layout) and reserve trim knobs so production can maximize depth at the real best point, not at an assumed nominal.
Pass criteria (production-friendly, no magic numbers)
Notch depth remains usable across temperature and warm-up; depth does not collapse under normal environmental change.
Notch frequency does not drift beyond the system’s tracking or re-cal range.
Depth maximization is repeatable across units using the reserved trim hooks and sweep procedure.
Differential / FDA-Based SVF (for ADC Front-Ends)
When SVF should be differential
ADC differential inputs: easier headroom planning and lower distortion for a given dynamic range.
Noise/EMI environments: controlled common-mode improves robustness for real cables and real grounds.
High linearity targets: symmetric signal handling reduces even-order distortion and CM coupling.
This section focuses on how SVF lands in a differential chain, not a general survey of differential filter topologies.
Two practical implementations
Option ASE→Diff (FDA) → SVF
FDA sets VOCM and provides differential drive authority.
SVF operates in a controlled differential domain with symmetric loading.
Best when the source is single-ended and ADC requires strict input common-mode.
Option BDirect differential SVF
SVF is built as a symmetric differential structure (summer + integrators mirrored).
Common-mode control must be explicit (FDA, CM servo, or a defined VOCM reference scheme).
Best when the full chain is differential and symmetry can be maintained end-to-end.
Key constraints checklist (what breaks differential SVF in real ADC front-ends)
VOCM compatibility
FDA/VOCM must land inside the ADC input common-mode window across tuning extremes and temperature.
Headroom and internal swing
Differential swing plus common-mode motion must not push any internal node into compression or rail recovery (BP often fails first).
Symmetry and matching
Pair critical R/C elements and keep the two halves physically symmetric; asymmetry becomes CM leakage and distortion.
ADC input load interaction
The ADC presents sampling capacitance and transient loading. Define the isolation strategy (small series R/RC/buffer) so tuning does not destabilize the chain.
Layout rules (differential SVF is a symmetry game)
Route differential pairs with matched environment; keep return paths consistent.
Place paired components close and oriented consistently to reduce thermal gradients.
Keep VOCM routing clean and quiet; prevent digital noise from modulating common-mode.
Make test points symmetric; otherwise measurements create false imbalance.
Avoid asymmetric stubs and probe loading near high-impedance nodes.
The chain highlights three non-negotiables: VOCM alignment, symmetry/matching, and ADC sampling load interaction. Treat them as first-class requirements before tuning f0/Q.
Verification hooks (what to test in the correct order)
Small-signal sweep: confirm target response and symmetry (OUTP/OUTN balance).
Large-signal linearity: validate THD/SFDR at tuning extremes and intended loads.
Common-mode behavior: confirm VOCM stability and low CM leakage into differential output.
ADC integration: repeat tests with the real ADC load; confirm no “only fails when ADC is connected” behavior.
Copyable application recipes (only what Sallen-Key owns)
This section provides reusable chain templates for where a 2nd-order Sallen-Key LP/HP is the right tool:
gentle anti-alias roll-off, bandwidth shaping for denoise, and low-to-mid Q shaping for audio/measurement.
When targets require steeper roll-off or strict group delay, link out to cascaded biquads or phase equalizers.
Each chain must be validated with the real source impedance and the real ADC (kickback + sampling window).
H2-12. IC Selection Logic (Op-amp choice fields + inquiry checklist)
Convert datasheet items into measurable risk control
Sallen-Key success is not “pick a big GBW.” Selection must prove stability and settling under the real load (ADC kickback),
then confirm headroom and distortion under the required swing. Use the table and inquiry checklist below to force evidence under your conditions.
A) Selection table (Spec field → Why → Failure signature → Quick check → Mitigation)
Why: rail-to-rail does not guarantee linearity or fast recovery close to rails with real loads.
Failure signature: waveform “looks okay” but THD/SFDR is poor; recovery is slow after saturation.
Quick check: test near-rail operation at required load; include the worst-case output current corner.
Mitigation: keep headroom; select parts with distortion specs near rails; or change supply strategy.
B) Vendor questions (copy/paste inquiry checklist)
Request evidence under the actual conditions. Do not accept “typical no-load curves” for a Sallen-Key driving an ADC.
Inquiry template (fill blanks)
Application: Sallen-Key LP/HP
Supply: ____ V (single/dual), bias/Vcm: ____
Target fc: ____ , target Q: ____ , gain K: ____
Signal: amplitude ____ , frequency range ____
Load model:
– Rload: ____ ohm
– Cload: ____ pF (plus ADC input network)
– ADC sampling: Cin ____ , switch/kickback present (yes/no)
Settling requirement:
– acquisition window T: ____ us
– required error: < X (define LSB or %FS)
Please provide:
1) Stability / phase margin evidence under the above Cload/ADC model
2) Step settling to < X within T under the above load
3) THD/SFDR at the above swing + frequency under the above load
4) Output swing/current capability at the above load and near-rail behavior notes
C) Decision flow (Spec → Risk → Action)
Prove stability under real load: ADC network connected, worst-case Cload corner included.
Prove settling to the window: |error| < X by time T inside the acquisition window.
Prove headroom + distortion: THD/SFDR at the required swing and frequency under final loading.
If any step fails: take the minimal fix first (Riso / ratio / headroom), then buffer, then change topology.
These FAQs capture SVF-specific long-tail issues without expanding the main content. Each answer follows the same 4-line, testable structure.
Why does Q drop when I tune the center frequency?
Likely cause: The f0 tuning path also changes loop gain/ratio, or op-amp loop behavior shifts with frequency and reduces effective Q.
Quick check: Hold the Q-control network constant and tune only f0; then hold f0 and tune only Q—compare the two sweeps.
Fix: Decouple tuning paths: use R/C banks for f0 and keep Q on a separate K/feedback ratio (digipot only in K path: TPL0501-100, AD5245, MCP4661).
Pass criteria: Across the full tuning range, repeated sweeps return to the same Q window at the same settings (no “Q collapse” when f0 moves).
Why is the notch depth much shallower on the PCB than in simulation?
Likely cause: HP/LP mismatch (tolerance, parasitics, thermal gradient, or loading at the sum node) prevents true cancellation.
Quick check: Measure HP and LP around the notch region (same probe/cable path) and check whether depth changes when the load/probe changes.
Fix: Enforce symmetry + matching (same thermal zone, mirrored routing) and add trim hooks (digipot TPL0501-100 or MCP4661 + EEPROM 24LC256 to store trim state).
Pass criteria: Notch depth remains near-target after connecting the final load and after swapping probe setups (depth does not “fill in”).
SVF works at small signal but distorts badly at higher amplitude—why?
Likely cause: Slew-rate/headroom limits cause compression or clipping at internal nodes before the “external” output looks obviously wrong.
Quick check: Run an amplitude sweep at fixed f0/Q and watch BP + integrator outputs; distortion will rise sharply near the first node that approaches the rails.
Fix: Reduce peak node swing (lower Q or redistribute gain) or raise headroom; choose an op-amp with adequate SR/linearity (examples: TI OPA1656, ADI ADA4898-2).
Pass criteria: At maximum specified input amplitude, the waveform shows no clipping and measured distortion remains within the system budget.
Why does the BP output clip first even when LP/HP look fine?
Likely cause: BP is typically the highest-energy/highest-peak node (Q magnifies it), so it hits headroom first while LP/HP still appear acceptable.
Quick check: Probe BP and both integrator outputs and identify which node approaches the rails first at the failing amplitude.
Fix: Lower BP node level (move gain after the SVF, reduce Q, or increase supply/headroom); if needed use a more linear amplifier (OPA1656 / ADA4898-2 as starting points).
Pass criteria: Under worst-case tuning, BP remains linear at the required amplitude and no node exhibits early clipping.
How much op-amp GBW margin do I need for a target Q?
Likely cause: Insufficient loop gain/phase margin at the operating frequency reduces effective Q and warps the response.
Quick check: Repeat the same design with a significantly higher-GBW amplifier; if Q “magically returns,” GBW/phase is the bottleneck.
Fix: Use a conservative GBW starting point on the order of “tens of times (f0×Q)” and confirm with sweep + large-signal checks (example amplifiers to evaluate: OPA1656, OPA1612, ADA4898-2).
Pass criteria: Q and peak shape stay stable across tuning extremes and do not collapse when the final load is attached.
Why does probing the integrator node change the response?
Likely cause: Probe capacitance/leakage loads a high-impedance node and changes the integrator time constant and damping (Q/f0 shift).
Quick check: Compare results using an active probe vs a standard passive probe, or buffer the node and re-measure.
Fix: Design measurement-friendly hooks: add a unity buffer footprint (example: OPA320) or expose a buffered test pad via analog switch (TS5A23157 / ADG1419).
Pass criteria: f0/Q/notch results remain consistent across probe types and the “probe state” no longer determines the outcome.
Why does tuning with a digipot increase noise and shift f0?
Likely cause: Digipots add resistance noise, code-dependent R variation, and temperature behavior; changing R directly shifts the time constant (f0 moves).
Quick check: Sweep digipot codes and log (noise floor, f0); compare against a fixed precision resistor network at the same nominal value.
Fix: Use digipot for small-range K/Q trimming rather than the main integrator R; store selected codes in EEPROM (TPL0501-100 / AD5245 / MCP4661 + 24LC256).
Pass criteria: At any stored tuning state, repeated measurements return to the same f0/Q and noise stays within the budget.
Why does the notch center drift with temperature even with “1% parts”?
Likely cause: “1%” controls initial value, not matched tempco; HP and LP drift differently (plus PCB thermal gradients), shifting cancellation frequency.
Quick check: Temperature sweep and log both notch depth and notch frequency; check whether drift tracks board gradients or tuning states.
Fix: Keep ratio parts co-located and thermally coupled; add trim and store per-unit calibration (digipot MCP4661 + EEPROM 24LC256 as a fixture-friendly approach).
Pass criteria: Notch frequency and depth stay inside the allowed drift window across the specified temperature range.
How do I quickly verify Q without a full network analyzer?
Likely cause: Without a VNA, Q estimation often fails due to inconsistent stimulus and probe/load sensitivity rather than math.
Quick check: Measure BP peak at f0 and collect a few frequency points around it to find the two -3 dB points (repeat with the same fixture).
Fix: Use the -3 dB bandwidth method as the default rule; for portable fixtures, a DDS source (example: AD9833) can generate repeatable stepped tones.
Pass criteria: Q derived from repeated point-measurements matches within repeatability limits and agrees with a sweep when available.
Why does the filter take long to recover after overload?
Likely cause: An internal node saturates; overload recovery plus integrator charge re-balancing creates long tails (BP/notch shows it first).
Quick check: Apply a short overdrive pulse and measure recovery time to normal sweep behavior; identify which node clips first.
Fix: Prevent saturation (reduce peak swing, adjust gain/Q, increase supply), and add a diagnostic bypass path using TS5A23157/ADG1419 to isolate “SVF vs downstream.”
Pass criteria: After the specified overload event, the filter returns to nominal f0/Q/notch behavior within the allowed recovery time.
Can I sum HP+LP anywhere to make a notch, or must it be buffered?
Likely cause: Summing at an uncontrolled impedance point adds loading and phase error, which directly fills the notch.
Quick check: Compare notch depth when summing through a buffered summer vs a direct wire-sum; also compare with/without the final load.
Fix: Sum HP+LP in a controlled summing stage (example buffer/summer op-amp: OPA320) and keep both paths symmetrically loaded; use an analog switch (TS5A23157) if multiple sum points are needed for debug.
Pass criteria: Notch depth remains stable across expected load conditions and does not vary strongly with probing.
How do I keep common-mode stable in a pseudo-differential SVF?
Likely cause: Common-mode is weakly defined; asymmetric loading and bias/VOCM impedance let CM wander, raising distortion and drifting the apparent response.
Quick check: Measure VOCM while tuning f0/Q and during large-signal tests; compare behavior under symmetric vs asymmetric loads.
Fix: Use an FDA to lock CM and drive differential loads (starting points: THS4551, ADA4940-1) and keep routing/component placement symmetric around the differential pair.
Pass criteria: VOCM stays within the target window across tuning and amplitude, and distortion/noise does not jump when the final load is attached.
