ADC Clocking & Jitter: Phase Noise, Aperture Jitter and Budgets
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This page explains how clocking and jitter set the real SNR and ENOB limits of an ADC system, then walks through budgeting jitter, choosing clock sources, PLLs, and distribution topologies for different applications, and turning those choices into practical checklists and selection criteria without touching algorithm or application-level details.
What this page solves
This page focuses on the clocking and jitter side of high-speed and high-resolution ADC systems. It targets hardware engineers, system architects, and FPGA designers who need to know how clean the sampling clock must be and how to allocate jitter budget across the clock tree to meet target SNR and ENOB.
Typical situations include:
- Measured SNR is several dB below the datasheet, and the suspected root cause is clock jitter.
- Multi-channel or time-interleaved ADCs show ENOB variation and phase mismatch, raising doubts about the clock tree quality.
- There is uncertainty whether a simple XO plus buffer is enough, or whether a dedicated low-jitter PLL or clock generator is required.
What this page will help with
- Understand how clock jitter and aperture jitter limit ADC SNR and ENOB across input frequency.
- Estimate how much jitter a given resolution, sampling rate, and input frequency can tolerate, and derive a practical jitter budget.
- Review typical clock tree architectures from XO or VCXO through PLL or clock generator and fanout buffers into one or more ADCs.
- Translate phase-noise and jitter specifications into actionable design decisions for converter clocking.
What this page does not cover
- Reference and buffering details such as reference noise, load transients, and reference amplifiers.
- Analog front-end and anti-alias filter design, including drivers, RC/LC filters, stability, and distortion.
- PCB layout techniques for clocks such as routing, impedance, return paths, stack-up, and grounding.
- JESD204 or LVDS link eye diagrams, equalization, CDR, and protocol-level questions.
- System-level time synchronization and timestamping based on PTP or distributed timebases.
Key clock & jitter concepts
This section defines the clocking and jitter terms that appear throughout the rest of the page. The goal is to create a clean vocabulary for ADC clock design, without going into full mathematical derivations yet.
Clock jitter: edge timing uncertainty
Clock jitter is the short-term variation of the clock edge from its ideal position in time. It can be expressed as cycle-to-cycle jitter or edge jitter, but for ADC performance the most useful quantity is the rms jitter of the sampling edge, because it directly relates to SNR degradation.
Peak-to-peak jitter is sometimes quoted but depends heavily on observation time and statistics. For converter design, rms jitter is the primary figure of merit when budgeting jitter and comparing clock sources.
Aperture jitter: uncertainty inside the ADC
Aperture jitter is the uncertainty of the actual sampling instant inside the ADC itself. Even with a perfect external clock, switch timing, sampling capacitor network, and internal circuitry introduce a residual random delay. This jitter is usually specified in the datasheet as an rms value and sets a hard floor on the best achievable SNR at high input frequencies.
Phase noise and integration bandwidth
Oscillator and PLL datasheets often specify phase noise as L(f), the single-sideband noise around the carrier versus offset frequency. To convert phase noise into rms jitter, phase noise is integrated over a defined offset-frequency band and then translated into time-domain jitter. The chosen integration bandwidth strongly affects the resulting jitter number, so specifications from different sources are only comparable when the bandwidth is consistent.
Random jitter vs deterministic jitter
Random jitter is unbounded, noise-like timing variation that typically follows a Gaussian distribution and is caused by thermal and device noise. Deterministic jitter is bounded and repeatable, often stemming from power-supply ripple, digital switching noise, or spurs in a PLL. Jitter budgets for ADCs usually focus on the random component that translates directly into broadband SNR loss, while many deterministic components are handled in layout and power integrity disciplines.
SNR sensitivity vs input frequency
For a given rms jitter, SNR loss becomes more severe as input frequency increases. The instantaneous slope of the input signal is higher at high frequency, so the same timing error translates into a larger voltage error at the sampling instant. As a result, low-frequency precision applications can tolerate significantly more clock jitter than RF or near-Nyquist sampling applications.
Jitter → SNR/ENOB budgets
This section explains how sampling jitter limits SNR and ENOB, and how to convert a resolution or SNR target into a practical jitter budget for the complete clock path. The focus is on usable formulas and engineering-level examples instead of full mathematical derivations.
Relationship between jitter and SNR
For a sinusoidal input, the SNR limit caused purely by sampling jitter can be approximated by SNR_jitter ≈ −20·log10(2π·f_in·t_jitter,rms). Here f_in is the highest significant input frequency component and t_jitter,rms is the total rms sampling jitter. This expression shows that, for a fixed jitter, SNR falls by roughly 20 dB every time the input frequency increases by one decade.
A target ENOB can be related to SNR through ENOB ≈ (SNR_total − 1.76) / 6.02. When jitter dominates the noise, SNR_total is effectively SNR_jitter and the achievable ENOB is set by the total rms jitter and the input frequency.
Back-calculating maximum allowed jitter
To estimate the maximum allowed jitter, the jitter–SNR relation can be rearranged to t_jitter,max ≈ 1 / (2π·f_in·10^(SNR_target/20)). The design flow is: define the highest relevant input frequency band, choose the target SNR or ENOB based on system requirements, compute the maximum jitter that keeps SNR_jitter above this target, and then apply a safety margin so that the actual clock solution has some headroom.
Before deriving a jitter budget, the theoretical SNR of the ADC itself should be checked from the datasheet. If the converter’s quantization and internal noise already limit SNR below the jitter limit, improving clock jitter will not increase system ENOB.
Splitting the jitter budget
The total sampling jitter can be viewed as the rms combination of several contributions: t_j,total ≈ √(t_j,clk² + t_j,aperture² + t_j,dist²). Here t_j,clk comes from the external clock source and PLL chain, t_j,aperture is the intrinsic aperture jitter of the ADC itself, and t_j,dist represents extra jitter added by distribution elements such as fanout buffers, gating, and noisy routing.
A practical jitter budget often allocates portions of the allowed t_j,total to each contributor. For example, if t_j,total should be no higher than 150 fs rms, the budget might reserve about half for the clock source and PLL, a significant share for the ADC aperture jitter as given in the datasheet, and the remainder for distribution and routing. This allocation guides both component selection and layout effort.
Example 1 – 14-bit, 250 MSPS IF-sampling
Consider a 14-bit, 250 MSPS converter that captures an IF band around 70–100 MHz and aims for an effective resolution around 11.5–12 bits, corresponding to an SNR target in the low 70 dB range. Plugging this SNR target and the IF frequency into the jitter–SNR formula leads to a maximum total jitter in the order of a few hundred femtoseconds. After applying margin, the practical design target typically falls into the sub-200 fs range, so the clock source and PLL must be chosen carefully.
Example 2 – RF-sampling at 1 GHz
For an RF-sampling ADC that digitizes a 1 GHz carrier with a multi-GSPS sampling rate and targets around 10–11 bits of ENOB, the same formula yields a much tighter jitter limit, often in the tens of femtoseconds or below. In this regime, jitter tends to be the dominant constraint on SNR, and high-performance oscillators, PLLs, and jitter cleaners are almost always required.
Example 3 – 18-bit, 1 MSPS precision DC
For an 18-bit precision converter running at about 1 MSPS with an effective signal bandwidth in the tens of kilohertz, even a high SNR target above 100 dB still allows jitter in the picosecond range. In this type of design, SNR is usually limited by front-end noise, reference stability, and drift rather than by clock jitter, so ultra-low-jitter clocking brings much less benefit than careful analog design.
Clock source architectures
This section compares common clock-source building blocks and shows how to combine them into practical architectures for single-ADC, multi-ADC, and time-interleaved converter systems. The focus is on frequency planning and jitter performance rather than on specific part numbers or system-wide synchronisation algorithms.
Oscillators and VCXOs
Crystal oscillators and temperature-compensated oscillators provide a fixed-frequency, low-noise reference with good stability. VCXOs add fine frequency tuning capability while retaining very good phase noise. These devices are well suited as direct clock sources for lower-speed converters or as reference inputs to PLLs, clock generators, and jitter cleaners.
PLLs and clock generators
PLL-based clock generators synthesize multiple output frequencies from a single reference, supporting programmable sampling rates and several synchronized outputs. They introduce additional phase noise and spurious tones, so the key specifications are output rms jitter over the specified integration band, VCO phase noise, loop bandwidth, and spur performance. For mid-to-high-speed ADCs, a clean PLL or clock generator often forms the core of the clock tree.
Jitter cleaners and clock conditioners
Jitter cleaners and clock conditioners are specialised PLL devices designed to remove jitter from a noisy reference and regenerate a low-jitter sampling clock. They are widely used in RF-sampling, high-speed communication, and multi-card systems where the available reference is not clean enough for direct use with ADCs. These devices can significantly reduce clock jitter at the cost of higher complexity, power, and component count.
Typical clock-tree structures
A simple clock tree uses a low-noise XO driving a buffer that feeds a single ADC. This fits lower-speed and modest-ENOB applications where the jitter budget is relaxed and only one converter or a small number of channels is present.
A more flexible architecture uses an XO or VCXO to feed a PLL or clock generator, which then drives an output buffer and the ADC. This arrangement supports programmable sampling rates and multiple output clocks for ADCs and digital logic, with jitter performance determined mainly by the clock generator.
The most demanding systems combine a high-quality oscillator, a jitter cleaner, and a multi-output fanout buffer to feed several ADCs or interleaved channels. This structure is common in RF-sampling converters, dense multi-channel cards, and time-interleaved ADCs where very low jitter and matched outputs are mandatory.
Single-ADC, multi-ADC, and TI-ADC needs
A single ADC typically requires only one low-jitter clock, so a simple oscillator-plus-buffer solution is often enough when frequencies and resolution are moderate. Multi-ADC systems, such as simultaneous-sampling or multi-board capture cards, require several phase-aligned outputs derived from a shared reference, pushing designs toward multi-output PLLs or jitter cleaners with fanout buffers. Time-interleaved ADCs need tightly related clocks across subchannels to avoid spurs and mismatch artefacts, which further tightens jitter and skew requirements and often motivates higher-end clocking solutions.
When a dedicated clock chip is required
A simple XO plus buffer is usually sufficient for low-to-mid-speed precision ADCs where input frequencies are relatively low, the jitter budget is generous, and only a small number of channels are present. As sampling rates and input frequencies increase, or when several converters require aligned clocking, a PLL or clock generator becomes necessary to provide extra outputs and programmable sampling rates. RF-sampling converters, multi-board timing schemes, and systems that must derive the ADC clock from a noisy system reference generally require a jitter cleaner and high-performance fanout device to meet tight jitter budgets.
Clock distribution topologies
This section focuses on topology-level clock distribution for ADC systems: how clock signals are routed from the source to one or more converters using point-to-point paths, star fanout, and daisy-chain structures. The goal is to keep clock paths clean and predictable in terms of jitter and skew, without diving into PCB-level details such as impedance, via design, or stack-up choices.
Single-board, single-ADC clocking
With a single ADC on a board, a simple point-to-point connection from the clock source or PLL output to the converter clock input is usually sufficient. The path is short, there are no intermediate buffers, and additive jitter is minimal. This topology suits lower channel counts and many mid-speed designs where a single high-quality clock is enough.
Single-board, multiple ADCs: star vs daisy chain
When several converters must capture signals synchronously, the choice of clock-distribution topology has a direct impact on clock skew and jitter. A star distribution uses a dedicated fanout buffer with multiple matched outputs, each driving one ADC input. This structure offers the best control of relative delay and skew, and the additional jitter is dominated by the fanout buffer’s additive jitter specification.
A daisy-chain or buffered-chain topology routes the clock through a series of devices, often reusing clock outputs from ADCs or intermediate buffers. While routing can be simpler, delay and skew accumulate along the chain and each stage adds jitter. This approach is better suited to moderate speeds and systems where channel-to-channel timing alignment is less critical, and it is less attractive where high ENOB and tight synchronisation are required.
Clocking for time-interleaved ADCs
Time-interleaved ADCs rely on several sub-ADCs sampling at precise phase offsets. The clock distribution network must provide clocks with fixed phase relationships and closely matched jitter to each subchannel. In highly integrated TI-ADC devices these phases are often generated internally from a single low-jitter input clock, while discrete implementations may use multi-phase PLLs or dividers. Correction algorithms for gain, offset, and timing mismatch are handled elsewhere; this section focuses on delivering phase-consistent clock paths to all interleaved channels.
Multi-board systems with a shared reference
In chassis-based or multi-card systems, a common reference clock is usually distributed to each board, where local PLLs or jitter cleaners generate the required sampling clocks. This approach keeps all converters frequency-locked to the same reference while allowing each board to select its own sampling rate and clock tree structure. Details such as backplane routing, connector effects, and higher-level time synchronisation schemes are handled in dedicated synchronisation and PCB layout topics.
Role of clock fanout buffers
Clock fanout buffers provide multiple low-skew outputs and isolate the primary clock source from varying ADC input loads. They add some amount of jitter, but they also enable clean star topologies and scalable multi-ADC clock trees. In high-performance systems, the additive jitter and output-to-output skew of the fanout device should be included explicitly in the jitter budget and used as a key selection parameter. Layout-specific techniques such as impedance control, length matching, and return-path management are covered in the dedicated “Clocking & PCB Layout” page.
Inside the ADC: aperture jitter & sampling network
This section looks inside the converter and explains how internal aperture jitter and the sampling network influence SNR, even when the external clock is very clean. Understanding these datasheet parameters helps set realistic expectations for jitter budgets and clarifies which performance limits come from the ADC architecture itself.
Datasheet jitter parameters
High-speed ADC datasheets often specify aperture jitter t_j (aperture jitter) as an rms timing uncertainty of the sampling instant inside the converter. Some devices also provide a jitter-limited SNR at a given input frequency, indicating the best achievable performance when jitter is the dominant limitation. These parameters define a floor that cannot be overcome by improving only the external clock.
When t_j,aperture is given, it should be included directly in the total jitter budget. When only jitter-limited SNR is specified, an equivalent aperture jitter value can be inferred using the jitter–SNR relation and used as a fixed contribution in budget calculations.
Sampling switch, capacitor network, and bandwidth
The sampling network of an ADC typically consists of a switch that connects the input signal to a sampling capacitor for a short acquisition window. Device noise, finite switch transition time, and internal bandwidth limitations create uncertainty in the exact time at which the sampled value is captured. Large capacitance and limited drive strength can extend the settling time inside this window, effectively increasing the sensitivity of the sampled voltage to small timing shifts and contributing to aperture jitter.
High-frequency and large-swing behaviour
At low input frequencies and small signal amplitudes, the waveform slope around the sampling instant is shallow, so a given amount of aperture jitter produces only a small voltage error. At higher frequencies and large signal swings, the slope becomes much steeper and the same timing uncertainty translates into larger voltage errors. This effect is reflected in datasheet curves where SNR decreases as input frequency increases, even when the external clock quality remains constant.
Combining external clock jitter and aperture jitter
The effective sampling jitter is the rms combination of external clock jitter and the converter’s own aperture jitter. A practical model treats total jitter as t_j,total ≈ √(t_j,clk² + t_j,aperture² + t_j,dist²), where t_j,clk represents jitter from the clock source and distribution network, t_j,aperture comes from the internal sampling network, and t_j,dist accounts for additional jitter in buffers or routing. Once a total jitter target has been derived from SNR goals, the allowable external clock jitter can be estimated by subtracting the aperture and distribution contributions in rms.
When the ADC’s aperture jitter already dominates the jitter budget, further improvements to the external clock produce limited SNR gains. In this situation, system performance is better improved by choosing a converter with lower aperture jitter or by relaxing the required input frequency range rather than by chasing even lower clock jitter.
Application patterns vs jitter requirements
Different application classes impose very different jitter requirements on the ADC clock. This section compares RF and high-speed communication, IF and radar or instrumentation, motor and power control, and DC precision measurement from a jitter sensitivity perspective, without entering into algorithm details such as modulation schemes, FOC control, or imaging processing.
RF and high-speed communications – tight jitter
Wideband RF receivers, direct RF-sampling software-defined radios, and very high-frequency spectrum instruments operate with input frequencies in the hundreds of megahertz to multi-gigahertz range while targeting around 10–12 bits of effective resolution. In this regime, total sampling jitter often becomes the dominant noise source and directly limits achievable ENOB. Jitter requirements are in the tight range, frequently tens of femtoseconds or below, and clock architectures usually rely on low phase-noise oscillators, high-performance PLLs, jitter cleaners, and low-jitter fanout devices.
IF, radar, and instrumentation – mid–tight jitter
Intermediate-frequency receivers, radar IF stages, and general-purpose test instruments often digitise signals in the tens to a few hundreds of megahertz range. These systems still demand high SNR and good ENOB, so jitter must remain low, typically in the sub-200 fs to sub-100 fs range, but requirements are less extreme than in direct RF sampling. Selecting a suitable IF band can relax jitter constraints compared with digitising the original RF carrier, trading some analog complexity for a more achievable clock design.
Motor control and power control – mid / relaxed jitter
Motor drives, field-oriented control, and switched-mode power supplies measure currents and voltages whose fundamental content is typically in the hundreds of hertz to tens of kilohertz range, with sampling rates from tens of kSPS up to a few MSPS. In these applications the clock jitter requirement is moderate: well-controlled picosecond-level jitter is usually sufficient, and performance is more strongly driven by ADC resolution, conversion latency, front-end amplifier noise, and loop design. Jitter matters primarily for its influence on sampling instant accuracy and loop phase margin, not as the main SNR limiter.
DC precision measurement – relaxed jitter
Precision DC and low-frequency measurements such as weighing systems, precision voltage or current measurement, thermocouple readout, and slow process monitoring operate with effective signal bandwidths in the hertz to low kilohertz range. High-resolution converters in this space are usually limited by sensor noise, reference noise, 0.1–10 Hz noise, and long-term drift instead of clock jitter. Reasonable, well-designed clocking easily meets jitter needs, and further reducing jitter brings little benefit compared with improving the analog front end and thermal management.
From a system-design perspective, RF and wideband communication applications lie at the tight end of the jitter scale, IF and radar or instrumentation occupy a mid–tight band, motor and power control fall into mid or relaxed jitter levels, and DC precision measurement sits in the most relaxed range where jitter is rarely the primary constraint.
Engineering checklist – clocking & jitter
This section turns the previous concepts into a practical checklist for schematic reviews and design evaluations. Each item provides a reminder to confirm specifications, calculate jitter budgets, validate clock-source and PLL choices, review distribution topology, account for ADC internal jitter, and plan laboratory verification.
Specifications and jitter budget
• Signal bandwidth and maximum input frequency are clearly defined for each operating mode.
• Target SNR or ENOB is specified at the key input frequencies of interest.
• The jitter–SNR relation is used to compute a maximum allowed total jitter for each band.
• Adequate design margin is reserved so that practical clock solutions can meet the jitter budget.
Clock source and PLL
• Oscillator or reference source phase-noise performance supports the jitter targets.
• PLL or clock-generator configuration (multipliers, dividers, loop bandwidth) is checked for acceptable output jitter and spur levels.
• Calculated or specified t_j,clk from the clock chain fits inside the overall jitter budget.
• Jitter cleaners are used where necessary to recover a low-jitter clock from noisy references, while unnecessary PLL stages are avoided.
Distribution topology and fanout
• Clock-tree diagrams identify whether point-to-point, star, or daisy-chain topologies are used for each converter group.
• For multi-ADC designs, star distribution with a low-jitter fanout buffer is considered where tight skew is required.
• Additive jitter and output-to-output skew of each fanout stage are included in the jitter and timing budgets.
• For daisy-chained or multi-board structures, jitter accumulation and skew growth along the chain are evaluated and documented.
ADC internal jitter
• Aperture jitter t_j,aperture is extracted from the ADC datasheet or inferred from jitter-limited SNR specifications.
• Total jitter is estimated using an rms combination of clock, aperture, and distribution jitter contributions.
• The remaining jitter budget for the external clock path is derived after accounting for ADC internal limitations.
• For multi-channel or time-interleaved converters, internal jitter and channel-to-channel timing behaviour are reviewed for their impact on SFDR and spur levels.
Application modes
• RF and wideband communication modes are checked against a tight jitter budget compatible with the highest ENOB targets.
• IF, radar, and instrumentation modes are verified using jitter limits appropriate to their IF bands and resolution requirements.
• Motor and power-control modes confirm that clock quality does not compromise loop timing or stability, while recognising that jitter is not usually the main SNR constraint.
• DC precision modes are assessed to ensure jitter is negligible compared with noise and drift, avoiding unnecessary overdesign of clock circuitry.
Laboratory validation
• Test points are reserved to observe key clock nodes and, where appropriate, to measure phase noise or integrated jitter directly.
• Measurement plans include SNR and ENOB versus input frequency to confirm that jitter-related limits match design expectations.
• Clock and jitter test procedures are documented so that production and maintenance teams can repeat essential checks when systems are built or updated.
IC selection logic – clock sources, PLLs, and buffers
This section focuses on selecting clock-related ICs for ADC systems: oscillators, PLL and clock generators, jitter cleaners, and fanout buffers. The goal is to translate target sampling rate, SNR or ENOB, and required jitter into concrete selection criteria and enquiry fields for vendors. ADC device selection itself is handled on separate pages and is outside the scope of this section.
From target fs and SNR to required jitter
Once the signal bandwidth, maximum input frequency, and target SNR or ENOB are defined, the jitter–SNR relation is used to derive a maximum allowed total rms jitter for each key frequency band. This total jitter budget is then split between the external clock path and the ADC itself: clock source and PLL jitter, distribution and fanout additive jitter, and datasheet aperture jitter are combined in rms. The remaining headroom for the clock source and PLL defines the minimum phase-noise and jitter performance needed from each clocking IC.
Oscillators (XO / TCXO / VCXO) – key questions and examples
For crystal-based oscillators the enquiry should cover output frequency, frequency stability over temperature, and phase-noise performance at key offset frequencies. Important parameters include guaranteed frequency range, long-term stability in ppm, phase-noise values at offsets such as 10 kHz, 100 kHz, and 1 MHz, and any datasheet rms jitter numbers specified over a defined integration bandwidth. Output standard (LVCMOS, LVDS, LVPECL, CML), supply voltage, and start-up time also need to match the ADC clock input and power-tree constraints.
Fixed-frequency low-jitter XOs such as the Crystek CCHD-575 family are commonly used as clean references for high-speed converters and test equipment. Programmable low-jitter oscillators and VCXOs such as SiLabs or Skyworks Si570 and Si571 offer wide programmable output ranges with good jitter, and are often chosen for evaluation boards and communication systems that require flexible frequency plans.
PLL, clock generator, and jitter cleaner selection
For PLLs, clock generators, and jitter cleaners, key questions include the supported input reference range, available output frequency range, and the number and type of outputs. Datasheets should provide integrated rms jitter for each output in a specified integration band and detailed phase-noise plots; these are used to verify that the resulting tj,clk fits inside the jitter budget at the highest input frequencies. Configuration options such as multiplier and divider settings, loop-bandwidth flexibility, and spur performance are also important when designing frequency plans.
Many high-performance ADC boards use converter-focused clocking ICs such as Analog Devices AD9528 clock generators or Texas Instruments LMK04828 jitter cleaners, which combine low-jitter device clocks with integrated SYSREF support for JESD204B/C subclasses. Generic jitter attenuators and clock generators such as the Skyworks or SiLabs Si5345 are used where multiple unrelated clock domains must be generated from a noisy reference. Selection should be driven by required jitter, number of outputs, JESD or SerDes needs, and acceptable complexity.
Fanout buffer and clock buffer selection
Clock fanout buffers extend a clean clock source to multiple loads and enable star topologies. When selecting these devices, the most important parameters are additive jitter in femtoseconds rms, maximum operating frequency, and output-to-output skew. The buffer must support the required input and output standards, such as LVDS, LVPECL, CML, or HCSL, and provide sufficient drive strength and edge rates without introducing unnecessary overshoot or ringing.
Devices such as the Analog Devices ADCLK948 demonstrate the type of fanout buffer used in high-speed converter systems, offering multiple low-jitter outputs with tight skew and support for gigahertz clock rates. Different family members provide variants with other output standards or channel counts to match specific ADC and FPGA combinations. In all cases, additive jitter and skew from each buffer stage must be included in the jitter and timing budgets established earlier.
Vendor enquiry and selection checklist
When contacting distributors or device vendors for clocking ICs, enquiry fields should at least include target sampling rate and input frequency band, required SNR or ENOB, and the resulting maximum allowed total jitter. For oscillators, list desired output frequency, stability over temperature, required phase-noise or jitter level, output format, supply voltage, and operating temperature range. For PLL, clock generator, or jitter-cleaner devices, specify the available reference clocks, required output frequencies and counts, maximum rms jitter per output, any need for JESD204 subclass SYSREF generation, and available configuration interfaces such as SPI or I²C.
For fanout and clock buffers, enquiry fields should cover the number of outputs, supported I/O standards, maximum clock frequency, additive jitter, output skew, supply options, and package or footprint constraints. Combining these questions with the jitter budget and topology choices from earlier sections produces a focused short list of oscillator, PLL, jitter cleaner, and fanout devices tailored to the converter clock-tree requirements, while leaving ADC device selection to dedicated pages.
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Clocking & jitter – frequently asked questions
This FAQ collects common long-tail questions around ADC clocking and jitter, focusing on practical limits, concept differences, architecture trade-offs, layout distance, and lab verification so that clock design choices can be tied back to jitter and SNR budgets on this page.
1. How much clock jitter is acceptable for a 14-bit 250MSPS ADC?
For input tones in the 100–150 MHz range, keeping SNR close to the 14-bit limit typically requires total rms jitter in the tens-of-femtoseconds region. That total budget includes external clock jitter, jitter added by the distribution network, and ADC aperture jitter from the datasheet. After subtracting aperture jitter and distribution contributions in rms, the remaining jitter margin for the clock source and PLL is often on the order of a few tens of femtoseconds.
A practical design flow is to use the jitter–SNR equation at the highest intended input frequency, choose an SNR margin below the datasheet value, and then allocate that jitter budget across clock source, PLL or jitter cleaner, fanout stages, and internal aperture jitter as described in the jitter-budget section of this page.
2. What is the difference between clock jitter and aperture jitter?
Aperture jitter describes the uncertainty of the actual sampling instant inside the ADC itself, set by the behaviour of the internal sampling switch, capacitor network, and internal bandwidth. It is a property of the converter architecture and process, and appears in the datasheet as aperture jitter or as a jitter-limited SNR figure. Aperture jitter cannot be improved by changing the external clock; it can only be reduced by choosing a different ADC.
In a complete system the total sampling jitter is the rms combination of external clock jitter, distribution jitter, and aperture jitter. When aperture jitter dominates, further improvements to the external clock yield diminishing returns in overall SNR.
3. Can I use the same clock for multiple ADCs without losing performance?
Daisy-chaining converters or buffers can increase skew and accumulate additive jitter as each stage adds a small amount of noise and uncertainty. For systems that require tight alignment between channels, such as phased arrays or interleaved converters, the distribution network should be designed around low-jitter fanout buffers and minimised skew paths, with daisy-chain structures used only where timing requirements are relaxed.
If a shared reference is noisy or must be distributed over long distances, a local jitter cleaner on each board can regenerate a low-jitter device clock from a common reference before fanout. The total jitter after distribution must still fit inside the jitter budget derived from the target SNR and input frequency.
4. Do low-frequency (kHz) ADC applications care about clock jitter?
In motor-control and power-control applications, where relevant signal content is typically in the hundreds of hertz to tens of kilohertz, picosecond-level total jitter is usually more than adequate. Performance is more strongly influenced by ADC resolution and latency, analog front-end noise, and loop design. For DC and very low-frequency precision measurements with high-resolution sigma-delta or precision SAR converters, jitter is normally not the dominant limitation; sensor noise, reference stability, 0.1–10 Hz noise, and thermal drift are usually more critical.
A reasonable approach is to confirm that clock jitter is small enough that its calculated SNR contribution is several decibels better than the overall SNR target at the highest frequency of interest, and then focus design effort on noise, drift, and linearity rather than chasing ultra-low jitter specifications.
5. How do I convert phase noise plots to rms jitter for my ADC clock?
In practice this process is often handled with vendor tools, spreadsheets, or application notes that approximate the integration based on a few corner points of the phase-noise plot. The key is to choose integration limits that are relevant to the ADC design: low offset frequencies capture long-term wander that may be irrelevant for high-frequency sampling, while very high offset frequencies may lie outside the useful bandwidth of the system. The resulting rms jitter value is then used as the clock jitter term in the jitter–SNR equation and compared against the jitter budget for the highest input frequencies.
When comparing different clock devices, ensure that jitter figures are based on similar carrier frequencies and integration bandwidths, otherwise direct comparison can be misleading. If only integrated jitter is provided, it should still be checked that the vendor’s integration range makes sense for the intended ADC application.
6. Why is my measured SNR worse than the datasheet even with a low-jitter clock?
Analog front-end design is another major factor. Insufficient driver bandwidth, high distortion, noisy amplifiers, or poorly designed anti-alias filters can introduce noise and spurs that reduce SNR. Reference and supply noise, especially on the ADC reference and analog rails, can further degrade performance. PCB layout issues such as shared return paths, coupling between digital and analog traces, and poor decoupling can also introduce additional noise and jitter at the sampling instant.
A systematic approach is to confirm clock jitter against the jitter budget, verify that the ADC is configured and driven similarly to the datasheet conditions, and then review the driver, reference, and layout according to the design hooks and checklist sections. This makes it easier to identify whether jitter, analog noise, or implementation details are the dominant cause of the SNR gap.
7. Is it better to clock the ADC from an FPGA or from a dedicated clock chip?
For mid-bandwidth instrumentation or IF applications, the choice depends on the required ENOB and maximum input frequency. Some newer FPGA families provide reasonably low-jitter PLLs that are adequate for moderate SNR targets, provided that power supply and layout are carefully controlled. For motor control, power control, and many low-frequency measurement tasks, the jitter performance of an FPGA PLL is often sufficient, and system constraints such as latency, pin count, and integration may dominate the decision.
A robust selection process compares the jitter budget derived from target SNR and input frequency with the published jitter performance of the FPGA PLL and of candidate clock chips. If the FPGA solution falls comfortably within the budget and the application is not in the most jitter-sensitive class, it is usually acceptable; otherwise a dedicated clocking IC is the safer choice.
8. How close should I place the clock generator to the ADC?
Routing does not generally create large amounts of random jitter by itself, but poor routing can introduce reflections, crosstalk, and coupling from digital or power nets that show up as timing uncertainty and additional noise at the ADC clock input. Long or meandering traces, plane splits, or multiple unnecessary vias increase the risk of such effects and effectively add to the distribution jitter term.
A practical guideline is to place the generator or fanout buffer within a region that allows short, straight clock traces to each converter, to keep return currents on a solid plane, and to avoid running clock lines adjacent to noisy digital buses. Detailed line length, stack-up, and via strategy are treated in the clocking and PCB layout guidance, which complements this jitter-focused discussion.
9. Can I reuse the SERDES/JESD reference clock as the ADC sampling clock?
In converter systems that use JESD204, clocking devices frequently support both device clocks and SYSREF generation from the same source, which simplifies synchronisation across multiple converters and lanes. When considering reuse of an existing SERDES reference, the design must check whether the available frequencies and divider ratios can produce the required sampling clock without introducing excessive jitter or spurs. If the SERDES reference is noisy or heavily distributed, a local jitter cleaner may be required to regenerate a clean sampling clock for the ADC.
Details such as link subclass, SYSREF alignment, and lane deskew belong to the link-integrity and JESD-focused material. From the clocking and jitter perspective, the main questions are whether the shared reference can meet the combined jitter budget and whether the resulting frequency relationships are compatible with both the converter and the serial interfaces.
10. How do I measure clock jitter in the lab for my ADC design?
A common workflow is to measure jitter at the output of the clock generator or jitter cleaner, compare the results with datasheet specifications, and then measure again near the ADC clock pins to see the effect of the distribution network. For many designs, the most accessible method is to measure ADC SNR as a function of input frequency using FFT analysis and then compare the observed degradation with the predictions from the jitter–SNR relation, which effectively back-calculates an equivalent jitter.
A good measurement plan defines which nodes will be probed, what instruments and bandwidths will be used, and how the measured jitter or SNR data will be mapped back to the design budgets. This allows clocking assumptions from the schematic stage to be confirmed, and gives a clear basis for deciding whether changes are needed in the clock source, PLL configuration, distribution topology, or PCB layout.
