Thermal drift is not “random noise.” It is structured movement driven by self-heating, airflow, and temperature gradients, which changes offset, gain, linearity (INL/DNL), and low-frequency stability over time.

Symptoms that strongly indicate thermal drift

• Warm-up drift: the output moves for minutes after power-on and then gradually settles.
• Step jump: a sudden shift after changing load, sampling rate, interface activity, or power mode, followed by slow recovery.
• Channel spread: multi-channel readings drift apart even when each channel looks “quiet” alone.
• Non-repeatability: INL/SNR results change with airflow direction, board orientation, enclosure state, or ambient swings.

Fast screening checks (10–30 minutes) to confirm “thermal” vs “random”

What this page delivers (engineering outputs)

• Thermal budget that assigns allowable drift to offset/gain/INL and low-frequency stability.
• Layout & airflow rules to reduce gradients and make convection repeatable.
• Repeatable verification plan (warm-up + steps + chamber) with required plots.
• Acceptance criteria expressed in LSB/°C, µV/°C, ppm/°C, and “drift-rate after X minutes.”
• IC inquiry template to request drift curves, methods, and mode-dependent power data from vendors.

Not covered here: clock jitter budgets, JESD/LVDS link integrity, and EMC/ESD protection are handled on dedicated pages.

A useful thermal taxonomy uses two axes: time behavior (slow settling vs step response) and spatial behavior (uniform temperature vs gradients). This classification determines what to log, which tests to run, and which fixes will actually work.

Time drift (how a single channel moves)

• Warm-up settle: monotonic movement until thermal steady state.
• Power/activity steps: sampling rate, interface speed, calibration, or nearby loads change → jump + recovery.
• Ambient ramp: higher dT/dt increases tracking error and short-term instability.

Spatial drift (how channels move apart)

• Board gradients: hotspots near DC/DC, FPGA/SerDes, power stages, or poor heat spreading.
• Package gradients: uneven internal heating and imperfect heat paths to copper and airflow.
• Asymmetry: different copper/vias/airflow across channels creates mismatch that changes with time.

Drift vs noise (engineering decision rules)

Detailed noise-spectrum methods belong to the DC/low-frequency precision page; this page uses time-domain tests to keep thermal drift measurable and fixable.

Thermal effects become actionable only when they are translated into datasheet-style error terms and system metrics. This mapping enables budgeting, targeted tests, and acceptance limits.

Four dominant thermal error terms

• Offset drift → DC reading moves even with a constant input (zero shifts).
• Gain drift → the same stimulus produces different codes at different temperatures (scale changes).
• INL/DNL drift → code edges move and the linearity shape changes over time (not a pure shift).
• Low-frequency noise shift → stability and ENOB at slow bandwidth degrade (drift-like floor rises).

What to observe (forced plots)

How to express acceptance limits (budget-friendly)

• Offset drift: µV/°C or LSB/°C, plus a post-warm-up drift rate over a defined window.
• Gain drift: ppm/°C (span stability) over the operating temperature range.
• Linearity drift: INL change in LSB across temperature, or “code-edge movement” in critical regions.
• Low-frequency stability: ENOB or noise-floor stability at the measurement bandwidth and averaging time.

Not a thermal topic: SNR degradation driven by input frequency and clock quality belongs to the clock-jitter page.

Thermal drift often comes from power-state changes, not from ambient temperature alone. The fastest way to reduce drift is to identify which block changes dissipation and to log mode flags that align with drift steps.

Major heat sources in a data-acquisition chain

• ADC core (sample rate, digital activity, internal references/calibration).
• Reference + buffer (load current and warm-up behavior).
• Input driver (bias current and output swing).
• Digital side (FPGA/SerDes, interface lanes, framing, training bursts).
• Power regulation (DC/DC and LDO losses moving with load).

The “power state machine” that triggers thermal steps

Ownership checklist (what to log to catch the culprit)

• Mode flags: ADC mode, sample rate, calibration enable, interface speed/lane mode.
• Power rails: rail currents (or proxy telemetry) for ADC, FPGA/SerDes, and DC/DC load.
• Thermal sensors: near ADC, near reference, and near the nearest hotspot.

Link integrity is not covered here; only link activity as a heat source is included.

Board-level thermal behavior is dominated by three concepts: path, spreading, and bottleneck. Once the dominant path is visible, hotspots and channel-to-channel gradients become predictable without complex simulation.

The “thermal trio” (engineering meaning)

• Path: the main heat corridor from a hotspot into copper planes, via fields, chassis, or airflow.
• Spreading: how fast heat can fan out once it enters a plane (hotspot gets flattened or stays concentrated).
• Bottleneck: a narrow neck or broken plane that throttles heat flow and creates steep local gradients.

Why gradients form (board patterns that almost always bite)

• Narrow copper necks: heat is forced through a small cross-section → temperature “step” across the neck.
• Long thermal corridors: temperature drops along distance → a stable gradient forms from hot to cold.
• Single-point hotspots: one block (DC/DC, FPGA corner, MOSFETs) dominates → gradients radiate outward.
• Asymmetry: different copper/via density left vs right → channels see different temperature vs time.

Fast board checks (no simulation required)

This section focuses on executable PCB rules; detailed thermal modeling workflows are out of scope.

Placement rules reduce drift by controlling gradients. The goal is to keep the ADC, reference, and driver inside a single cold island while keeping dominant hotspots outside a defined thermal keep-out band.

Cold island rules (same thermal environment)

• Place ADC + REF + Driver together so they share airflow and copper spreading.
• Avoid routing dominant thermal paths through the cold island (no “hot-to-cold” corridors).
• Keep the cold island on a stable copper region with consistent via density.

Keep-away from hotspots (thermal keep-out band)

• Keep the cold island away from DC/DC inductors/MOSFETs and high-power switch nodes.
• Keep the cold island away from FPGA high-activity edges and SerDes regions.
• Draw a keep-out band around hotspot blocks; do not place precision analog blocks inside it.

Multi-channel symmetry (placement + thermal paths)

• Mirror channel placement around a symmetry axis, including copper and via density.
• Match the distance and exposure to hotspots and airflow on both sides.
• Use channel delta as the acceptance indicator for thermal symmetry.

Sensor points (close the loop with measurements)

This section focuses on thermal placement. Signal-integrity routing and ground partitioning belong to dedicated pages.

Airflow must be treated as a repeatable boundary condition, not as “best effort cooling.” Drift becomes hard to reproduce when airflow direction, blockage, or recirculation changes the temperature gradient across the analog region.

Direction rule: cold island first, hot region last

• Route inlet air across the cold island (ADC + REF + Driver) before it reaches hotspots.
• Keep the main exhaust path downstream of heat sources to avoid hot air washing over the analog region.
• Avoid short-circuit paths where inlet air bypasses the board and recirculates locally.

Enclosure pitfalls that break repeatability

• Blockage: harnesses, tall parts, filters, or grilles reduce local flow and create hotspots.
• Recirculation: cavities and poor ducting create vortices that feed warm air back into the cold island.
• Shadowing: inductors/heatsinks create “wind shadows” that change gradients run-to-run.

Production consistency risks (what changes across units)

EMC concerns of fans are out of scope here; this section focuses only on thermal repeatability.

Calibration works best after power and temperature become stable. The most effective drift reduction steps are often power-state discipline and measurement scheduling that avoid thermal steps during critical sampling windows.

Fix the power window during measurement

• Hold sample rate and interface activity constant during the measurement window.
• Keep background processing load stable to avoid hidden power steps.
• If a mode change is required, treat it as a new warm-up event.

Avoid frequent sleep/wake thermal steps

• Duty-cycling creates repeating thermal ramps that change drift behavior run-to-run.
• For low-power needs, use longer steady windows rather than frequent toggling.

Time-division scheduling (move bursts away from critical windows)

• Schedule calibration, self-test, and high-speed transfers outside critical measurement windows.
• Consolidate bursts into dedicated non-critical slots to keep the measurement window thermally quiet.

Warm-up and “steady-state” gates (start measuring only when stable)

Calibration algorithms are out of scope here; stability is the prerequisite.

Drift becomes explainable only when temperature points, ADC codes, and mode metadata share the same time base. This section defines sensor placement, logging rules, and correlation plots that reveal uniform drift versus gradients.

Temperature points (minimum set)

• T1 near ADC: captures warm-up and self-heating effects.
• T2 near reference: correlates strongly with offset/gain drift drivers.
• T3 near hotspot: detects coupling from DC/DC, FPGA edges, or power stages.
• T4 near board edge: acts as an enclosure/airflow proxy (not a perfect ambient).

Same time base (in-system synchronization)

• Log temperature and ADC output through the same logger clock or the same sample/frame counter.
• Record mode changes with timestamps or event indices (rate changes, sleep/wake, cal/test, fan steps).
• Align plots by event edges; correlation without event alignment is unreliable.

Logging rules (required metadata)

Gradient detection: use channel delta

• Channel delta (ChA − ChB) suppresses common drift and amplifies gradients and asymmetry.
• Uniform drift often moves all channels together; gradients show up clearly in the delta plot.

System-wide timestamp distribution (PTP and multi-node sync) is out of scope; only same-logger synchronization is required here.

A strong verification plan turns drift into decision-grade plots. The plan combines warm-up, step response, and temperature chamber tests, then applies consistent acceptance gates based on drift rate, step recovery, and channel delta.

Warm-up test (define “stable” by drift rate)

• Log codes and temperature from power-on until drift rate falls below a defined threshold.
• Extract settling time and post-settle drift rate using a sliding time window.
• Open the measurement gate only after the stability criterion is met.

Step tests (peak + recovery)

• Load step: change load state; observe peak jump and recovery time.
• Rate/mode step: change sample rate or interface activity; measure drift step response.
• Fan step: change fan level; quantify coupling and gradient sensitivity.

Chamber plan (steady points + ramp rate)

• Steady points: hold multiple temperatures; gate each point on low drift rate before sampling statistics.
• Ramp rate: run controlled dT/dt profiles to separate steady drift from transient drift.

Required plots (decision-grade)

Acceptance gates (pass/fail logic)

• Steady-state: drift rate below threshold for the intended measurement duration.
• Step response: peak jump below limit and recovery time below limit after each step.
• Consistency: channel delta within limit across airflow and load conditions.

Frequency-domain FFT details are out of scope; the requirement is to output plots that support a clear decision.

Thermal drift must be converted into acceptance-grade limits that survive production variation. A good spec includes (1) a clear drift expression, (2) guard-bands for environment and build spread, and (3) a fix-priority ladder when margins are consumed.

Choose the right drift expression (when to use each)

Turn drift into a system budget (allocation template)

1. Define the acceptance limit for the measured quantity (DC accuracy, channel match, or drift rate).
2. Allocate a thermal slice inside the system error budget (keep headroom for non-thermal errors).
3. Split the thermal slice into three buckets:
   • Component drift: ADC / reference / driver intrinsic drift.
   • Board gradients: placement asymmetry, hot-zone coupling, bottlenecks, wind shadows.
   • Production spread: fan variance, filter clogging, assembly contact, enclosure tolerances.
4. Set a design target below the acceptance limit so production guard-bands do not consume all margin.

Production guard-bands (what must be covered)

When limits are exceeded: fix in the right order

This section defines system acceptance language (specs and guard-bands). Component choice is handled in the next section.

Selection should start from thermal-related fields, then map each field to a drift risk, and finally generate a vendor inquiry. Part numbers below are examples; acceptance limits and conditions must be verified in the datasheet and in-system tests.

Thermal fields (use as spreadsheet headers)

Risk mapping (fields → symptoms)

Example part numbers (for shortlisting)

Inquiry template (copy/paste to vendors)

This section focuses on thermal-risk fields and procurement questions. Final acceptance limits are defined by the system guard-band and verification plan.