What it is (master-side building blocks)

• HS switch in the pull-up path — controls how VBAT feeds the bus during recessive and transitions.
• Controlled pull-up network (R/diode/RC) — shapes edge rate and robustness vs EMC trade-offs.
• Current limit + fault response — foldback/hiccup/thermal behavior to survive shorts and abuse.
• Diagnostics — fault bits + counters + wake attribution for serviceability.
• Optional hold-up — improves survivability through VBAT dips (crank/start-stop) and brownout recovery consistency.

Not here (route to sibling pages)

• LIN protocol, frames, scheduling → see LIN Master/Controller.
• Slave-side electrical behavior and generic transceiver details → see LIN Transceiver.
• System-level surge/ISO pulse protection stacks (TVS, ISO 7637 planning) → see EMC / Protection & Co-Design.

Pass criteria (placeholders)

• False-wake rate: < X events/day on worst harness + temperature corners.
• Fault recovery: recover to normal bus operation within Y ms after short removal.
• VBAT dip robustness: no stuck-dominant; communication resumes within Z ms after VBAT recovery.

Not here (kept intentionally brief)

Node-count planning, gateway wake policies, and upper-layer diagnostics workflows are referenced only as context and routed to dedicated pages.

Equivalent path (what current actually does)

Model the recessive pull-up path as: VBAT → HS switch (R_DS(on)) → pull-up network (R/diode/RC) → LIN bus. The bus itself is a load dominated by C_BUS (harness + node inputs) plus node leakage and clamp paths. This model is sufficient to locate the dominant contributors to slow edges, margin loss, and repeatability issues.

Quantified knobs (minimum parameter set)

• R_EQ: effective pull-up resistance seen by the bus (includes network + R_DS(on) contributions).
• R_DS(on): HS switch path resistance and its temperature sensitivity (edge/bus-high drift).
• C_BUS: harness + node input capacitance; increases with node count and stub length.
• VBAT corner: low/high supply corners (cold crank vs load dump proximity) that shift current and thresholds.
• I_PK / I_DOM: peak pull-up current vs dominant-phase current; used to sanity-check limit settings.
• Measurement points: V_BAT, V_BUS, and I (shunt/proxy current-limit telemetry) on the same time base.

Direction-only estimates (use for sanity checks)

Measurement hooks (to close the loop)

• V_BAT: record supply corner and dip/recovery edges on the same capture as the bus.
• V_BUS: capture both recessive edges and dominant levels on worst harness and temperature corners.
• I proxy: shunt or device telemetry for current-limit events; correlate to retries and wake anomalies.
• C_BUS surrogate: compare configurations (node count/stub length) as controlled experiments; avoid guessing.

Not here (kept narrow on purpose)

Full transceiver-level waveform specifications and protocol timing rules are routed to the dedicated LIN Transceiver page.

Protection behaviors (describe by outcomes, not vendors)

• Fixed current limit: clamps current; thermal headroom decides survival time under sustained fault.
• Foldback: reduces current after detection; improves thermal survivability but may reduce dominant margin.
• Hiccup (auto-retry): cycles on/off; reduces average power but can create periodic bus disturbances.
• Thermal shutdown: turns off when T exceeds T_SD; recovery depends on hysteresis and cooling conditions.

Digital fields that must be defined (minimum schema)

• I_LIMIT: limit magnitude (and foldback profile if applicable).
• t_LIMIT: time-to-action (and any timers that gate retries).
• T_SD and hysteresis: thermal shutdown threshold and recovery behavior.
• Auto-retry policy: hiccup period, max retries, cool-down requirements.
• Latch/clear conditions: what clears fault state (time, voltage, temperature, register action).
• Counters: over-current count, thermal count, and “recover-to-healthy-bus time” for serviceability.

Design decisions (risk-managed trade-offs)

• Limit too low → dominant level and wake robustness can degrade on worst C_BUS and low VBAT corners.
• Limit too high → higher fault energy and thermal stress; increases risk of post-stress drift and intermittent failures.
• Recovery consistency → define clear conditions and verify “recover-to-healthy-bus” time is bounded (Y ms placeholder).

Not here (system-level compliance)

ISO pulse compliance, load-dump planning, and external protection stack design are routed to EMC / Protection & Co-Design. This section stays focused on current limiting, thermal behavior, and deterministic recovery.

Pass criteria (placeholders)

• Recover-to-healthy-bus: < Y ms after short removal, across temperature corners.
• No stuck-dominant: bus returns to recessive without manual intervention.
• Event attribution: over-current/thermal counters reflect real events (no window/definition mismatch).

Hold-up targets (behavior, not voltage bragging)

• No reset storm: avoid uncontrolled POR/BOD cycles that change wake behavior.
• No false wake cascade: prevent dip/recovery edges from being interpreted as bus activity.
• No missed wake window: ensure recovery timing stays within the expected wake/sleep policy.
• No stuck-dominant: after recovery, the bus must return to a healthy recessive state.

Minimum sizing framework (direction-only)

This estimate is for sizing direction only; final behavior must be verified on a real dip/recovery profile with synchronized logging.

What to measure & record (minimum dataset)

• Brownout threshold: BOD level and hysteresis; document the effective threshold in-system.
• Reset reason: POR / BOD / WDT; avoid “unknown reset” classifications.
• Dip profile: VBAT min, duration, recovery slope; capture VBAT and VDD on the same time base.
• Post-recovery bus state: stuck-dominant check + recover-to-healthy-bus time (Y ms placeholder).

Not here (power-domain strategy)

Detailed SBC power-domain policies, watchdog architecture, and reset-tree design are routed to SBC integrating LIN. This section stays focused on hold-up sizing, brownout thresholds, and post-dip bus behavior.

Pass criteria (placeholders)

• Recover-to-healthy-bus: < Y ms after dip recovery, across temperature corners.
• No false wake spike: false-wake rate remains < X/day during dip/recovery campaigns.
• Reset attribution: POR/BOD/WDT classification matches observed thresholds and timing (no ambiguity).

Wake sources (master-side attribution only)

• Bus wake: activity detected by a bus comparator; sensitive to edge noise and dip/recovery artifacts.
• Local wake: local input/event triggers a wake; must be distinguishable from bus-triggered wakes.
• Timer/gateway wake: scheduled wake; should produce an explicit reason code for diagnostics.

Digital definitions (minimum vocabulary)

• Wake reason code: fixed enumeration for bus/local/timer; must be stable across software versions.
• Wake filter window: time window and rule set used to accept/reject activity as a wake event.
• Debounce: minimum persistence requirement that suppresses spikes and ringing artifacts.
• Bus activity counter: defined counting window and conditions (avoid denominator mismatch across logs).

False-wake triage path (repeatable)

1. Bucket by reason: group events by wake reason code (bus/local/timer) before any hypothesis.
2. Layer by conditions: temperature, harness configuration, node count, and VBAT dip profiles.
3. Align window definitions: filter window, debounce, and counter windows must match across logs.
4. Correlate to captures: bus waveform + event log on the same time base to confirm the root bucket.

Not here (other bus ecosystems)

CAN partial networking is a CAN subsystem topic and is intentionally excluded from this LIN master page.

Pass criteria (placeholders)

• False wake: < X events/day across temperature and harness corners.
• Attribution coverage: 100% of wakes have a valid reason code (no “unknown wake”).
• Counter consistency: bus activity counter uses a fixed window and definition across builds.

Knobs available on the master side (minimum set)

• Slew control: controls dv/dt on edges; trades EMI vs sampling margin and wake sensitivity.
• Pull-up strength: effective R_EQ and pull-up current; trades margin vs emissions and fault energy.
• Transition shape: dominant↔recessive behavior influenced by HS switch behavior and shaping components.
• RC/diode paths: used to damp ringing/overshoot or provide a controlled fast path (describe by behavior).

Harness / C_BUS coupling (what changes in the field)

Treat C_BUS as a real system variable. Verify final behavior on representative harness configurations, not only on a bench short cable.

Knob-to-effect rules (directional)

• Slew slower → EMI ↓ ; margin may ↓ on high C_BUS corners; wake sensitivity often improves.
• Pull-up stronger → margin ↑ ; EMI ↑ ; fault energy ↑ (short events become harsher).
• RC shaping stronger → ringing ↓ ; EMI ↓ ; over-shaping risks long tails and sampling issues.
• Symmetry drift (temp/VBAT) → window narrows; verify both edges and steady levels across corners.

Required A/B comparisons (minimum experiment matrix)

• Short vs long harness: compare edges, overshoot/undershoot, retries, and bus activity counts.
• Cold vs hot: include pull-up strength drift and symmetry changes; log error/retry statistics.
• Few vs many nodes: treat node count and stubs as a controlled variable for C_BUS.
• Same time base: waveform capture and counters must share a synchronized timestamp window definition.

Not here (external protection selection)

TVS arrays, common-mode chokes, and protection/termination component selection details are routed to EMC / Protection & Co-Design. This section stays on master-side knobs and measurement closure.

Recommended diagnostic set (grouped)

Serviceability rules (hard requirements)

• Every wake has a reason: no “unknown wake” category allowed.
• Every fault has clear rules: time/voltage/temp/register conditions must be defined.
• Windows are defined: counter windows and filter windows must be documented and stable.
• Events are time-aligned: timestamp (or window id) must enable correlation with waveform capture.

Safety hooks (hooks only, not a full safety case)

• Fault injection points: exercise OC, brownout, stuck dominant, and wake filters in validation.
• Coverage thinking: detect → record → recover; ensure each step is observable.
• Independent monitoring hook: correlate reset reason and wake reason for consistency checks.

Pass criteria (placeholders)

• False wake: < X/day (across temperature and harness corners).
• OC recovery success: > Y% (defined as recovery to healthy bus within Z ms).
• Post-brownout recovery: communication restored < Z ms after recovery.

Not here (upper-layer diagnostics)

Upper-layer UDS/DoIP procedures and network-management workflows are routed to gateway/diagnostics pages. This section stays on device-level bits, counters, and event logging.

Placement priorities (master-side only)

• Interface zone first: keep connector-facing protection and the LIN pin loop short to control parasitics.
• HS switch + pull-up network close to LIN: treat the pull-up path as part of the waveform, not “just power.”
• Decoupling close to the active domain: keep high di/dt return currents away from wake/fault sensing references.

Return paths & partition (predictable current loops)

Do not diagnose from the wrong place: waveform and return path behavior must be checked near the LIN pin, not at a distant node.

Measurement hooks (minimum set)

• VBAT: capture dip/recovery profiles that can trigger protection or reset chains.
• VDD: correlate brownout thresholds to reset reason and bus symptoms.
• LIN (near pin): validate edge/overshoot where parasitics are actually applied.
• FAULT: latch timing for OC/thermal events; prevents “silent” degradations.
• WAKE: attribute false wakes to bus vs local sources.
• Reset reason strap/state: POR/BOD/WDT attribution must be observable and consistent.

Typical pitfalls (fast checks)

Not here (full EMC parts and clauses)

Detailed EMC component parameters and standard clause mapping are routed to EMC / Protection & Co-Design. This section focuses on master-side placement, returns, and measurement hooks.

Three-stage funnel (what each stage proves)

• Stage 1 — Bench (short cable): tune knobs into a stable region and freeze measurement windows and counters.
• Stage 2 — Harness (representative): validate C_BUS sensitivity on worst length and max node count.
• Stage 3 — Vehicle (real disturbance): validate wake/hold-up/reset attribution under VBAT dips and temperature corners.

Correlation rules (time-base hard rules)

• One time base: waveform capture window = error/retry counter window = wake window.
• Wake event schema: timestamp + reason code + window id (no ambiguous wake bucket).
• Reset attribution: reset reason must correlate to VBAT/VDD threshold evidence.
• Fixed denominators: define the denominator of “rate” metrics (per time, per frame, per window).

Minimum must-do checklist (do not skip)

• Cold/hot: capture symmetry drift and margin changes across temperature corners.
• Low/high VBAT: include dip/recovery profiles; correlate to reset and wake attribution.
• Max nodes + worst harness length: treat C_BUS as a controlled worst case.
• Repeated wake cycles: stress wake filters and counters; quantify false wake rate (X/day placeholder).

Stage gates (placeholders)

Vehicle failure triage (first order)

1. Reset reason + VBAT/VDD: confirm whether brownout/reset changed bus behavior.
2. Wake reason + filter window: bucket false wakes by bus vs local vs timer sources.
3. LIN waveform at the pin: check edge/tail/ringing on the real harness corner.
4. Counters and denominators: ensure retry/error metrics use fixed windows and definitions.

Not here (production ATE station details)

Detailed ATE station design and factory test workflows are excluded here. This section defines bench-to-vehicle validation stages and time-aligned correlation rules.